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Power Minimisation of VLSI Wave Digital Filters through Systolic Block Size Selection P. Israsena and S. Summerfield Division of Electronic and Electrical Engineering School of Engineering University of Warwick, Coventry, CV4 7AL, UK

Abstract Systolic architectures for Wave Digital Filters are investigated for low power applications. Based on a 3-port adaptor implementation of the 2nd order section, minimum power is found using pipelining with a 2-bit block size for which the power consumption is reduced by 50 % and the power-area-delay performance increased by 5 times relative to the starting, non-pipelined implementation.

Introduction Wave Digital Filters, especially the Lattice forms which are a Parallel Combination of Allpass Subfilters (PCAS), are becoming established for various signal processing applications [1,2]. Because of their low coefficient sensitivity and regularity the filters are ideal for VLSI implementation. In earlier work, the 2-port adaptor had been employed to realise the 2nd order section - the filter’s fundamental building block. Recent work, however, suggests the superiority of a 3-port implementation especially in term of speed [3]. With an increasing demand for portability, low power implementation of the filters is now relevant. This letter explores the effect of different levels of pipelining on the area, speed and power.

Pipelined architectures The 3-port adaptor implements the 3 functions:

y1 = x1 − γ 1 (x 2 − x1 − x3 )

(1a)

y 2 = − x 2 − γ 2 (x 2 − x1 − x 3 )

(1b)

y 3 = x 2 − x1 − x3 − y1 − y 2

(1c)

If x1 (t ) = y1 (t − 1) and

x 2 (t ) = y 2 (t − 1) then y3/x3 is a 2nd order all pass function [2]

with –2