0.5 V Supply Resistorless Voltage Reference for Low Voltage Applications Renato Campana V.
Hamilton Klimach
Sergio Bampi
PGMicro - Graduate Program on Microlectronics Federal Univ. of Rio Grande do Sul. Porto Alegre, Brazil
PGMicro - Electrical Engineering Department Federal Univ. of Rio Grande do Sul Porto Alegre, Brazil
PGMicro - Informatics Institute Federal Univ. of Rio Grande do Sul Porto Alegre, Brazil
[email protected]
[email protected]
ABSTRACT The analysis and design of a resistorless sub-bandgap voltage reference using a Schottky diode instead of a bipolar junction is presented. It is a self-biased circuit and works in the nano-ampere current consumption range at a supply voltage as low as 0.5 V. The design is validated through post-layout simulation results for a 130 nm CMOS technology, including process variability analysis. A voltage reference around 240 mV is achieved for VDD = 1.2V , with a temperature coefficient TC of 43 ppm/◦ C in the range from -40◦ C to 120◦ C and 192 ppm/◦ C with VDD = 0.5V in the same temperature range. The current consumption is 276 nA for VDD = 1.2V at 27◦ C, and the silicon area is 0.0016 mm2 for the entire reference.
Categories and Subject Descriptors B.4 [Very Large Scale Integration Design]: Analog and Mixed-Signal Circuits—Analog and mixed-signal circuit optimization
General Terms Theory, Design, Performance
Keywords Sub-Bandgap voltage reference, low supply voltage, Schottky diode, ultra-low power.
1.
INTRODUCTION
The Bandgap Reference (BGR) circuit is an essential block of several analog and mixed-signal circuits such as data converters, voltage regulators and phase-locked loops [1], [2]. This reference, introduced by Widlar in 1971 [3], uses the complementary-to-absolute-temperature (CTAT) characteristic of the forward voltage drop across a PN junction and
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[email protected]. SBCCI August 31 - September 04, 2015, Salvador, Brazil © 2015 ACM. 978-1-4503-3763-2/15/08 $15.00. DOI: http://dx.doi.org/10.1145/2800986.2800987
[email protected]
linearly combines it with the proportional-to-absolute temperature (PTAT) characteristic of the voltage difference between two PN junctions with different current densities, to obtain a temperature independent output voltage [4], ideally independent of the load, power supply, and fabrication process variability. The traditional topology circuit offers an output voltage around 1.2 V. Taking advantage of the parasitic bipolar transistors in CMOS technology this bipolar voltage reference circuit was adapted for use in CMOS circuits [1]. However, the continuous scaling of transistors dimensions in combination with the need to reduce power consumption in large digital ICs is driving down the supply voltage for nanoscale CMOS technologies [4], since is the most efficient way to reduce the power consumption of digital circuits (the 2 [5]). For this dynamic power density is proportional to VDD reason, supply voltages well below 1V and even down to 0.5V for low voltage and low power (LVLP) applications are projected in the ITRS roadmap [4], [5]. Since digital and analog circuits are usually together in mixed-signal integrated circuits, the aforementioned circuits and systems must operate more and more under LVLP conditions [2], [6], and special techniques should be used to design them. Recent research has demonstrated the feasibility of designing analog and RF circuits that can operate with low supply voltages around to 0.5 V [4], [7], [8], [9], [10], [11], [12]. In the case of the traditional bandgap voltage reference, with an output voltage (VREF ) near to 1.2 V which exceeds the sub 1 V supply voltage, several alternative circuit topologies have been proposed to overcome that limitation. Some of these new circuit topologies are still based on the bandgap principle and generate an output voltage equal to a fraction of the 1.2V [2]. But, for these cases, the minimun supply voltage cannot be lower than the forward biased PN junction voltage (about 0.6 V) [13]. Some of these circuits operate with supply range from 0.85 V to 0.9 V [14], [15], [16], [17], or around 0.75 V [18]. MOS-only voltage references, on the other hand, can operate at lower supply voltages and are not bound by the limitations due to the forward biased PN junction voltage. Most designs exploit the negative temperature dependence of the MOS threshold voltage and combine it with a PTAT characteristic, which can be obtained with MOS devices biased in the subthreshold region. Some high performance voltage references operating down to 0.85 V voltage supply have been reported in [2], [13], [19], [20], [21].
In this work, we suggest to replace the PN junction used in a sub-bandgap reference proposed in [20], by a CMOScompatible Schottky diode, since the forward biasing voltage of this device for the same current density level is much lower than the PN junction, which impacts in additional power supply reduction. This paper is organized as follows: after the introduction, the basic operation principle of the proposed circuit is shown in section II. A compact MOSFET model is presented and applied to the circuit in section III. Section IV is dedicated to develop the design methodology of the circuit. Simulation results are presented in section V and finally, in section VI some conclusions from this work are drawn.
2.
CIRCUIT OPERATING PRINCIPLE
The circuit topology circuit was proposed in [20] and it is shown in Fig.1, but using a Shottky diode instead of the traditional bipolar transistor (BJT). In the original circuit, the forward bias voltage (usually from 0.5 to 0.6V ) imposes a limit for the minimum supply voltage (VDDmin ), as can be seen through the voltage critical path MP8-BJT. Using a Shottky diode this critical path can work at a lower voltage because the diode forward voltage is reduced to around 0.2 to 0.3V . VDD MP9
MP10
MP11
MP8
MP12
MN3
MN5
MN7
VREF VD
MN2
MN4
MN6
IDSH MN1
+ VGS1
Figure 1: Voltage Reference Schematic Diagram
Figure 3: Vdiode vs temperature curve for the 2µm x 2µm Schottky Diode, with Idiode =60 nA
MN1 and MN2 gate-source voltages and consequently their drain current since they are in series, defining the Schottky diode current IDSH , through a feedback path that uses a current mirror to bias the diode (MP8 and MP9). Since the MN1 and MN2 transistors have the same current, and assuming that they have the same aspect ratio, the diode voltage appears divided by two at the gate of MN1. This voltage is then added to a PTAT voltage generated by three self-cascode structures in cascade, composed by MN2-MN3, MN4-MN5 and MN6-MN7, to provide a temperature independent output VREF . Fig. 2 shows the forward I-V curves of two different alternative devices used at the node voltage VD in Fig. 1: two Schottky diodes as shown (with differents geometries), and the conventional vertical bipolar pnp transistor connected as a diode, at 27◦ C. Under a forward voltage below 0.50 V, the emitter current of the bipolar transistor is on the order of hundreds of pAs, which could result in significant errors when compared to the drain and source leakage currents [20], thus imposing a severe constraint for the minimum power supply voltage. In the same Fig 2, the curves of the Schottky diodes can work in the 0.2-0.3 V interval with currents from tens to hundreds of nanoamperes, thus constituting an advantage over the bipolar device when the target is the operation under very low supply voltages. Fig. 3 shows the Schottky diode voltage over temperature characteristics when biased with Idiode = 60nA for which the forward voltage is 0.25 V at room temperature. Through this figure one can see that this device presents a CTAT behavior like the PN junction, with a temperature dependence around δVD /δT ≈ −1.5mV /◦ C.
3. 3.1
CIRCUIT ANALYSIS The UICM Model
The Unified Current Control Model UICM [22], has proven to be an important tool for circuit design due to its accurate modelling of MOSFETs through any inversion level. From this model the drain current of a long channel MOSFET is expressed as ID = IF − IR = ISQ (if − ir )S Figure 2: I-V curves for the Schottky Diodes and the Bipolar Transistor
The equilibrium of the bias condition of the circuit can be understood as follows. The diode voltage establishes the
(1)
where IF and IR are the forward and reverse components of the current, if and ir are the forward and reverse inversion coefficientes (or ’levels’) and S = W/L is the active area aspect ratio, where W and L are the MOSFET width and lenght, respectively. ISQ is a process related parameter called ’sheet specific current’ being defined as
0
ISQ = µCox n
φ2t
(2) 2 where n is the subthreshold slope factor, µ is the channel effective mobility (both slightly dependent on the gate 0 voltage), Cox is the gate capacitance per unit area and φt = kB T /q is the thermal voltage, where kB is the Boltzmann’s constant, q is the electronic charge, and T is the absolute temperature. When the transistor is saturated, the reverse current IR is neglibible with respect to the forward current IF and the drain current is almost independent of the drain voltage, i.e. ID ≈ IF = ISQ Sif
If both transistors are biased in weak inversion (if < 1), the F (if ) therm of Eq. (4) can be approximated by a Taylor i expansion given by F (if ) ≈ −1 + ln( 2f ), and applying that to the last Eq. we have VDSdown = φt ln
3.2
Self-Cascode
The association of two MOSFETs as in the Fig. 4, where Mup operates in the saturation region and Mdown operates in the triode region, is called the Self-Cascode (SC) circuit and generates a PTAT voltage in the VDSdown , when the transistors are biased in the subthreshold region.
(6)
IDup = KIref = ISQ Sup if up Iref = ISQ Sup
The relationship between the inversion levels and the terminal voltages is the UICM equation given by
where VS(D) is the source (drain) voltage, referred to the bulk terminal. VP is the pinch-off voltage, defined as VP = (VGB − VT )/n, where VT is the threshold voltage. The transistor operates in weak inversion for if < 1, in strong inversion for if > 100, and in moderate inversion for 1 < if < 100. More details about the UICM model can be found in [22].
Now, applying the Eq. (1) to this circuit, one can obtain the following equations for the transistor currents in terms of the inversion levels
(3)
p p VP − VS(D) = F (if (r) ) = 1 + if (r) −2+ln 1 + if (r) (4) φt
if down if up
if up K
(7)
IDdown = (K + Z)Iref = ISQ Sdown (if down − irdown ) (8) Since in this circuit if up = irdown , Iref is given by Eq. (7), and applying it to Eq. (8) results Z Sup if down =1+ 1+ if up K Sdown
(9)
Now replacing the last statement in the Eq. (6) finally results Z +K Sup VDSdown = φt ln 1 + (10) K Sdown As one can see in the last equation, the SC performs as a PTAT generator circuit if the transistors Mup and Mdown are biased in the subthreshold region, with VDSdown typically less than a hundred milivolts [20].
3.3
Voltage Reference Circuit
According to the circuit of Fig. 1, the reference voltage (VREF ) that results in the output node can be expressed through the voltage drop acroos MN1 added to the SC PTAT voltages
KIREF
MUP
ZIREF
VREF = VDS6 + VDS4 + VDS2 + VGS1
MDOWN
Figure 4: Self-Cascode circuit When two MOS transistors share the same gate voltage (VG ), both have the same pinch-off voltage (VP ), so applying Eq. (4) to the Mdown transistor results in the following expression for its drain-source voltage VDSdown = φt [F (if down ) − F (irdown )] As both transistors share the same gate voltage and the source of Mup is tied to the drain of Mdown , then if up = irdown , so the last Eq. can be rewritten as VDSdown = φt [F (if down ) − F (if up )]
(11)
Since the same current flows in M1 and M2, and they have approximately the same aspect ratio, their gate-source voltages is almost equal, resulting that VGS1 ≈ VD /2, being VD the Schottky diode voltage. By applying Eq. (10) the last equation (11), and remembering that the current mirrors (MP8-MP12) have the same aspect ratio, so ID6 = 2ID7 , ID4 = 3ID5 and ID2 = 4ID3 , then the VREF results as:
(5)
VREF = φt ln
1+2
S7 S6
1+3
S5 S4
1+4
S3 S2
+ VD /2
(12) where the first term of the equation represents the PTAT voltage and the second one (VD /2) presents the CTAT behavior. Such as mentioned before, since δVD /δT ≈ −1.5mV / ◦ C, so through the Eq. (12) it is possible to verify that temperature compensation of VREF can be performed with a proper sizing of devices S2 − S7 to provide a positive δVP T AT /δT ≈ 0.75mV /◦ C, making this VREF temperature independent [20], [6].
DESIGN PROCEDURE
According to the section II and Fig. 1, the Schottky diode inclusion through the voltage critical path MP8-diode reduced the limit for the VDDmin . From Fig. 2 one can see that when this device of 2µm x 2µm anode size is biased with IDSH = 60nA the diode voltage results VD ≈ 250mV and the supply voltage could be reduced to 350 mV ( 250mV + 100mV of VSDsat ) , when compared to a junction diode based sub-bandgap reference. The aspect ratios of MP8-MP12 were chosen to be equal to improve layout aspects and matching. They are all biased in weak inversion so they have a minimum saturation voltage around VSDsat ≈ 100mV . The chosen inversion level for these transistors was if p =0.2, resulting the aspect ratio (16/2) for all PMOS according to Eq. (3), being the specific current around ISQP ≈ 32nA for the standard PMOS transistors in this technology. From Fig. 1 one can see that the proposed circuit uses three self-cascode structures to provide the PTAT voltage, composed by MN2-MN3, MN4-MN5 and MN6-MN7 respectively, and from section III they must be biased near the subthreshold condition to operate as PTAT generators (in fact the SC also works as a PTAT circuit when the transistors are biased in strong inversion, but only if both are kept under constant inversion levels). Since under the chosen bias condition and 27 ◦ C the forward Schottky diode voltage is ≈ 250 mV, and the VGS1 is around half of that voltage, the total PTAT voltage that must be added by the SC circuits to compensate the diode CTAT dependence is ≈ 125 mV, resulting a final reference voltage around 250 mV. The chosen PTAT voltages of each SC were around 35 mV for the first one and 45 mV for the last ones, resulting the inversion levels around if 2 = 0.4, if 3 = 0.3 for the first SC and if 4,6 = 3, if 5,7 = 1 for the last two. From Eq. (3) the SC transistors aspect ratio can be calculated, resulting the values shown in table I. We determinated the specific current to be around ISQN ≈ 200nA for the standard NMOS transistors in this technology. The final sizing is presented in Table I after some size adjustments that were done from circuit simulation. All the PMOS transistors have the same aspect ratio and, it chosen Schottky diode anode size is 2µm x 2µm, since according to Fig. 2, is the minimum size for the foundry-characterized Schottky diode, and which the minimum current consumption.
5.
MN1 17 5
MN2 15 5
MN3 4.5 5
MN4 1.5 5
MN5 1.5 5
MN6 1 5
MN1
MN2
MN3
MN4 MN5
MN6 MN7
Schottky Diode
35 µm
Figure 5: Voltage Reference layout
Figure 6: Voltage Reference vs. Temperature with VDD = 1.2V
Figure 7: Voltage Reference vs. Supply Voltage for 27◦ C
Table 1: MOSFETs SIZING
W (um) L (um)
MP8-MP12
45 µm
4.
MN7 1.5 5
MP 16 2
SIMULATION RESULTS
The results presented in this section are from post-layout simulations. The layout is shown in the Fig. 5 and the occupied area is 0.0016 mm2 . Fig. 6 shows the temperature dependence of the output reference voltage with a supply voltage of VDD = 1.2V The voltage reference value varies between 237mV and 239mV for a temperature range from -40◦ C to 120◦ C. The effective temperature coefficient (T CEF F ), as given
by Eq. (13) [20], is 43 ppm/◦ C for VDD = 1.2V and 192 ppm/◦ C for VDD = 0.5V , both inside a very wide temperature range from -40◦ C to 120◦ C. T CEF F =
VREF max − VREF min (Tmax − Tmin ) VREF (27◦ C)
(13)
Fig. 7 shows the reference voltage dependence on the supply voltage, or VDD vs. VREF . From this figure, one can see that the minimum supply value VDDmin is around 0.4 to 0.5 V. One finds that this voltage reference circuit does not have low line sensitivity (LS). The analysis of the circuit sensitivity to the fabrication variability effects was done through Monte Carlo simulation, that was performed separately for ’mismatch’ and for
’process’ variations, with 1000 runs each. These simulations are shown in Fig. 8. Through these figures, one can see that the larger sensitivity of the circuit relies on process variation effects, reaching a maximum of 81 mV over the typical VREF ≈ 240mV for a 3σ requirement. Process variations impact is larger in MOSFETs biased in subthreshold region [20] like the ones used in this reference circuit to save power. According to Eq. (12), the VGS1 term represents the CTAT voltage that results from the combination of the diode characteristics with the MOSFETs characteristics, including the threshold voltage VT , which is a parameter that presents large process variability in state of the art CMOS technologies [6].
(a)
that the cited Voltage References operate with smaller temperature ranges, and some of them use trimming [21]. If a higher TC can be tolerated, the VDDmin can be reduced to VDD = 0.45V , resulting a TC=210 ppm/◦ C. Our Voltage Reference design for very low VDD does not use any trimming strategy yet. Finally, the total power consumption is less than 330 nW for the overall supply voltage range, at room temperature.
6.
CONCLUSIONS
In this paper we proposed a resistorless voltage reference circuit that uses a Schottky diode instead of a junction diode, since with that inclusion, the circuit can operate with supply voltage as low as 0.5 V. It was analysed using a consistent MOSFET model that is valid from weak to strong inversion condition and design equations were derived. A design methodology was proposed and validated through the implementation of the circuit in a standard 130 nm CMOS process, where post-layout simulations include process and mismatch variability effects analysis. A voltage reference of 239 mV was achieved for a supply voltage of 1.2 V, with temperature coefficients of 43 ppm/◦ C in the range from -40◦ C to 120◦ C and 192 ppm/◦ C with VDD = 0.5V in the same temperature range. The current consumption is 276 nA with VDD = 1.2V at 27◦ C, and the chip area is 0.0016 mm2 . Improvements are necessary to increase PSRR and reduce line sensitivity. A trimming technique may be also necessary to deal with the large process sensitivity, possibly including diode curvature compensation. The circuits were sent to fabricated. It expected those prototypes for test measurements.
Acknowledgment The authors acknowledge the IC-Brazil Program for CAD tools, the CNPq and CAPES for financial support, and MOSIS for silicon prototyping. (b)
( c)
Figure 8: VREF Monte Carlo results for (a) mismatch, (b) process and (c) total variability A comparison among a few low supply Voltage References and the proposed circuit is presented in Table II. The smallest silicon area can be one of the greatest advantages of this circuit in comparison with the other ones. One can see also
7.
REFERENCES
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Table 2: PERFORMANCE COMPARISON OF THIS WORK TO OTHER LOW SUPPLY VOLTAGE REFERENCES
Tech. Voltage reference type Comments Temp. Range Minimun VDD VREF T.C. (ppm/◦ C) Power PSRR (dB) @ 1 kHz LS (mV /0.1V ) Area (mm2 )
This work 130 nm Schottky
[4] 90 nm Schottky
[13] 110 nm VT O
Simulated −40◦ to 120◦ 500 mV 239 mV @ VDD = 1.2 V 216 mV @ VDD = 0.5 V 43 @ VDD = 1.2 V 192 @ VDD = 0.5 V 330 nW @ VDD = 1.2 V 113 nW @ VDD = 0.5 V 32 @ VDD = 1.2 V 27 @ VDD = 0.5 V 32.8 0.0016
Measured 0◦ to 100◦ 550 mV 247 mV
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Measured 10◦ to 90◦ 242 mV 195.6
[18] 130 nm Bipolar and switched capacitor Measured −25◦ to 85◦ 0.75 184.84
Measured −25◦ to 85◦ 0.7 438.7
270
134
40
22.11
358 uW
5.35 uW
170 nW
19 nW
N/A
N/A
40
N/A
3 0.059
0.8 0.013
N/A 0.07
0.571 0.041
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[21] 180 nm VT O
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