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USO0RE41719E

(19) United States (12) Reissued Patent

(10) Patent Number:

Kinzer et al. (54)

US RE41,719 E

(45) Date of Reissued Patent:

POWER MOSEET WITH INTEGRATED

(58)

Sep. 21, 2010

Field of Classi?cation Search ................ .. 257/34l,

DRIVERS INA COMMON PACKAGE

257/401, 666, 723, 676, 782, 672, 724, 691,

257/685, 497, 773, 901, 109, 904, E23.079, (75) Inventors: Daniel Kinzer, El Segundo, CA (US); Tim Sammen’ Empingham (GB); Mark Pavier, Felbridge (GB); Adam Amali, Hawthorne’ CA (Us) (73)

257/1323-153 See application ?le for complete search history. (56) References Cited US. PATENT DOCUMENTS

Assignee: International Recti?er Corporation, El Segundo’ CA (Us)

5,084,753 A * 5,289,061 A * 5,313,095 A

*

5/1994

(21)

Appl. No.: 11/183,302

5,792,676 A 5,814,884 A

* *

8/1998 Masumoto et a1. 438/111 9/1998 Davis et a1. ............... .. 257/723

6,066,890 A

*

5/2000

(22)

Filed:

6,133,632 A

* 10/2000 Davis et a1. ..... ..

.

Jul. 15, 2005

6,388,319 B1 * 6,448,643 B2 * 2001/0012189 A1 *

Related U's' Patent Documents

Reissue of:

(64)

_

Tsui et a1. ................. .. 257/723

_

* med by examlner

Issued:

Jul. 15, 2003

Primary ExamineriTram H Nguyen

Appl. No.: Filed:

10/138,130 May 2, 2002

(74) Attorney, Agent, or FirmiFarjami & Farjami LLP (57) ABSTRACT

Pr0v1s10na ' ' 1

' appl'1cat10n

N 0. 60/288193 , , ?l e d

on

A driver stage consisting of an N channel PET and a P chan nel FET are mounted in the same package as the main poWer FET. The poWer PET is mounted on a lead frame and the

M ay 2 ,

Int_ CL H01L 29/76 H01L 29/9 4 H01L 31/062 H01L 31/113

(200601)

driver FETs are mounted variously on a separate pad of the lead frame or on the main FET or on the lead frame tenni

(200601) (200601) (200601)

nals. All electrodes are interconnected Within the package by mounting on common conductive surfaces or by Wire bond ing. The drivers are connected to de?ne either an inverting or

non-inverting drive. (52)

257/723

Cheah et a1. .... .. 257/723 Cheah et a1. .... .. 257/723 Tang ......................... .. 361/56

6,593,622

2001.

(51)

5/2002 9/2002 8/2001

Tagawa et al. ............ .. 257/672

Patent No.2

U.S. Applications: 60

1/1992 Goida et al -------------- -- 257/685 2/1994 Sugibayashi et a1. ...... .. 327/434

US. Cl. ..................................................... .. 257/341

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12 Claims, 6 Drawing Sheets

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US. Patent

Sep. 21, 2010

Sheet 5 of6

US RE41,719 E

WW3)

FIG. 6

DRIVER l/ P

F! G. 8

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US RE41,719E 1

2

POWER MOSFET WITH INTEGRATED DRIVERS IN A COMMON PACKAGE

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a non-inverting con?gura tion for an integrated driver and power MOSFET. FIG. 2 is a top view of a ?rst embodiment of a dual pad lead frame and the three die forming the circuit of FIG. 1. FIG. 2A is a cross-section of FIG. 2, taken across section line 2ai2a in FIG. 2. FIG. 3 is a top view of a second package embodiment,

Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue speci?ca tion; matter printed in italics indicates the additions made by reissue. RELATED APPLICATION

using an internal isolating substrate on a common lead frame

This application claims the bene?t of US. Provisional

pad.

Application No. 60/288,193, ?led May 2, 2001.

FIG. 3A is a cross-section of FIG. 3 taken across section

FIELD OF THE INVENTION This invention relates to semiconductor devices and more speci?cally relates to a power MOSFET device with driver FETs integrated into or copacked with the same package to provide drive current to the gate circuit of the power MOS FET.

BACKGROUND OF THE INVENTION

20

Power MOSFETs frequently require a high gate current

pulse for their operation. For example, circuits containing control or synchronous power MOSFETs frequently require a high gate pulse current for their operation. As a speci?c example, high frequency dc to do converters such as syn chronous buck converters are operated in the region of 3 MHZ and above, at breakdown voltages of about 30 volts and below. The gate driver current ig for the control and synchro nous MOSFETs of those circuits is determined, approxi

mately by:

con?guration for the device of the invention. 25

30

35

to 10 ns, the switching current can therefore be of the order

1.4A. This poses a problem for control ICs where capability to deliver this current level is not economically viable, given manufacturing complexity versus chip area required.

FIG. 8 is a top view of a lead frame and die for implement ing the circuit of FIG. 7 with the driver FET insulated from the lead pad by a passivation layer as in FIG. 3. FIG. 9 is a top view of a further embodiment of lead frame and die to implement the circuit of FIG. 7 with the two driver FETS integrated into a single die, as in FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

For a typical SO-8 packaged device such as the

IRF7811W made by the International Recti?er Corporation, the gate charge Qg required to turn on the MOSFET is in the region of 14nC. If the MOSFET turn on time tON is limited

line 3ai3a in FIG. 3. FIG. 4 is a top view of a third embodiment for the three die and a lead frame. FIG. 5 is a top view of a fourth embodiment for the pack age. FIG. 6 is a top view of a ?fth embodiment in which the two driver FETS are integrated into a common integrated circuit. FIG. 7 is a circuit diagram of an inverting driver circuit

40

FIG. 1 shows a circuit in which two small MOSFETs, P channel MOSFET 2 and N channel MOSFET 3 act as driv ers for a main N channel MOSFET 1. All MOSFETs are

vertical conduction devices, although other structures could be used. Further, the MOSFETs 1, 2 and 3 could be replaced by other types of transistors, as desired. A single input line 23 from a suitable driver integrated circuit (Driver I/ P) is connected to gates G2 and G3 of MOS FETs 2 and 3 respectively. The sources S2 and S3 of FETS 2

Solving this problem has typically been addressed by the

and 3 respectively are connected to a common node and to

addition of separate driver ICs placed in circuit between the control IC and the MOSFETs. As switching frequencies

G1 of MOSFET 1. Input power terminal UP and output

increase, the layout related circuit ef?ciency of this approach reduces, and the parasitic inductances caused by the distance between the separate components cause higher losses during

power terminal O/P are connected as shown with respect to 45

switching.

MOSFET 1 may be a die having an area of 70>< 15.75 mils and an on resistance of 250 mohm. N channel

Thereafter, wirebonds are formed between bond pads on

die 1, 2 and 3 and the pins GND/ S1 and IN (23) in order to form the connections of the circuit of FIG. 1. The bond wires

FET 3 may have a siZe of 23.6>