Plot 2, Bayan Lepas Technoplex Industrial Park. Mukim 12, S.W.D., 11900 Penang, Malaysia. Abstract-This paper will describe the design of a discrete.
100MHz-650MHz, 1 Watt Distributed Power Amplifier with Discrete MOSFET devices Tan TeikSiew1&2, Mohd Fadzil Ain1, and Syed Idris Syed Hassan1 1
School of Electrical and Electronic Engineering Universiti Sains Malaysia Seri Ampangan, 14300 Nibong Tebal, Penang, Malaysia 2
Motorola Technology Sdn Bhd Plot 2, Bayan Lepas Technoplex Industrial Park Mukim 12, S.W.D., 11900 Penang, Malaysia
Ld/2
Abstract-This paper will describe the design of a discrete MOSFETs distributed power amplifier with 1 watt output power in the 100MHz-650MHz frequency range. Miller theorem and staggering technique are discussed to further increase the bandwidth and improve the stability of the amplifier. Experimental and simulation results of such a structure are discussed.
Ld
Ld
D
Zo
G
Ld/2
D G
S
D
S
S
Lg
Lg/2
Input Lg/2
Lg
I. INTRODUCTION The principle of the distributed amplifier is very attractive and well known for broadband amplifier configuration since their invention in 1935 by Percival [1]. Distributed amplifier offers a means of achieving gain at high frequencies by absorbing the parasitic capacitances of the FETs into synthetic input and output transmission lines, which are then coupled by transconductance of the FETs. The amplifier can be designed to give a flat, low pass response up to very high frequencies [2]. In this paper, we will present a design of 1 watt, 3 stages of distributed power amplifier with frequency range of 100MHz-650MHz by using Mitsubishi RF power MOSFET, RD01MUS1. The design has been shown some performance improvements over previous design [3] in terms of bandwidth and stability by applying staggering technique and Miller theorem. The design also attempts to match the impedance of the input and output ports to 50Ohms over the bandwidth of the amplifier.
Zo
Figure 1. 3 stages of distributed amplifier.
1-4244-0549-1/06/$20.00 ©2006 IEEE.
Drain
Gate Cds
Cgs
Source Figure 2. Simplified lossless unilateral FET model.
If the drain capacitance is made equal to the gate capacitance, then the input and output current will be phase synchronized by having the same gate and drain line inductance. With this condition and assuming the image impedance matched termination, the voltage gain of the distributed amplifier can be derived as [4]
II. BASIC DISTRIBUTED AMPLIFIER A simple 3 stages of distributed amplifier structure is shown in Fig. 1. As discuss in [3], the theory of the distributed amplifier can be easily been analyzed based on lossless unilateral model for FET device. We assume, for convenience, the simplified FET equivalent shown in Fig. 2.
Output
G
Vout − N × gm = Vin w2 2 × 1− 2 wC
L − Nθ e C
where N: gm :
number of stages stage transconductance
wC :
cutoff frequency of the lines
θ:
propagation constant of the lines
(1)
The cutoff frequency and line impedance are given as
wC =
ZO =
The term
1−
2 LC
Lg/2
(2)
Lg/2
Lg/2
Input
Lg/2
Lg/2
Cgse
Lg/2
Cgse
Zo
Cgse
(a)
L C
Ld/2
(3)
Ld/2
Ld/2
Input Cdse
Ld/2
Lg = 0.7 × Ld
(4)
C gs = 0.7 × C ds
(5)
However, the drain to gate capacitance, Cgd is a parasitic element present in the device model and can not be neglected or reduced. Hence, in order to maintain the unilateral approximation, the Miller theorem can be applied to the circuit configuration shown in Fig. 3. Therefore, the effective FET capacitance values become:
Zo
Cdse
Cdse
w 2 in (1) will cause a peak in the gain as wC2
the frequency approaches the cutoff frequency. There are several methods to eliminate this undesired peaking effect. The one used in this design is based on the staggering technique outlined by Sarma [5]. The approach is to make the drain line cutoff frequency smaller than that of the gate transmission line. Defined as the ratio of the drain-line to the gate-line cutoff frequencies, the staggering factor of about 0.7 has been analyzed as the optimum value [5], so that we get the maximum bandwidth without getting any peak in the gain response. Restricting the line impedances to being equal and applying the staggering technique with a factor of 0.7, the gate line inductance and capacitance can be derived as
Ld/2
Ld/2
(b) Figure 4. (a) New gate transmission line model. (b) New drain transmission line model.
In typical FET devices, the Cgs is larger than Cds. One way to overcome the differences of Cgs and Cds as well as solving for (9) is to couple the FET devices to the input gate line through series capacitors, Cga [7]. The Cga can be calculated as Cgse//Cga=0.7xCdse
(10)
Also, as discuss in [3], the impedance looking into the L-C transmission line will exhibit a strong deviation from the nominal impedance near the line’s cutoff frequency. One way to realize the image impedance match over a broad range is to insert m-derived half sections between the lines and each termination. The m-derived half circuit is illustrated in Fig. 5, where it has been shown that using m values near 0.6 provides near optimal results. This technique will greatly improve the image impedance match, while also allowing simple resistive terminations to be used. The complete resulting modified schematic of the basic distributed amplifier is shown Fig. 6. mL/2
Cgse = Cgs + Cgd (1 + Av )
(6)
⎛ 1 ⎞ Cdse = Cds + C gd ⎜⎜1 + ⎟⎟ A v ⎠ ⎝
(7)
(1-m2)L/2m mC/2
where voltage gain,
Av = g m Z 0
(8)
Figure 5. Low pass m-derived half section.
Hence, (5) become
C gse = 0.7 × C dse
(9)
With the Miller effect, the new equivalent gate and drain transmission lines for 3 stages distributed amplifier are shown in Fig. 4. Zo
Ld
Ld/2 D 50 Ohms
Cgd
Matching Section
G
S
Cga Lg/2
Cgs
Cga
Ld/2
D G
S
Cga
output
D G
S
Cga
Matching Section
Cga
Cga
Input
Vs
Ld
Lg
Lg
Lg/2
Cds
+
V
Zo gmV+
Vo
Figure 3. FET model where the Miller theorem is applied.
Figure 6. Modified DA with gate coupling capacitor and m-derived half section.
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dB(S(2,2))
dB(S(1,1))
(b)
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freq, GHz
k factor
20
(a)
(b)
10
L L11 L=12.4LnH
L L12 L=12.4 nH
L L2 L=23.3 nH
L1 L=18.7 nH
L L3 L=23.3 nH
L L4 L=18.7 nH
DC_Block DC_Block6 FET FET2
FET FET1
FET FET3
0
0.0
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freq, GHz
Figure 8. Comparison of small signal performance between previous design [3] and current design using ideal models.
The amplifier was then optimized using Motorola’s proprietary non-linear model for FET, lumped components, such as resistors, capacitors and inductors, and transmission lines to ensure accurate simulation results. The optimized small signal performance is illustrated in Fig. 9. For this result, the amplifier was biased with gate voltage of 2.7V and drain supply of 7.5V. The result is clearly shown that the gain bandwidth is improved from 500MHz to 650MHz and the k factor was >1 across the band. 40
0
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dB(S(1,2))
(b) (c)
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(a)
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(c)
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(b)
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L L5 L=13 nH
C C4 C=1.96 pF
L L6 L=16.3 nH
(c)
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(b)
R R3
DC_Feed DC_Feed1
R R4
DC_Feed DC_Feed2
L L8 L=13 nH R R5
DC_Feed DC_Feed3
C C5 C=1.96 pF
DC_Block DC_Block4
R R2 R=50 Ohm
(c)
(a)
(b)
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1.0
(a)
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freq, GHz
freq, GHz
L L10 L=8.7 nH
-10
-20
C C3 C=8 pF
L L7 L=16.3 nH
1.0
0
-10
-30
k factor
Term Term1 Num=1 Z=50 Ohm
L L9 L=8.7 nH
0.9
10
30
DC_Block DC_Block2
0.7
(a)
0
Term Term2 Num=2 Z=50 Ohm
0.5
freq, GHz
10
0.1
C C2 C=8 pF
C C1 C=8 pF
1.0
-10
dB(S(2,2))
DC_Block DC_Block5
C C7 C=2.8 pF
0.8
Legend: (a) Simulated result from previous design [3]. (b) Simulated result for current design.
30
dB(S(1,1))
DC_Feed DC_Feed4
C C6 C=2.8 pF
0.6
freq, GHz
40
freq, GHz R R1 R=50 Ohm
1.0
5
-20
0.1
V_DC SRC1 Vdc=7.5 V
0.8
10
(a)
0
0.6
freq, GHz
freq, GHz
dB(S(2,1))
In this paper, the Mitsubishi RF power MOSFET, RD01MUS1, was again chosen from [3] to design a distributed power amplifier. For initial design, an ideal model of FET was used to represent the RD01MUS1. From the datasheet of the device [8], the parasitic capacitances are given as: Cgs=14pF, Cds=8pF, and Cgd=1.25pF. Also, the transconductance, gm given by Mitsubishi at bias condition of 2.7V with supply of 7.5V is 0.32S. From (6) till (8), the effective FET capacitances were calculated as Cgse=35.25pF and Cdse=9.33pF, where Av=16. By applying the staggering technique, the effective gate capacitance shall be Cin=0.7xCdse=6.53pF. A series of gate coupling capacitors, Cga with values of 8pF calculated from (10) are needed to reduce the Cgse to Cin. With line impedance of 50Ohms, the line inductors and matching networks can be easily been calculated. The Advanced Design System (ADS) simulator was used extensively to predict and optimize the small signal and large signal performance of the amplifier during the design phase. The simplified simulation schematic is depicted in Fig. 7. The simulated small signal performance using ideal FET and lumped component models is illustrated in Fig. 8. As compare with previous design [3], the current design shows that the bandwidth is slightly improved to 650MHz with no peaking in the gain near cutoff frequency. The gain is slightly lower than previous design [3] due to the lower gate coupling capacitance used. Hence, the gain can be traded for bandwidth by an appropriate choice of series capacitors while maintaining a given gain bandwidth product. As the peaking effect eliminated, the input and output return loss are also improved, where S11
