10kV SiC MOSFET split output power module Szymon Bęczkowski, Helong Li, Christian Uhrenfeldt, Emanuel-Petre Eni, Stig Munk-Nielsen Aalborg University Pontoppidanstræde 101 9220 Aalborg, Denmark email:
[email protected]
Keywords «Silicon Carbide (SiC) », «Power semiconductor device», «Wide bandgap devices», «MOSFET», «High voltage power converters»
Abstract The poor body diode performance of the first generation of 10kV SiC MOSFETs and the parasitic turn-on phenomenon limit the performance of SiC based converters. Both these problems can potentially be mitigated using a split output topology. In this paper we present a comparison between a classical half bridge and a split-output power module. It is found that the peak current during turn-on is reduced significantly, however some additional challenges arise during implementation.
Introduction Wide band gap semiconductors provide an opportunity to push the boundaries of current power conversion technology beyond what is possible with current state of the art silicon devices. SiC material is characterized by increased thermal conductivity and increased electron drift velocity compared to silicon [1]. Switching speeds of 10kV SiC MOSFETs are comparable to low voltage Si MOSFETs. These improved properties allow engineers to create power converters running with higher DC voltages at much higher switching speeds as what is currently possible. Possible applications for 10kV SiC MOSFETs include solid-state transformers, HVDC converters, inverters for wind turbines connected directly to MV distribution lines and many more [2–3]. However, until today most wind turbine converters operate at low voltage and the coupling to the distribution grid is done through a transformer. Replacing the current low voltage Si-based converters has the potential to lower the losses inside the turbine and the size and weight of the converters. In spite of the aforementioned benefits, many systems still use low voltage Si technology. This is due to the maturity of current Si power switches and good understanding of their behaviour. Medium voltage SiC MOSFETs are new to the field and have not yet reached their full potential. Their lifetime and short-circuit behaviour has not yet been fully characterized. The whole converter stack needs to be redesigned to work with medium voltage. This requires new knowledge and skills needed for people designing and maintaining the power converters. Apart from these system issues the 10kV SiC MOSFET presents a few additional design challenges. One is the poor performance of the built-in body diode [4]. To overcome this, a series connected Si Schottky diode, may be used together with an additional external antiparallel 10kV JBS (junction barrier Schottky) diode as in fig. 1a [5]. This solution, however, increases the conduction losses and increases the complexity of a power module layout.
Fig.1. Issues arising using the first generration 10kV SiC MOSFET: a) poor performance body diodee needs to be turned-off using a series connected Schottky diode; b) CGD and CGS input capacitances of the MOSFET form a voltage divider that may cause unwanted MOSFET turn-on due too high dv/dt
A second problem is a dv/dt trigggered turn-on. This phenomenon is due to the intrrinsic capacitances present in the MOS structure. CGD G and CGS form a capacitive voltage divider (fig. 1b) connected to the gate of the MOSFET. When the top t transistor in a half-bridge turns on and the volltage in the midpoint rises this capacitive voltage dividder will couple the output voltage to the gate. If thhe threshold voltage level is reached the bottom transiistor will turn-on. This may lead to a short circuitt and destruction of the power module. To prevent this from happening, transistors may need to be sloowed down to reduce the output voltage dv/dt thus incrreasing switching losses. A split output topology can mitiggate both of these problems by changing how the commutation process occurs. Previous research, usiing low voltage SiC power MOSFETs and SiC Scchottky diodes in split-output topology, has shown that most of the current commutates to external diodes d and the body M it showed diode of a discrete MOSFET wass almost unused in the commutation process [6]. Moreover, an increase in efficiency of a spliit-output topology power converter over a classicaal half-bridge. These properties of the split-output topoology make it an attractive option for 10kV SiC MOSFETs. M
Split-output topology Compared to the half-bridge (fig. 1a), the split-output module (fig. 2b) is composeed of two switching cells: N-cell and P-cell [7]. Each cell consists of a transistor and a diode. The two cell outputs can be directly connected together [8–9]] or by using two discrete inductances, LN and LP [6]. These inductances decouple the switching cells from each other, isolating transistor Q1 from thhe dv/dt induced by switching Q2 and thus preventting parasitic turn-on.
Fig. 2. Analysed topologies: a) traditionaal half-bridge; b) split output with external decupling inducttors LP and LN
Additionally, in the split output power p module, the body diode of Q2 is decoupledd from transistor Q1. Commutation occurs between thee SiC junction barrier Schottky diode and transisttor from the same switching cell. The performance of the external SiC JBS is much better comparedd to the body diode of a SiC MOSFET reducing condduction and switching losses [6].
Power modules Two power modules were designed to compare the behaviour of traditional half bridge and split output topology (fig. 3). The modules were designed to be similar in layout to allow for an easy comparison. a)
b)
Fig. 3. DBC layouts of a) traditional half-bridge; b) split-output power modules
The modules were fabricated on a 0.63mm AlN substrate with 0.3mm copper layers (fig. 4). Dies were soldered to the substrate using a vapour-phase process. The wire bonding of the soldered dies and the DBC were done using 250μm aluminium heavy wire. The structure was then encased and embedded in silicone gel. a)
b)
Fig. 4. Manufactured power modules after soldering and wire bonding steps: a) half-bridge and b) split-output.
Measurements Both modules were tested using an industry standard double pulse test to analyse the dynamic behaviour. They were mounted on a low inductance laminated busbar with two 50μH capacitors connected in parallel. A 25mΩ T&M Research SBNC-2-025 current shunt was used to measure the module current. Current was measured on the negative DC terminal of the power module. PMK PHV4002-3 passive voltage probes were used to record the output voltages. A −5/+20V gate driver was used in both cases. The top MOSFETs’ gate-source terminals are shorted. A schematic of the switching test circuit is shown in fig. 5 and the values of the passive components are given in table 1. Table 1. Values of the passive components in the measurement circuit.
L = 20mH LP = LN = 35μH CDC = 100μF (2×50μF) LDC ≈ 35nH (estimated from the switching waveforms)
Fig. 5. Details of the mechanism causingg a peak transient in the module current during Q1 or QN turnn-on. a)
b)
Fig. 6. Measured module current at 40000V DC-link voltage for a) half-bridge and b) split-output moodules.
As can be observed in fig. 6, the module peak current during bottom MOSFET turrn-on was decreased T is related to the significantly in the split-output (ffig. 6b) compared with the half-bridge (fig. 6a). This decoupling effect of the two exteernal inductors. In a classical half-bridge (fig. 5a),, during Q1 turn-on, the charge stored in Q2, D2 and CL is discharged through Q1, LDC and CDC. In the case of a split-output topollogy the charge that needs to be removed from thee top devices is split into two separate charges. DN dioode charge causes the peak during Q1 turn-on. Thhe energy stored in Q2 and CL is transferred to externnal LN and LP inductors.
Fig. 7. Currents in external LN and LP innductors compared to the iL load current
When inspecting the currents of the t LP and LN inductors, in time instances t0–t1 annd t4–t5 in figure 7, it is noted that the LP inductor cuurrent always reaches the same absolute value afteer Q1 turn-on. The absolute value of this current is related r to the energy stored in the QP and DP beforre turn-on and the LP inductor value after the turn-oon, since the energy stored in the LP and LN inducttors has to be equal to the energy stored in the semicoonductors before switching. This phenomenon is described in detail in the turn-on analysis below.
Q1 turn-off analysis
Fig. 8. Voltage and current waveforms of half-bridge (two left) and split output (two right) power modules during a turn-off event.
While the analysis of the switching waveforms in case of a half-bridge is straight forward, the analysis of a split-output power module is more complex. The external LN and LP inductors create additional dynamics inside the module. Since they can store energy, the switching waveforms depends on the current distribution between LN and LP. Some of the current contributions connected to these inductors circulate inside the module and some circulate through the DC-link capacitor. This needs to be taken into account in order to understand the switching waveforms. The analysis of a turn-off event can be broken into a few distinct events (fig. 8; note that some events overlap): ←t1: inductor current ramped to ~8A, iLN = iL t1–t2: Q1 turns off, vP raises to vDC t1–t3: difference in vP and vN potentials, vPN
,, cause the current change in LN and LP
The value of the LN and LP inductors determine the t1–t3 time length and also the dynamic current sharing between the two inductors. If the value of these inductors is comparable to the load inductance, most of the QN current would commutate to DN [6]. However, due to high DC-link voltage such high value inductors may not be practical due to their size and cost. In that case, other measures are needed to fix the body diode problem. One approach may be to operate with zero or reduced dead time between the two MOSFET gate signals to limit the use of the body diode. Due to the external LN and LP inductors this kind of operation may be feasible, however, the analysis of this hypothesis is outside the scope of this paper.
Q1 turn-on analysis
Fig. 9. Voltage and current waveforms of half-bridge (two left) and split output (two right) power modules during a turn-on event.
Similarly to the turn-off, the analysis of a turn-on event can be broken into few distinct events as in fig. 9: ←t1: inductor current freewheels in DN and the body diode of QP. At t1 time iLN = 1A and iLP = 6A. Current sharing may be different depending on the forward characteristics of these devices and the operating point of the circuit. t1–t2: Q1 turns on, vP falls to approximately zero t1–t4: difference in vN and vP potentials, vNP, causes the current change in LN and LP t3–t4: negative iLP current causes VN to drop. The process continues until charges from P-cell semiconductors are removed. The peak minimum value of this current iLP(peak.low) depends on the total output charge stored in the DP and QP semiconductors and the LN and LP inductor values. the stored charge depends on the vDS and the nonlinear capacitance of the active devices. Under the condition that {LN, LP}≪L we can assume that iLN + iLP ≈ constant during switching, therefore the change in the iLN inductor current implies an opposite change in iLP inductor current. Furthermore, the peak LN inductor current is equal to iL – iLP(peak.low) and can be much higher than the load current. As a consequence, the conduction losses linked to iLN current are increased.
Conclusions From the analysis of presented switching waveforms, it is found that a split output power module exhibits a lowered peak current during QN turn-on due to the presence of external decoupling inductors LN and LP. These inductors also prevent current peaks due to capacitances present in the load inductance since these peak currents circulate through the DC-link of the power converter. The observed decrease in their value may be beneficial for the EMI performance of the total converter system.
The split-output topology was evaluated to test the feasibility of mitigating the problems with the body diode of these early 10kV MOSFETs. While the topology works well in low voltage systems, it may not be optimal for high voltage converters due to the necessarily high value of external decoupling inductors needed for its operation. However, operation with zero dead time may mitigate this problem. This hypothesis is yet to be tested. Small values of the external decoupling inductors cause high iLN and iLP peak currents. The absolute value of these currents is higher than the load current. These current circulate inside the power module structure causing excessive losses.
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