Journal of Circuits, Systems, and Computers Vol. 20, No. 4 (2011) 709725 # .c World Scienti¯c Publishing Company DOI: 10.1142/S0218126611007566
12-BIT PSEUDO-DIFFERENTIAL CURRENT-SOURCE ¤ RESISTOR-STRING HYBRID DAC
M. T. S. AB-AZIZy, A. MARZUKIz and Z. A. A. AZIZx School of Electrical and Electronic Engineering, Engineering Campus, Universiti Sains Malaysia, Nibong Tebal, Penang, 14300, Malaysia y
[email protected] z
[email protected] xeezul¯
[email protected] Received 6 July 2009 Accepted 13 January 2011 This paper discusses a hybrid Digital-Analog Converter (DAC) architecture which is a combination of a binary-weighted resistor approach for eight bits in the least-signi¯cant-bit and thermometer coded approach for four bits in the most-signi¯cant-bit. The proposed design combines advantages of the binary-weighted resistor approach and thermometer coded approach. The ¯nal design is composed of two 12-bit DACs to achieve a pseudo di®erential output signal. The converter was designed with a Silterra 0.18 m 1.8 V/3.3 V CMOS process technology. The post-layout simulation results show that this design achieves 12-bit resolution with INL and DNL of 0.375 LSB and 0.25 LSB, respectively. The power consumption is 6.291 mW when the designed DAC is biased with supply voltage equal to 3 V. The performance is accomplished with a design area of 230 m 255 m. Keywords: Digital-to-analog converter; integrated circuit.
1. Introduction A Built-In Self-Test (BIST) for analog and mixed-signal components has been identi¯ed as one of the major requirements for the IC test.13 The main advantages of the BIST are to reduce test access requirements and to address the growing performance gap between a Chip Under Test (CUT) and a tester by integrating tester functions onto the CUT. In addition, parasitics induced from an external Automatic Test Equipment (ATE) can be reduced. Example of the application of a test Digital-to-Analog Converter (DAC) is shown in Fig. 1. In Fig. 1, the test DAC is used to imitate the analog signal and at the same time test the functionality of the Programmable Gain Ampli¯er (PGA), the Analog-to-Digital Converter (ADC) and *This paper was recommended ‡ Corresponding author.
by Regional Editor Krishna Shenai.
709
M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz Voltage Inputs (Potentiometric Sensors)
710
• • •
Bandgap Reference
Capacitive Sensor Interface
12 bit Pseudo-Differential DAC
Capacitive Sensors
Temperature Sensor
Differential 10:1 Analog Multiplexer
PGA
LPF
12-bit ADC
Analog Digital
Fig. 1. Application of 12-bit pseudo-di®erential DAC in sensors analog front-end architecture.
the Low Pass Filter (LPF). An Analog Mulitplexer is normally used to channel the signal from either a real or test signal. Obviously the test DAC has to be physically small. Three type of DACs which are suitable for the test DAC are the binary-weighted resistor DAC, weighted-current-steering DAC and thermometer coding DAC. The binary-weighted resistor DAC is composed of resistors that are connected in series. As the digital input weighted is increased the resistor value is normally decreased exponentially. This approach is easy to design and implement but for only small digital input.4 For higher resolution, very large resistance must be used and therefore is not practical. Di®erences in resistances can reduce the resistor matching, this will a®ect the output linearity. The weighted-current-steering DAC is composed of current-sources, each of which is connected with a switch controlled by the input digital codes. The current-steering switches method is considered faster than the voltage switches method because a reference current is not interrupted and only a signi¯cant voltage appears at the output but not across the switches.5 No decoder is needed and this reduces circuit complexity and increases the operating speed.6 However, the current steering DAC has static and dynamic performance limitations due to process variation, current mismatch and glitch energy.7 The thermometer coding DAC is composed of a binary-to-thermometer decoder circuit. The digital input needs to be converted to the thermometer code that is consisted of 2 N 1 number of bits in thermometer code for N-bit of digital input.
12-Bit Pseudo-Di®erential Current-Source Resistor-String Hybrid DAC
711
The advantages of this architecture are signi¯cantly better Di®erential Nonlinearity (DNL), and glitch and monotonicity performances.7 This paper discusses a hybrid DAC architecture that combines the concepts of the binary-weighted resistor DAC and the thermometer coding DAC. The binaryweighted resistor scheme is for an eight least-signi¯cant-bit (LSB) and the thermometer coding scheme is for the four most-signi¯cant-bit (MSB). This architecture also used current steering as the switchable current source to provide current through the resistor network. The hybrid architecture will get the most advantages from di®erent segments such as better DNL and Integral Nonlinearity (INL), while consuming less area and complexity. The design of the DAC is small and can be placed into any mixed signal IC or system on chip. This paper is organized as follows. Section 1 discusses the introduction of the DAC. Section 2 explains the design target. Section 3 explores the design methodology of the DAC. It explains the binary-weighted resistor DAC and the thermometer coding DAC concepts. It also explains the switchable current source. It ¯nally explains the hybrid DAC concept which is used in this work. Section 4 describes the implementation of the pseudo-di®erential DAC. Section 5 discusses the test bench and simulation results. Finally, the conclusion is explained in Sec. 6. 2. Hybrid DAC Speci¯cation The design is composed of two single-ended DACs and each is referenced to ground as shown in Fig. 2(a). The ¯rst DAC is controlled by a 12-bit D½11 : 0 input and the Vref 11 10 9 8 7 6 5 4 3 2 1 0
Vref × 1.032 Vref × 1.016
P2 = 0 P2 = 1
S1 && S2
S1 && S2
DAC P
Vref S1 && S2 P1 P1 P1 P1 P1 P2 P1 P1 P1 P1 P1 P1
11 10 9 8 7 6 5 4 3 2 1 0
P1 = 0
DAC 1
Voltage Out
D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
DAC P
DAC N
DAC N S1 && S2 DAC 2
P1 = 1
P2 = 0 P2 = 1
Vref × 0.016
0
D[11:0] Digital Code
(a)
(b)
Fig. 2. (a) Pseudo-di®erential DAC block diagram, (b) DAC transfer characteristic.
4095
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M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz
second DAC is controlled by P1 and P2 which are programmable to produce reference voltage. All the digital inputs are inverted, meaning that a \1" or logic high input will cause a correspondingly low voltage on the DAC output. As D½11 : 0 increases from 0 to 4095, the ¯rst DAC output decreases respectively from its maximum value to zero volt. The second DAC is used to produce a reference voltage level at Vref 1:032, Vref 1:016, Vref 0:016 or 0 V, which can be controlled with P1 and P2 registers. This is shown in Fig. 2(b). Finally, the output of the two DACs are multiplexed to provide three independent modes of operation that are: normal operation, swapped outputs when setting S1 and S2 registers are high, and lastly high impedance output when setting S1 ¼ 0. For the high impedance mode both DACs are powered down and drawn negligible current (S1 is connected to POWER).
3. Methodology Figure 3 shows the overall blocks diagram and its interconnections. The DAC Reference is the most important block that is used to provide constant biasing voltages to DAC 1 and DAC 2 in Fig. 3. The DAC Decoder is used to decode a 12-bit digital input to appropriate code for both DACs instantaneously. The outputs of the DACs are multiplexed according to modes of operation as discussed in Sec. 2.
DAC 1
CAPCONN
CAPCONN
VOUT
BITN[7:0] 8
8
15
DAC 2
BIT8N[14:0]
BITN[7:0]
BIT8P[14:0]
BITP[7:0]
15 DAC 1
VFB
BITP[7:0]
IB20
BIT8N[14:0]
DACBIAS1 DACBIAS2
DACOUT
VREF
DACBIAS1 DACBIAS2
BIT8P[14:0]
DACBIAS1 DACBIAS2
POWER
DAC 2
DACOUT
DAC REFERENCE
P1
12
P2
S1
DAC P
D[11:0]
S2
DAC N
DAC DECODER
DAC MULTIPLEXER
Fig. 3. The 12-bit pseudo-di®erential hybrid DAC architecture.
12-Bit Pseudo-Di®erential Current-Source Resistor-String Hybrid DAC
713
The most fundamental cell in this work is the switchable current source. This cell consists of three PMOS transistors with di®erent width over length ratios (W/L). The main objective is to provide a constant current to the resistor string after the switch is turned ON. For the LSB section, the 8-bit digital input will be inverted ¯rst from its current stages then connected directly to the current-source switches. The sum of current °ow through the binary-weighted resistor produces the voltage level and measures as the output DAC. Instead of continuing to add an exponentially increasing resistance for each bit beyond 8 bits, a thermometer coding DAC is used at the top of the string in a binary-weighted resistor string. The proposed thermometer coding DAC uses a decoder circuit which can convert a 4 MSB input to 15-bit. 3.1. Switchable current-source The switchable current source made up of three PMOS transistors is shown in Fig. 4. It will operate depending on the input voltage level connected to the gate of transistor M3. When there is a high voltage level at the input M3, it will turn OFF transistor M3, switching ON the current source and a constant current will °ow to the IOUT through transistor M2. The switchable current source is turned OFF, if a low voltage is at the gate of M3, the M3 will draw constant current from the transistor M1 to the ground instead of IOUT. The fourth terminal of the PMOS transistors is connected to VDD.
VDD
DACBIAS1
M1
DACBIAS2
M2 I
BITSEL
M3 IOUT
GND Fig. 4. Switchable current source.
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M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz
3.2. Binary-weighted resistor For the LSB segment, a binary-weighted resistor string is used. Section 2 stated as the input increases from 0 to 4095 the DAC output decreases from its full scale 1.20 V to 0 V. Therefore the value of each resistor is proportional to the digital input bit weighted value. Figure 5 is an example for a 3-bit LSB structure. When input is low, it turned ON the current source then the constant current with magnitude of I will °ow through the resistor string. The value of resistors are exponentially increased as the weighted input bits are increasing. By using the superposition theorem, the outputs can be calculated. This structure can be extended until D½7 and the resistance value increases exponentially depending on the input bit. Based on Fig. 5, the simpli¯ed 3-bit mathematical model is: Vout ¼ ð2 2 D½2 þ 2 1 D½1 þ 2 0 D½0ÞðI RÞ ;
ð1Þ
where I is a constant current source, R is the least signi¯cant bit resistor and D is the input bit, which is \1" for high and \0" for the low level. Based on Eq. (1) the mathematical model for 8 LSB is: Vout ¼ ð2 7 D½7 þ 2 6 D½6 þ 2 5 D½5 þ 2 4 D½4 þ 2 3 D½3 þ 2 2 D½2 þ 2 1 D½1 þ 2 0 D½0ÞðI RÞ :
ð2Þ
3.3. Thermometer coding This work used a 4-to-16 prior coding scheme for the thermometer coding. The thermometer coding consists of 2 N 1 number of bits for N-bit of digital input. For every bit in the thermometer code, it will be connected with two switchable current Vout = 7(I × R) = 7LSB D[2]
I 2R
I × 2R +
D[1]
I R
2I × R +
D[0]
I R
3I × R
GND Fig. 5.
Simpli¯ed 3-bit structure of LSB segment.
12-Bit Pseudo-Di®erential Current-Source Resistor-String Hybrid DAC
715
Table 1. Thermometer coding for 4 MSB segment. D½11
D½10
D½9
D½8
Thermometer coding
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
111111111111111 111111111111110 111111111111100 111111111111000 111111111110000 111111111100000 111111111000000 111111110000000 111111100000000 111111000000000 111110000000000 111100000000000 111000000000000 110000000000000 100000000000000 000000000000000
sources as in Sec. 3.1. The high bit in the thermometer code will turn ON switchable current sources and the summation of the currents will °ow to the weighted resistor string. Table 1 shows a 4 MSB input to its corresponding thermometer code. The equivalent resistance used for the 8-bit binary-weighted resistor for the LSB segment of DAC as in Sec. 3.2 is: Req ¼ R þ R þ 2R þ 4R þ 8R þ 16R þ 32R þ 64R ¼ 128R :
ð3Þ
For instance, when D½8 is low, and other Ds in Table 1 are high, this will give the thermometer code of 100000000000000. As stated previously, one bit high in the thermometer code will turn ON the switchable current sources. The output voltage is: Vout ¼ ð2 1ÞI Req ¼ 2I 128R :
ð4Þ
According Eq. (4), 1 in the brackets is the number of high level bits in the thermometer code. It is multiplied by 2 because of it is connected with two switchable current sources. The total output responding to a 4 MSB segment is: Vout ¼ ðD½11ð16I 128RÞ þ D½10ð8I 128RÞ þ D½9ð4I 128RÞ þ D½8ð2I 128RÞÞ
ð5Þ
or Vout ¼ ð2 11 D½11 þ 2 10 D½10 þ 2 9 D½9 þ 2 8 D½8ÞðI RÞ :
ð6Þ
3.4. Hybrid DAC Sections 3.2 and 3.3 discuss theories of the binary-weighted resistor DAC and the thermometer coding which are employed to make two segments of the 12-bit hybrid
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M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz
DAC architecture. The combination of both architectures will complete the 12-bit hybrid DAC. The completed model of the analog output voltage for the 12-bit hybrid DAC architecture from Eqs. (2) and (6) is: ! 2 11 D½11 þ 2 10 D½10 þ 2 9 D½9 þ 2 8 D½8 þ 2 7 D½7 þ 2 6 D½6 Vout ¼ ðI RÞ : ð7Þ þ 2 5 D½5 þ 2 4 D½4 þ 2 3 D½3 þ 2 2 D½2 þ 2 1 D½1 þ 2 0 D½0 The proposed 12-bit hybrid DAC is shown in Fig. 6. The MSB segment that uses the thermometer code is at the top of diagram and the LSB segment which is binaryweighted resistor is at the bottom. The required voltage is approximately 1.20 V, and the least signi¯cant bit resistor R is de¯ned to be 15 . So with 15 and 1.20 V, the required constant current I is 20 A. In order to determine the full scale output, Eq. (7) is used and when all the
VDD
VOUT
16I D[11] 8I D[10] 4I D[9]
MSB Segment
2I D[8] I D[7] 64R
LSB Segment
I D[6] 32R I D[5] 16R I D[4] 8R I D[3] 4R I D[2] 2R I D[1] R I D[0] R
Fig. 6. MSB and LSB segments of the 12-bit hybrid DAC.
12-Bit Pseudo-Di®erential Current-Source Resistor-String Hybrid DAC
717
inputs are low, the full scale output voltage of 1.2285 V can be achieved. According to the Eq. (7), the resolution of the DAC is 0.3 mV. 4. Implementation 4.1. DAC reference The DAC Reference generates the bias voltages necessary for the switchable current sources in each DAC in Sec. 4.3. A single stage ampli¯er is used to impose the reference voltage across the 31 unit resistors in series. On top of that, series resistors consist of 16 unit current source switches, and one unit resistor value that is arranged in series is 120 (to match with resistor in the binary-weighted resistor string). Figure 7 shows the DAC Reference diagram. The ¯rst bias voltage DACBIAS1 is the voltage required at the gate of transistor M1 in switchable current source to maintain a constant current as shown in Fig. 4. The second bias DACBIAS2, is a cascode bias feeding to increase output impedance of the current source as in Fig. 4. The external voltage reference (VREF) is needed to maintain the bias voltages because this is one of the most important factors to provide a constant current throughout the resistor network. R and C in Fig. 7 are used for the circuit stability. VOUT and feedback voltage (VFB) are connected at the top level in order to con¯gure the circuit as a bu®er ampli¯er. The fourth terminal of the PMOS transistors is connected to VDD while the fourth terminal of
VDD
BITSEL
PDB
‘VDD’ ‘GND’ DACBIAS1 DACBIAS2
VHSN DACBIAS1 DACBIAS2
POWER
PD
BITSEL
BITSEL
‘VDD’ ‘GND’ DACBIAS1 DACBIAS2
‘VDD’ ‘GND’ DACBIAS1 DACBIAS2
Switchable current source
Switchable current source
IOUT
IOUT
Switchable current source [16X] IOUT
VHSN
1.5 k
PDB
C
DACBIAS1 DACBIAS2
VOUT R IB20 20µA
VFB
2.35 pF
VREF 1.20 V
Rs
PD
PD
GND
Fig. 7. DAC Reference diagram.
31unit resistors of 120 in series
718
M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz
the NMOS transistors is connected to GND. With the target value current, I equals 20 A, VOUT is therefore equal to 1.1904 V. 4.2. DAC decoder The DAC Decoder function is to decode the LSB and MSB digital inputs to the appropriate codes. For LSB, each input is connected to each of the NOT gate to invert its value to the BITP[7:0] output. This must be done because to switch ON the current source, the voltage must be at a low level. For the MSB, the inputs are decoded to the thermometer code that has a 15-bit code, which corresponds to BIT8P[14:0]. These outputs of the DAC Decoder are then connected to DAC 1. Another function is to provide control signals for the reference voltages which are provided by the P1 and P2 registers. The control signals correspond to the BITN[7:0] and BIT8N[14:0] outputs. These outputs are then connected to DAC 2. Figure 8 shows the DAC Decoder that consists of NOT gates to invert its input value and the thermometer coding decoder circuit. 4.3. Single DAC A Single DAC, as shown in Fig. 9, employs 38 switchable current sources that are arranged in parallel according to the BIT8[14:0] and BIT[7:0] from the DAC Decoder BIT8P[7] D[11]
D[0]
BITP[0]
P1
BIT8N[0]
D[1]
BITP[1]
P1
BIT8N[1]
BIT8P[0]
D[2]
BITP[2]
P1
BIT8N[2]
BIT8P[9]
D[3]
BITP[3]
P1
BIT8N[3]
D[4]
BITP[4]
P1
BIT8N[4]
D[5]
BITP[5]
P1
BIT8N[5]
D[6]
BITP[6]
P1
BIT8N[6]
D[7]
BITP[7]
P1
BIT8N[7]
P1
BITN[0]
P1
BIT8N[8]
P1
BITN[1]
P1
BIT8N[9]
P1
BITN[2]
P1
BIT8N[10]
P1
BITN[3]
P1
BIT8N[11]
P1
BITN[4]
P1
BIT8N[12]
P1
BITN[5]
P1
BIT8N[13]
P2
BITN[6]
P1
BIT8N[14]
P1
BITN[7]
BIT8P[8]
D[10] BIT8P[1] BIT8P[10] D[9]
BIT8P[2] BIT8P[11]
D[8] BIT8P[3] BIT8P[12] BIT8P[4] BIT8P[13] BIT8P[5] BIT8P[14] BIT8P[6]
Fig. 8. DAC Decoder diagram.
12-Bit Pseudo-Di®erential Current-Source Resistor-String Hybrid DAC
DACBIAS DACBIAS2
BIT8[14] BIT8[13] BIT8[12] BIT8[11] BIT8[10]
719
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
BITSEL
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
‘VDD’ ‘GND’
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
DACBIAS1 DACBIAS2
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
Switchable current source
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
BITSEL
BIT8[9] BIT8[8] BIT8[7] BIT8[6] BIT8[5]
BIT8[4] BIT8[3] BIT8[2] BIT8[1] BIT8[0]
BIT[7] BIT[6] BIT[5] BIT[4] BIT[3] BIT[2] BIT[1] BIT[0]
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
DACOUT
BINARY-WEIGHTED RESISTOR STRING
Fig. 9. Single DAC diagram.
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M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz
block as discussed in Sec. 4.2. This block also includes the binary-weighted resistor string. All the switchable current sources are biased by DACBIAS1 and DACBIAS2 generated from the DAC Reference as discussed in Sec. 4.1. The sum of the currents through to the binary-weighted resistor at the bottom of Fig. 9 produces the output voltage. DAC 1 and DAC 2 (see Fig. 3) are having the same architecture as in Fig. 9, the inputs name will be changed according to Sec. 4.2. This work only used a single magnitude of resistor to build the binary-weighted resistor string. This will increase resistor matching in order to get the better output linearity. Therefore, the resistors are arranged in parallel or series depending on the required values. For this design, the LSB resistor is ¯xed to be 15 . Therefore from simple calculation, a 120 resistor is chosen. Figure 10 shows the structure of the binary-weighted resistor string, each of resistor value 120 .
B[7] R
R
R
R
R
R
R
R
R
R
R
R
R
R
B[6]
B[5]
B[4] R B[3] R
R
B[2] R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
B[1]
B[0] R
Fig. 10. Binary-weighted resistor string.
DAC 2
721
S1
S2
DAC 1
12-Bit Pseudo-Di®erential Current-Source Resistor-String Hybrid DAC
DAC P
DAC N
Fig. 11. DAC Multiplexer diagram.
4.4. DAC multiplexer The DAC Multiplexer block works as the multiplexer to select output modes by using control signals S1 and S2. This is shown in Fig. 11. The combination of the NAND and NOT gates are used in the multiplexer design. Also included in this block are simple CMOS switches. The fourth terminal of the PMOS transistors is connected to VDD while the fourth terminal of the NMOS transistors is connected to GND. 5. Simulation Results The post-layout simulations are performed with the \nominal case" model of Silterra 0.18 m 1.8 V/3.3 V CMOS process technology. For the simulation, a 12-bit pattern D½11 : 0 is varied from 0 to 2 12 1 with an update rate of 10 MHz applied to the input port. The test bench is shown in Fig. 12. The load (resistor and capacitor) is chosen not large enough to a®ect the performance of the DAC. A simple current source/mirror is designed to provide the reference current for the DAC Reference
M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz
Fig. 12. Test bench.
722
12-Bit Pseudo-Di®erential Current-Source Resistor-String Hybrid DAC
723
circuit. The simulation result shown in Fig. 13 reveals that this design is monotonic with a gain error of 1.006. From Fig. 13, a full scale of 1.2069 V is achieved, while the minimum voltage (o®set) is 2.9 mV. The o®set is due to a small (leakage) current consumed by all the switches which is around 2.928 nA. The full scale voltage is slightly lower than the calculated value due to the current, I is 19.7 A and the value of the LSB resistor is lower than the intended value. The glitch occurs due to the transition state of switches. The worst glitch occurs during transition 011111111111 (code of 2047) to 100000000000 (code of 2048), where during this transition, all the switches seem to be ON temporarily. The glitch can be improved if very good nonoverlapping signals can be applied to each switchable current source. Table 2 shows the comparison between the calculated and simulation values of the DACN. Table 3 shows the results when the DACs are multiplexed. The overall results being compared with other DAC architectures is shown in Table 4. Figure 14 shows the layout of the complete 12-bit pseudo-di®erential hybrid DAC design.
Fig. 13. Full-scale simulation of the 12-bit hybrid DAC.
Table 2. Comparison of calculated and simulation values of DACN. Input
DACN(V)
P1
P2
Calculated
Simulation
0 0 1 1
0 1 0 1
1.2285 1.2093 19.2 m 0
1.2069 1.1870 21.838 m 2.933 m
724
M. T. S. Ab-Aziz, A. Marzuki & Z. A. A. Aziz Table 3. Results of DAC multiplexer output. Input
Output (V)
S1
S2
DACP
DACN
0 0 1 1
0 1 0 1
3.39 2.50 1.207 21.84 m
4.98 3.33 21.84 m 1.207
Table 4. Comparison of DACs.
Technology Resolution INL DNL Supply voltage Power consumption Full scale Operating frequency
Weighted current8
Thermometer code9
Switched current10
Hybrid6
This work
0.18 m 14-bit
