already more than 50A for a Pentium IV, and it will be even larger for the next generation of microprocessors. The large supply current not only poses a stringent ...
Design Considerations for VRM Transient Response Based on the Output Impedance * Kaiwei Yao, Yu Meng, Peng Xu and Fred C. Lee Center for Power Electronics Systems The Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA Abstract— This paper discusses the transient response of voltage regulator modules (VRMs) based on the small-signal models. The concept of constant resistive output impedance design for the VRM is proposed, and its limitation in application is analyzed. The impact of the output filter and the feedback control bandwidth shows that there is an optimum design for the VRM to achieve fast transient response, small size and good efficiency. Simulations and experimental results prove the theoretical analysis.
the transient comparison between non-AVP and AVP designs. It is very clear that the AVP design allows the use of fewer output capacitors, and hence reduces the VRM cost. Another benefit of the AVP design is that the VRM output power at full load is reduced, which greatly facilitates the thermal design. iO Vmax
I. INTRODUCTION
0.5*(Vmax-Vmin)
W/O AVP
As the clock speed of microprocessors is developed to be faster than 1GHz, a lower operation voltage is better for data processing efficiency. Currently, the supply voltage level is about 1.5V, and it will decrease further in the future. For such a low value, the allowable difference between the maximum and minimum voltage is very small. For example, a Pentium IV only allows a tolerance of about 130mV[1]. Conversely, the microprocessor is more power-hungry because of the high-density semiconductor integration. The supply current is already more than 50A for a Pentium IV, and it will be even larger for the next generation of microprocessors. The large supply current not only poses a stringent challenge on efficiency, but also adds a heavy burden on the transient response. One reason is the large current step; another one is the very fast current slew rate (50A/us now, and much higher in the future). Simply put, as a special power supply for the microprocessor, the voltage regulator module (VRM) must maintain a low output voltage within a tight tolerance range during the large current step transient with high slew rate. To meet such transient requirements, many capacitors are used in the VRM output, which increases the size and cost. Originally, the feedback control keeps the VRM output voltage at the same level for the entire load range. As a result, the output voltage spike during the transient must be smaller than half of the voltage tolerance window. If the output voltage level is a little higher than the minimum value at full load and a little lower than the maximum value at light load, the whole voltage tolerance range can be used for the voltage jump or drop during the transient. This is the concept of adaptive voltage position (AVP) design [2~3]. Fig. 1 shows * This work was supported by Intel, Texas Instruments, National Semiconductors, Intersil, TDK, Hitachi, Hipro, Power-One and Delta Electronics. Also, this work made use of ERC shared facilities supported by the National Science Foundation under Award Number EEC-9731677.
Vmin Vmax W/ AVP
Vmax-Vmin
Vmin Fig. 1. Transient without and with AVP designs.
The AVP is related to the steady-state operation of the VRM. If the transients between the two steady-state stages have no spikes and no oscillations, which situation is shown in Fig. 2, the AVP design is optimal. The transient can take advantage of the whole voltage tolerance window. The comparison between the current and the related output voltage waveforms (Fig. 2) reveals that the VRM equals an ideal voltage source in series with a resistor RO. Fig. 3 shows the equivalent circuit for the VRM. iO
∆ IO
Vmax VO
∆ VO
Vmin Fig. 2. The ideal AVP design for the transient.
Now it is very clear that the constant resistive output impedance design for the VRM is an optimum design for the transient. Actually, improving the dynamic regulation of a converter based on the output impedance consideration is an old concept [4~7]. However, not every converter can achieve constant resistive output impedance. Additionally, it is not clear how to design the feedback control loop. This paper
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clarifies these issues. Section II proposes a simple method to realize the constant output impedance. Both the voltage and current mode controls are discussed. Section III investigates the limitation of the constant output impedance design based on the small-signal analysis method. Finally, Section IV shows an example of optimal design. iO
RO= ∆ VO / ∆IO
+ Vmax VO
VRM
the parasitic resistance of the traces. The ESRC is the equivalent series resistance (ESR) of the output capacitor C. The ωo is the power stage double pole and the T(s) is the closed-loop gain. Fig. 5 shows the open-loop output impedance. At high frequencies, ESRC determines the output impedance. No matter how the closed-loop gain T(s) is designed, Zoc has the same value as Zo beyond the bandwidth. Feedback control can only attenuate the output impedance in the low-frequency range. As a result, the ESRC is the only value that is able to achieve the constant output impedance. 20
CPU
-
Zo
RL
40
Fig. 3. The equivalent circuit of the VRM for the ideal AVP design.
ESR C
60
Z oc
II. CONSTANT OUTPUT IMPEDANCE DESIGN Currently, the multi-phase synchronous buck converter is widely used for VRMs. The small-signal model can be simplified as a single-phase buck converter in continuouscurrent mode [8]. As a result, a simple buck converter, shown in Fig. 4, is used to analyze the output impedance with open loop and with closed loop. The equivalent series inductor (ESL) of the output capacitor is ignored here since the highfrequency ceramic capacitors in parallel greatly reduce its effect. Vin
Zo
QT
Z oc Vo
Gate Driver
d
Fm
QB
L
C ESRC
Ro
100 10
100
1 .10
3
4 1 .10
5 1 .10
6 1 .10
f(Hz)
Fig. 5. The output impedance with open and closed loops. .
The design method is simple. First, the closed-loop output impedance Zoc is derived: it is a function of the compensator transfer function Gcon(s). Then, Gcon(s) can be derived by solving the equation Zoc=ESRC. Finally, the compensator can be designed to be as close as possible to the ideal transfer function Gcon(s). Thus, some simple compensator designs can achieve approximately constant resistive output impedance. Both the voltage mode and peak current mode controls are discussed in the following section. A. Voltage Mode Control
-
Gcon + Vref
Fig. 4. Output impedance analysis using a buck converter.
Based on the small-signal analysis method [9~11], it is easy to derive the open-loop output impedance Zo and the closed-loop output impedance Zoc: (1 + s / ω C ) ⋅ (1 + s / ω L ) (1) Z o ( s) = RL 2 1 + s /(Q ⋅ ω o ) + s 2 / ω o Z ( s) , (2) Z oc ( s ) = o 1 + T ( s) 1 ,ω = L , ωc = L C ⋅ ESRC RL 1 , L /C . (3) Q≈ R L + ESR C C ⋅L Here, RL includes the DC resistance of the inductor L, the conduction resistance Rds-on of the MOSFETs QT and QB, and
ωo ≈
80
For voltage mode control, the closed-loop output impedance is: Z ( s) Z o (s ) , (4) Z oc ( s ) = o = 1 + T ( s ) 1 + Fm ⋅ Gvd ( s ) ⋅ Gcon ( s ) where Fm is the comparator gain and Gvd(s) is the transfer function of the output voltage Vo to the duty cycle d. Fig. 6 shows the ideal compensator transfer function to achieve Zoc=ESRC. Since the small-signal model is no longer effective beyond the half switching frequency, the real compensator design only needs to be accurate for the lowfrequency range. A single pole and zero compensator can satisfy this requirement. 1 + s / ω zv (5) Gcon ( s ) = K V 1 + s / ω pv Further mathematic analysis shows the detailed values of the DC gain, pole and zero. R L − ESRC (6) Kv = ESRC ⋅ Vin ⋅ Fm (7) ω pv = ω c
0-7803-7405-3/02/$17.00 (C) 2002 IEEE
b − b2 − 4 ⋅ a ⋅ c 2⋅a RL ESR C − a= 2 ωL ⋅ωc ωo
ω zv =
b = RL ⋅ (
(8)
Fig. 7 shows the closed-loop output impedance using this compensator design. It is almost constant. Simulation results in Fig. 8 show the nearly perfect transient response with AVP control. B. Current Mode Control
ESR C 1 1 + )− ωL ωc ωo ⋅ Q
c = R L − ESR C
(9)
20
Ideal
Compensator Gain 10
For current mode control, the analysis is slightly more complicated. Fig. 9 shows the dual-loop feedback control system. The peak current mode control is used as an example for this analysis. Since the current loop design is normally fixed according to the applied control chip, the major issue is how to design the voltage loop compensator.
App. 0
ω zv
Vin
ω pv
Z oi
QT
Z oc Vo
L 10
QB
20 1
10
100
3 1 . 10
4 1 . 10
5 1 . 10
6 1 . 10
Gate Driver
f (Hz)
C
Ri Ti
100
d
Compensator Phase
R
60
App.
Fm
20
Ro
ESRC Tv
Gcon
+
S CLK
20
60
Fig. 9. A buck converter using current mode control.
Ideal
100 1
10
100
3 1 . 10
4 1 .10
5 1 .10
6 1 . 10
f (Hz)
Fig. 6. Compensator design for voltage mode control. 30
dB
Zo
40
50
Zoc 60 1
10
100
3 1 . 10
4 1 . 10
5 1 . 10
Vref
6 1 . 10
f (Hz)
Fig. 7. The output impedance with voltage mode control.
25A
di/dt=50A/us
With the current loop closed, the output impedance with the open voltage loop is: T ( s ) Gvd ( s ) ⋅ Gii ( s ) , (10) Z oi ( s ) = Z o ( s ) + i ⋅ 1 + Ti ( s ) Gid ( s ) where Ti(s) is the current loop gain, Gii(s) is the inductor current to the load current transfer function, and Gid(s) is the inductor current to the duty cycle transfer function. The output impedance with the both loops closed is: Z oi ( s ) (1 + Ti ( s )) ⋅ Z oi ( s ) , (11) Z oc ( s ) = = 1 + T2 ( s ) 1 + Ti ( s ) + Fm ⋅ G vd ( s ) ⋅ G con ( s ) where T2(s) is the outer loop gain, which determines the system bandwidth and phase margin. Fig. 10 shows the ideal compensator transfer function to achieve Zoc=ESRC. As is the case for voltage mode control, a real compensator with one pole and one zero is good enough to come close to the ideal design. 1 + s / ω zi (12) Gcon ( s ) = K i 1 + s / ω pi Further mathematic analysis shows the detailed values of the DC gain, pole and zero as follows: Ri , (13) Ki ≈ ESR C (14) ω pi = ω c , and 1 , (15) ω zi = π ⋅ fs
Fig. 8. Simulation results with voltage mode control.
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where Ri is the current sensing gain and fs is the switching frequency. There is more physical meaning for the compensator design than was the case for voltage mode control. A pole compensates the output capacitor ESR zero, and a zero compensates the double right half plane zero introduced by the current sample and hold effect. Fig. 11 shows the closed-loop output impedance with this compensator design. It is almost constant. Simulation results in Fig. 12 show the nearlyt perfect transient response with AVP control. 10
Compensator Gain
Ideal ωzi
0
ωpi
10
20
App. 30 10
100
3 1 .10
4 1 .10
5 1 .10
6 1 .10
f (Hz) 20
Compensator Phase 0
Ideal
20
App.
40 60
80 10
100
3 1 .10
4 1 .10
5 1 .10
6 1 .10
f (Hz)
Fig. 10. Compensator design for current mode control.
III. LIMITATION OF THE CONSTANT OUTPUT IMPEDANCE DESIGN Based on the previous analysis, it seems that a VRM with any L or C values can achieve constant output impedance, but this is not true. For voltage mode control, if RLESRC, the DC gain is too low to attenuate the switching noise. Also, it is not easy to achieve current sharing between multi-channels with voltage mode control. The current mode control is different. The closed current loop makes the converter operate like a current source, which has very high output impedance at low frequency. The Zoi in Fig. 11 shows this clearly. As a result, the outer loop T2 needs a high DC gain to attenuate the output impedance at low frequency. However, there is a special requirement for the bandwidth in order to achieve the constant output impedance. Mathematical analysis shows that the bandwidth is just on the ESR zero of the output capacitor, as follows: 1 1 . (16) fc = ⋅ 2 ⋅ π C ⋅ ESR C This is easy to understand, since the open-loop output impedance Zoi (voltage loop open, but current loop closed) has a zero just on that point. Fig. 13 shows the relationship clearly. The ESR zeros of different kinds of output capacitors are also different. Fig. 13 shows that if the bandwidth is too near to half of the switching frequency, the system will not have sufficient phase margins and will become unstable. As a result, if the ESR zero is too high, it is impossible to realize constant output impedance. 40
T2
20
20
Zoi
25
fc
Gain
0.5·fs
0
30 35
Zo
40
20
Zoi
40
Zoc
45
60
50
Zoc
55 10
100
3 1 .10
10 4 1 .10
5 1 .10
6 1 .10
f (Hz) Fig. 11. The output impedance with current mode control.
100
1 2 ⋅ π ⋅ C ⋅ ESRC
3 1 .10
4 1 .10
5 1 .10
6 1 .10
5 1 .10
6 1 .10
f (Hz) 0 30
T2
60 Io
Io
90
Phase
120 Vo
Vo
150 180 10
100
3 1 .10
4 1 .10
f (Hz) Fig. 12. Simulation results with current mode control.
Fig. 13. The required outer loop gain.
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Table I lists the ESR zeros of three major kinds of output capacitors for the VRM application. For the Oscon capacitor, there is no difficulty in achieving 16KHz crossover frequency with 200~300KHz switching frequency. The ESRE is a special kind of electrical film capacitor produced by Cornell Dubilier; its size is much smaller than that of the Oscon. However, a higher switching frequency is required to achieve the 40KHz bandwidth. For the Ceramic capacitor, it is impossible to achieve constant output impedance with the state-of-the-art technology.
60
Capacitance 820µF 270µF 100µF
ESR 12mΩ 15mΩ 1.4mΩ
ESR Zero 16KHz 40KHz 1.1MHz
fc =
20
f0 =
20 40
However, the maximum inductor current slew rate cannot exceed the Faraday Law limitation, in which di/dt=Vo/L for step down and di/dt=(Vin-Vo)/L for step up. Larger value from Equation (19) means the duty cycle is saturated and the small-signal model is no longer effective. The equivalent points give the critical inductance value: Vin (20) Lci = ⋅ min( D,1 − D ) . 2 ⋅ π ⋅ ∆I o ⋅ f c
ω0 2 ⋅π
Open-Loop
60 10
3 1 .10
100
4 1 .10
5 1 .10
6 1 .10
f(Hz) Fig. 14. The inductor current transfer-function of current mode control. 1.2
SLmax = ∆io ⋅ ω c
1
The preceding analysis is based on the small-signal model. If the duty cycle is saturated, the closed-loop output impedance can no longer be used for transient analysis. Instead, the open-loop output impedance is effective in the transient. Since the open-loop output impedance is much larger than that of the closed-loop, the transient response of the former will be worse. To guarantee a good transient voltage waveform, the duty cycle should not become saturated. The critical inductance concept [8,12] reveals the point at which the duty cycle will go to saturation in a voltage mode controlled VRM. The crossover frequency determines the critical inductance value, above which the duty cycle will go to saturation. Vin (17) Lcv = ⋅ min( D,1 − D ) 4 ⋅ ∆I o ⋅ f c In the same way, a critical inductance value can be also derived for the current mode control. Fig. 14 shows the current transfer function Gii(s), and Fig. 15 shows the step response inductor current with peak current mode control. The inductor current with closed loop responds to the step load current change as a first-order system, in which the time constant is simply the bandwidth. The average inductor current during transient is Approximately: (18) i L (t ) = ∆I o ⋅ (1 − e − t ⋅2⋅π ⋅ f c ) , where fc is the crossover frequency. The inductor current slew rate with average small-signal model is: (19) SLiL (t ) = ∆I o ⋅ 2 ⋅ π ⋅ f c ⋅ e − t ⋅2⋅π ⋅ f c .
ωc 2 ⋅π
Closed-Loop
0
TABLE I. ESR ZERO FOR DIFFERENT KINDS OF CAPACITORS. Cap Type Oscon (SanYo) ESRE (CDE) Ceramic (TDK)
Outer-Loop Gain
40
0.8 0.6 0.4
1/ωc
0.2 0 0
1 .10
5
2 .10
5
3 .10
5
4 .10
5
t( s)
Fig. 15. The step-response of the inductor current.
As a result, in order to avoid duty cycle saturation, the output filter inductor should not be designed with a higher value than the critical inductance. Since a larger inductance value can improve efficiency by reducing the current ripple, the critical inductance value is a good design point for both transient and efficiency considerations. IV. A DESIGN EXAMPLE Based on the understanding of the constant output impedance design and its related limitations, an optimum design for certain output capacitors can be achieved, which simultaneously considers VRM size, transient and efficiency. A design process is shown here for a 12V to 1.6V/25A VRM using the Oscon capacitor shown in Table I. The required voltage tolerance is 100mV. With the constant output impedance design, the ESR of the output capacitor limits the transient voltage spike. In order to meet the 100mV voltage transient voltage spike requirement with 25A load current transient, the ESR of the output capacitors should be less than 4mΩ. As a result, four capacitors should be used in parallel. A commercial peak current controller (SIL6560) for twophase interleaving is selected for the VRM design. It can achieve current-sharing automatically, and the compensator can be designed according to the discussion in Section II to achieve constant output impedance. The outer-loop bandwidth is at exactly 16KHz, which is the ESR zero of the Oscon capacitor.
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Then, the output filter inductance can be determined based on the critical inductance value. 500nH is selected according to Equation 20 so that each channel inductance is 1µH. This inductance value can guarantee that the duty cycle will not become saturated during the transient. Finally, the switching frequency is selected according the bandwidth and the inductor current ripple. Here, a 250KHz switching frequency is selected, which easily achieves 16KHz crossover frequency with a stable system and is good enough to limit the inductor current ripple to 21% of the inductor DC current. Also, the switching frequency is not so high that the switching loss is relatively small. Two MOSFETs with SO-8 packages are used in each channel, one for the top switch QT and another for the bottom switch QB. Si4842 is selected for QT because of its low gate charge, and Si4442 is selected for QB because of its low Rds_on. The gate driver LM2726 is selected for its fast driving capability and very small dead time. Vishay’s surfacemounted inductor IHLP-5050CE is used for its small size and low profile. Fig. 16 shows the tested transient response waveform with the constant output impedance design. Perfect AVP is achieved. Fig. 17 shows the extended transient waveforms during the step-up and step-down periods. The duty cycle is not saturated during the transient with the critical inductance design. The tested outer-loop bandwidth in Fig. 18 shows that the crossover frequency is just on the ESR zero of the output capacitor. Fig. 19 shows the high efficiency achieved by using only four SO-8 MOSFETs based on the optimum design process.
Io
Vo
10A
Fig. 16. Experimental results for the transient.
Io
Vo
D VI. CONCLUSION (a)
This paper discusses the constant output impedance design method utilized to achieve perfect AVP for the VRM transient response. Both the voltage mode and current mode controls can achieve the constant output impedance. The limitation of voltage mode control is discussed. For current mode control, the bandwidth is just on the ESR zero of the output capacitor, such that the output capacitor determines the feasibility of the constant output impedance design method. Also, the limitation of the small-signal model shows the design guideline for the output filter inductance. Finally, an optimum design process is proposed, and a design example is given that achieves small size, high efficiency and good transient response. Simulation and experimental results prove that the constant output impedance design is a good design method.
Io
Vo
D (b)
ACKNOWLEDGMENTS The authors would like to thank Siliconix and Vishay for supplying free device samples.
Fig. 17. Extended transient waveforms: (a) step-down and (b) step-down.
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Outer-Loop Gain fc=16.6KHz Phase
Fig. 18. The tested outer-loop gain and phase.
0.9 0.88
Efficiency
85%
0.86 0.84 0.82 0.8 0
5
10 15 20 Load Current (A) Fig. 19. The tested efficiency.
25
30
Intel document, “VRM 9.0 DC-DC converter design guidelines,” Order number: 249205-002, April 2001. [2] M. Zhang, “Powering Intel Pentium 4 processors,” Intel Technology Symposium, 2000. [3] A.Waizman and C.Y. Chung, "Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology," IEEE Trans. Advanced Packaging, vol. 24, pp. 236−244, Aug. 2001. [4] R. Redl and N. O. Sokal, “Near-optimum dynamic regulation of Dc-Dc converters using feed-forward of output current and input voltage with current-mode control,” IEEE Trans. Power Electron., vol. 1, pp. 181−192, July 1986. [5] G. K. Schoneman and D. M. Mitchell, “Output impedance considerations for switching regulators with current-injected control,” in Proc. IEEE PESC, 1987, pp. 324−335. [6] L.D. Varga and N.A. Losic, “Synthesis of zero-impedance converter,” IEEE Trans. Power Electron., vol. 7, pp. 152−170, Jan. 1992. [7] R. Redl, B.P. Erisman and Z. Zansky, “Optimizing the load transient response of the buck converter,” in Proc. IEEE APEC, 1998, pp. 170−176. [8] P.L. Wong, “Performance improvements of multi-channel interleaving voltage regulator modules with integrated coupling inductors,” Dissertation of Virginia Polytechnic Institute and State University, March 2001. [9] R. Tymerski, V. Vorperian, F.C. Lee and W.T. Baumann, “Nonlinear modeling of the PWM switch,” IEEE Trans. Power Electron., vol. 4, pp. 225−233, April 1989. [10] R.B. Ridley, B.H. Cho and F.C. Lee, “Analysis and interpretation of loop gains of multiloop-controlled switching regulators,” IEEE Trans. Power Electron., vol. 3, pp. 489−498, Oct. 1988. [11] R.B. Ridley, “A new continuous-time model for current-mode control,” IEEE Trans. Power Electron., vol. 6, pp. 271−280, April 1991. [12] P.L. Wong, F.C. Lee, P. Xu and K. Yao, “Critical inductance in voltage regulator modules,” in Proc. IEEE APEC, 2002.
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