Complementary Thin-Base Symmetric Lateral Bipolar Transistors on SOI Jin Cai, Tak H. Ning, Chris D’Emic, Kevin K. Chan, Wilfried E. Haensch, Jeng-Bang Yau, Dae-Gyu Park IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598, USA Phone: 914-945-2310; Fax: 914-945-2141; E-mail:
[email protected] DEVICE CONCEPT AND EXPERIMENT RESULTS
ABSTRACT CMOS and bipolar technologies are intrinsically distinct. To take advantage of the beneficial attributes of both will drive expensive high mask count processes. We present a bipolar device architecture that will naturally integrate into an existing CMOS process flow without adding the complexity of vertical scaling present in the conventional high performance bipolar technologies. Symmetric thin-base silicon on insulator (SOI) lateral bipolar transistor is proposed. It overcomes the problems associated with conventional bipolar transistors including performance degradation at high current density and slow switching speed in saturation and fabricated samples show immunity to basepush-out effect. Simulation results suggest that THz fMAX is possible with current lithography capability and SOI thickness of 20 nm. Primary applications for low voltage and memory applications are discussed. INTRODUCTION While state-of-the-art vertical bipolar transistors, Fig. 1(a), still outperform CMOS in many analog and mixed signal applications, it is not suitable for use in digital applications because of the large footprint, and high supply voltage (VDD) / high power consumption in a current-switch logic circuit. Its collector-base junction area (ABC) is typically more than 3× larger than the emitter-base area, and the collector region is more lightly doped than the base region. Attempts to increase NC to a level comparable to NB will result in large increase in collector-base capacitance. This large and relatively lightly doped collector region causes vertical bipolar circuits to slow down dramatically if VDD is scaled to below 1V due to the saturation effect when the collector-base junction is forward biased and large amount of minority carriers are stored in the collector region. The lightly doped collector region also limits the high-frequency performance at high current densities due to base-push-out effect. With the advent of SOI technology, innovative thin-base lateral bipolar transistors without ABC penalty have been reported [1-3], see Fig. 1(b). But the asymmetric emitter/collector design still makes them vulnerable to base-push-out effect and not suitable for operation in saturation region, in addition to density/process cost issues. We propose a thin-base symmetric lateral bipolar transistor on SOI, shown in Fig. 1(c). We demonstrate building NPN and PNP on the same chip and show by simulation its capability of greatly extending high-frequency performance as well as suitability for low voltage applications.
978-1-4577-0505-2/11/$26.00 ©2011 IEEE
As indicated in Fig. 1(c), the quasi-neutral base is thinner than the physical base by the depletion layers on the emitter and collector sides. A 10nm quasi-neutral base can be patterned using 32 nm or larger CMOS gate patterning process, depending on the base doping concentration and thermal cycles. The high NC implies negligible base push out effect and minimal performance roll-off at high current densities, see Fig. 2. The emitter-collector symmetry implies suitability for circuits which operate in both forward- and reverse-active modes. We fabricated NPN and PNP transistors on the same chip with a PD-SOI CMOS compatible process flow on 60nm SOI substrate with a ‘gate’ length around 50nm, as illustrated in Fig. 3, using a standard CMOS maskset which is not optimized for bipolar. The gate stack includes a thin permeable oxide layer and a pre-doped polysilicon layer acting as the extrinsic base. The emitter and collector areas are implanted through an oxide hardmask protected gate stack. Fig. 4 shows the device cross-section after gate stack RIE and spacer etch. It shows no obvious recess in the exposed emitter/collector areas. Gummel plots for an NPN transistor and a PNP transistor measured after silicide are shown in Figs. 5-6 and Fig. 7, respectively. Forming gas anneal reduces recombination centers and improves the base current (Fig. 5). Series resistance is quite high due to the long silicide wires in the CMOS layout maskset (Fig. 6), and can be improved with optimized layouts for bipolar transistors. No roll-off of current gain is observed for up to a collector current density (JC) of 7mA/µm2, whereas base push-out causes roll-off in a vertical transistor at JC=0.5mA/µm2 with a collector doping of 1017/cm3 (Fig. 8). Measured output characteristics are shown in Figs. 9 and 10 respectively for an NPN and a PNP. PERFORMANCE ANALYSIS AND CIRCUIT INNOVATION We simulated fT and fMAX of the proposed device using commonly accepted bipolar models [4] for the two NPN transistors listed in Fig. 11. The more aggressive design (NPN2) has a thinner silicon thickness (20nm) and a higher base doping level (1019/cm3). The parasitic resistance and fringe capacitance assumptions are consistent with process capabilities. The quasi-neutral base width is 10nm in both cases, which is narrower than the metallurgical base width (~30nm) by the two depletion regions, as illustrated in the energy band diagram in Fig. 12. The equivalent circuit model and the formulas for fT and fMAX calculation are shown in Fig.
16.3.1
IEDM11-386
13. The model results are shown in Fig. 14. The thin silicon design (NPN2) has a lower base resistance and hence a higher fMAX that can exceed 1THz at JC=10mA/µm2. As a reference, the state-of-the-art vertical SiGe HBT data is also plotted [5]. The potential for this simple bipolar structure to out-perform the state-of-the-art SiGe HBT makes a compelling case for analog/mixed signal applications. In addition, the emitter-collector symmetry makes the device suitable for circuits involving both forward- and reverse-active modes of operation. In Fig.15, we propose a complementary bipolar inverter circuit and compare it with a conventional CMOS inverter. The bipolar transistors have a higher transconductance than CMOS thanks to the exponential dependence of drive current on the input voltage. Measured inverter transfer curves show a higher gain than CMOS inverter which can be maintained at VDD of 0.5V (Fig. 16). The complementary bipolar enables lower stand-by leakage current as compared to current switch logic. The leakage current is determined by the base current instead of the collector current (Fig. 17). Two complementary bipolar inverters can be cross-coupled to form a storage element in a SRAM cell in a BiCMOS platform (Fig. 18). The modeled static noise margin at VDD=0.5V can be improved with an increase in current gain, as shown in Figs. 19 and 20. Also, noise margin remains large even when there is large mismatch in current gains, as shown in Fig. 21. To avoid read disturbance, VEE can be pre-set to negative levels to boost the bipolar current. E
B
CONCLUSIONS We demonstrate NPN and PNP thin-base symmetric lateral bipolar transistors on SOI. The transistor is simple to build and can overcome some major performance limiting factors such as base push-out and minority charge storage. Modeling results show possibilities for high frequency analogy/mixed signal applications with fMAX > 1THz as well as for digital applications at supply voltage of 0.5V. ACKNOWLEDGEMENT This work was performed at the IBM Material Research Lab at Yorktown Heights. The authors would like to thank Drs. G. Shahidi, E. Leobandung and J. Sleight for technical discussions and management support. REFERENCES 1. 2. 3. 4. 5.
G. Shahidi D. Tang, B. Davari, et al., “A novel high-performance lateral bipolar on SOI”, IEDM Tech. Dig., pp. 663-666, 1991. S. Parke F. Assaderaghi, J. Chen, J. King, C. Hu and P. Ko, “A versatile BiCMOS technology with complementary lateral BJT’s”, IEDM Tech. Dig., pp. 453-456, 1992. R. Dekker, W. Einden, H. Maas, “An ultra low power lateral bipolar polysilicon emitter technology on SOI”, IEDM Tech. Dig., pp. 75-78, 1993. Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 2009. M. Khater, J. Rieh, T. Adam, A. Chinthakindi, J. Johnson, et al., ”SiGe HBT technology with fmax/ft=350/300 GHz and gate delay below 3.3psec”, IEDM Tech. Dig., p. 247-250, 2004.
C
p+ E
p+ n−
p n
p+ n−
n-
n+ p
n+
B
B
n+ polysilicon p+ polysilicon
p+ polysilicon
C
E
n+
n+
(a)
n+
substrate
substrate p− substrate
p
C
BOX
BOX
n+ subcollector
p+
(c)
(b)
Fig. 1. Schematics of NPN bipolar transistors: (a) conventional vertical bipolar transistor, (b) previously reported asymmetric SOI lateral bipolar transistor [1] and (c) symmetric lateral SOI bipolar transistor with thin base enabled by CMOS lithography capability. The dash lines indicate depletion layer boundaries.
SOI lateral bipolar
fT vertical bipolar
CMOS
Bipolar
Well implant RTA
Base implant
Gate dielectric
RTA Permeable oxide
Gate electrode
Pre-doped polysilicon
Gate stack RIE
Oxide HM and gate RIE
Spacer 1 Halo/extension Spacer 2 Source/drain implant
Log collector current density
RTA
LG SOI
TSI
BOX Spacer Emitter/collector implant RTA silicide
Fig. 4. SEM picture of SOI bipolar transistors after spacer etch. A thin permeable oxide is used as an Fig. 2. Better immunity to performance rollFig. 3. Common CMOS flow and lateral SOI bipolar etch stopper to minimize silicon recess. Silicon off in SOI lateral bipolar over vertical thickness is ~ 60nm and gate length is ~50nm. flow. Underlined processes are bipolar specific. bipolar transistors.
IEDM11-387
silicide
16.3.2
1E-3
1E-3
1E-3 Ic Ib
60mV/dec
Ic, before FGA Ib, before FGA Ic, after FGA Ib, after FGA
1E-9
1E-6 Ic, data Ic, model Ib, data Ib, model
1E-9
TSOI=60nm
1E-12 0.5
IC, IB (A/μm)
1E-6
IC, IB (A/μm)
IC, IB (A/μm)
60mV/dec
1E-12 0.5
1.5
1.0
VBE (V)
100
1000
TCAD, sym. lateral NPN
0.1
1
10
-0.5
Fig. 7. Measured Gummel plot for a lateral PNP bipolar transistor made on the same wafer as the NPN bipolar transistor.
200
IB=0.1μA to 0.5μA
IB=1μA to 10μA
150
60 40
100 50
20
Data
0.01
-1.0
VBE (V)
IC (μA)
100
1E-3
PNP TSOI=60nm
1E-12 -1.5
1.5
TSOI=60nm
80
IC (μA)
Current Gain
TCAD, vertical NPN
1 1E-4
1E-9
VBE (V)
Fig. 5. Measured Gummel plots for a lateral NPN Fig. 6. Correlation of measured data with an SOI bipolar transistor before and after forming analytic bipolar model assuming an emitter and gas anneal. base series resistance of 4.7 kΩ and 4.0 kΩ respectively.
10
1E-6
TSOI=60nm
1.0
60mV/dec
0 0.0
0.5
2
1.0
0 -1.5
1.5
-1.0
VCE (V)
JC (mA/μm )
Fig. 8. Current gain as a function of collector Fig. 9. Common-emitter output characteristics current density. Measured data for lateral SOI from a fabricated NPN lateral SOI bipolar transistor. bipolar shows no roll-off up to 7mA/µm2.
n+
Tsi
p
Cμ
rb
rc C
B
p+
Cπ E
0.0
Fig. 10. Common-emitter output characteristics from a fabricated PNP lateral SOI bipolar transistor.
B WE
-0.5
VCE (V)
n+
r'π (1+g'm re)
r'0 g'mvbe /(1+g'm re)
C
re E
E W dBE
WdBC
EC Ef
n+
p
n+
EV
WB(VBE = 0)
Fig. 11. Device design parameters used for modeling AC performance of SOI lateral bipolar transistors.
1 kT =τF + (CBE + CBC ) + CBC (re + rc ) 2π fT qI C
f max =
fT 8πrbCBC
Fig. 12. Schematics of the SOI bipolar transistor Fig. 13. Equivalent circuit and models for fT and and the energy band diagram under equilibrium fMAX. Fringe capacitance and parasitic resistance from E to C. The quasi-neutral base region width are included in the model parameters. WB is pinched by the depletion regions near E and C.
16.3.3
IEDM11-388
1200
fT, fMAX (GHz)
1000 800 600
VDD
VCC
NPN1, fmax NPN1, fT NPN2, fmax NPN2, fT SiGe HBT, fmax SiGe HBT, fT
ID ~ Gm%(VDD-VT)
IC~ exp(qVCC/kT)
Vout
Vin
Vout
Vin
400 200 0 1E-3
0.01
0.1
1
10
100
Fig. 14. Modeled high-frequency characteristics for the two transistor designs. The fMAX of the more aggressive design breaks the THz barrier. Lines are state-of-the-art vertical SiGe HBT data [5].
Ground
Ground
2
JC (mA/μm )
Fig. 15. Circuit diagrams of a complementary bipolar inverter and a CMOS inverter. Drive current in a bipolar inverter has an exponential dependence on supply voltage vs. a linear dependence in a CMOS inverter.
WL
1E-5
1.0
-6
0.8
SOI-BJT Vdd=0.7V
0.6
0.5V
SOI-BJT Vdd=1V
Leakage (A/μm)
VOUT (V)
10
0.4 CMOS Vdd=1V
0.2 0.0 0.0
0.2
0.4
0.6
0.8
1E-7
-12
10
1E-9
0.0
0.5
1.0
VIN (V)
1E-11
Inverter 2*IB
1E-13 0.0
1.0
VDD (= VCC)
-9
10
0.2
0.4
0.6
0.8
1.0
VDD (V)
VIN (V)
Betanpn = 30 Betapnp = 30
0.2 0.1
0.4 0.3 0.2 0.1 0
0 Vout1
0
0.1
0.2
0.3
Vin1; Vout2 (V)
0.4
0.5
0.6
-0.1 -0.1
0.3 0.2 0.1
0
Vin2
0.1
Vout1
0.2
0.3
0.4
0.5
0.6
Vin1; Vout2 (V)
Fig. 19. Modeled butterfly curves of a cross- Fig. 20. Modeled butterfly curves of a crosscoupled complementary bipolar inverter coupled complementary bipolar inverter. A operating at 0.5V. Current gain is 30 for both higher current gain leads to a higher noise margin. NPN and PNP transistors.
IEDM11-389
0.4
0 Vout1
Vin2
Betanpn = 1000 Betapnp = 30
0.5 Vout1; Vin2 (V)
0.3
-0.1 -0.1
0.6 Betanpn = 1000 Betapnp = 1000
0.5
Vout1; Vin2 (V)
Vout1; Vin2 (V)
0.4
BLC
Fig. 18. Proposed static memory cell using cross-coupled complementary bipolar inverters as memory elements for low voltage applications.
0.6
0.6 0.5
Vee
BLT
Measured leakage current of a Fig. 16. Measured transfer curves for a CMOS Fig. 17. inverter at VDD =1V and for a complementary complementary bipolar inverter and its correlation to 2×IB. The inset shows measured SOI bipolar inverter at VDD =0.5, 0.7 and 1V. inverter leakage vs. the input voltage at VDD=1V.
16.3.4
-0.1 -0.1
0
Vin2
0.1
0.2
0.3
0.4
0.5
0.6
Vin1; Vout2 (V)
Fig. 21. Modeled butterfly curves of a crosscoupled complementary bipolar inverter, indicating high noise margin even when there is large mismatch in current gain.
