High-Performancce Few-Layer-MoS2 Field-Effect-Transsistor with R Record Low Contact-Resistance Wei Liu+, Jiahao Kang+, Wei Cao+, D Deblina Sarkar+, Yasin Khatami+, Debdeep Jena++ and Kaustav Banerjee+ +
Department of Electrical and Com mputer Engineering, University of California, Santa Barb bara, CA 93106 ++ Department of Electricall Engineering, University of Notre Dame, Notre Dame, IN N 46556 Email: {liuwei, jiahao_kang, weiccao, deblina, yasin} @ece.ucsb.edu;
[email protected]; kaustav@ @ece.ucsb.edu Abstract
Recently, Molybdenum Disulphide (MoS2) has emerged as a promising candidate for low-power digital appliications. Compared to monolayer (1L) MoS2, few-layer MoS2 (FL-M MoS2) is attractive due to its higher density of states (DOS). Howeveer, a comprehensive study of FL-MoS2 field-effect-transistor (FET) is lacking. In this ET with record low paper, we report a high-performance FL-MoS2 FE contact resistance (~0.8 kΩ.µm) that is close to tthe value for metalsilicon contacts in CMOS technology. A corrrelation of device performance and the number of MoS2 layers is eestablished to guide the design of high-performance FL-MoS2 FET T. Moreover, it is found that edge contacts (metal contact to each eddge of MoS2 layers) play a key role in the efficient injection of electtrons from metal to MoS2. This is confirmed by experiments ass well as density functional theory (DFT) calculations. Moreoverr, a top gated FLMoS2 (5 nm) FET is also demonstrated withh a robust current saturation and high drive current (24 μA/μm) even without source/drain doping.
Introduction MoS2 (Fig. 1a), one of the transition-metal dichalcogenides (TMDs) shows promising properties for future nnanoscale FETs due to its non-zero band gap (Fig. 1b), atomic sccale thickness, and pristine interfaces (without out-of-plane dangling bonds, Fig. 1a) [1]. S2 allows excellent The atomically-thin 1L or few-layer (FL) MoS gate electrostatics to suppress short-channel-effeccts (SCE), which is one of the major issues in scaled metal-oxide-seemiconductor-FETs (MOSFETs) [2]. However, it has been challengiing to achieve high mobilities in 1L MoS2. While a theoretical caalculation predicted room-temperature mobility of 1L MoS2 up to ~410 cm2/V.s [3], L MoS2 on oxide experimental work on carrier transport in 1L substrates have reported low mobilities in the range of 0.1-10 cm2/V.s [1]. In the meantime, the effect of hhigh-κ dielectric in boosting the mobility of 1L MoS2 is being exploreed [4]. On the other hand, a high contact resistance between metal and 1L MoS2 degrades the performance of 1L MoS2 devices. In fact, metal-semiconductor contact is one off the critical factors that determine the performance of 2-ddimensional (2-D) semiconductor devices [5]. Compared with 1L L MoS2, FL MoS2 flakes (defined as several nm to sub-10 nm in this work), have a higher DOS (Fig. 1c) than that of 1L MoS2, whhich can potentially lower contact resistance and carry higher currrent. Moreover, FL MoS2 flakes retain the capability of overcomingg SCE. Hence, it is desirable to study FL MoS2 FET devices to maxximize performance of future MoS2 devices. However, the reported eexperimental works exhibit high contact resistances and small ON-cuurrents on FL MoS2 devices [6-8]. In addition, the effect of contacts on the operation of FL MoS2 FET and the mechanism of electronn injection into FL MoS2 channel still remain unclear. In this papper, we report and demonstrate an approach to achieve high-perfoormance FL MoS2 FETs and highlight the role of edge contacts in their design.
Device Fabrication MoS2 films are prepared by mechanical exffoliation from bulk MoS2 (purchased from SPI) on 90 nm SiO2/Si substrate. The
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Fig. 1 (a) Various views of the lattice strructures of TMDs. There are no dangling bonds on the surface, which leads to reduced surface D of MoS2 as a function scattering. (b) Band gap (calculated by DFT) of number of layers. 1L MoS2 has a direct band gap of 1.8 eV, while bilayer and bulk (> ~5 L) have an indirrect band gap of 1.5 eV and 1.2 eV, respectively [9]. (c) DOS of 1L L and bulk MoS2. It clearly shows that bulk MoS2 has higher DOS th han that of 1L MoS2.
Fig. 2 (a) Optical microscope images off 1L, 6 nm, and 10 nm MoS2 FET with Ti contact on SiO2 (90 nm)/S Si (n++) substrates. For fourpoint-measurements, current flows from m V1 to V4. Voltages are measured on V2 and V3. Channel resisstance is calculated as (V2V3)/I. The scale bar is 5 µm. (b) Scheematic of a back-gated FET device. Au (100 nm) deposited on top of Ti (10-50 nm) is used as contact metals. (c) AFM image of fabriccated MoS2 back-gated FET. (d) AFM measured height of MoS2 flak ke in (c) along the red line. MoS2 area is indicated by yellow dash lin ne in (c).
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Fig. 3 Annealing effect on the contact and device performance. (a) Ids-Vds characteristics of MoS2 (5 nm) FET with Ti contact without annealing measured at 5×10-6 mbar. (b) Ids-Vds characteristics of the same device after annealing at 420 K at 5×10-6 mbar. All the measurements are carried out at room temperature. thickness of the MoS2 films are identified using optical microscope (Fig. 2a) and atomic force microscope (AFM) (Fig. 2c, d). The source and drain are defined by electron-beam lithography followed by metallization (Ti and Au). Fig. 2b shows the detailed information of our back-gated 1L MoS2 FET device. Fig. 3 shows that annealing can significantly improve device performance and reduce the contact resistance. Before annealing, MoS2-Ti contact shows clear Schottky behavior as indicated by the nolinear Ids-Vds characteristics in Fig. 3a. After annealing, MoS2-Ti contact exhibits an ohmic behavior as confirmed by the linear Ids-Vds characteristics shown in Fig. 3b.
Mobility and Contact Resistance of MoS2 FET Mobilities of MoS2 with various thicknesses are extracted from the plots of channel conductance (G) as a function of back gate voltage (Vbg) shown in Fig. 4a, b, c, which are obtained from fourpoint-measurements. 1L MoS2 exhibits a mobility of 13.2 cm2/V.s
Fig. 4 Channel conductance (G) of (a) 1L, (b) 5L and (c) 15L MoS2 FETs with Ti contact as a function of Vbg, values of G are measured by four-point-measurements. (d) Intrinsic mobility (excluding the effect of contacts) of MoS2 as a function of the number of layers. The mobility of MoS2 can be extracted as µ=(L/W)dG/dVbgCox-1, where Cox is the capacitance of the 90 nm-thick bottom SiO2 dielectric; L and W represent the length and width of the channel, respectively. It was found that the intrinsic mobilities of few layer MoS2 FETs (varying from 40 cm2/V.s to 100 cm2/V.s) show strong dependence on the original bulk samples from which they are derived. In this work, all the devices are fabricated based on the MoS2 purchased from SPI.
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Fig. 5 Ids-Vbg characteristics of (a) 1L and (d) 15L MoS2 FETs (from Fig. 4) with Ti contacts, at Vds=0.1V. (b), (e) corresponding Ids-Vds characteristics of (a) and (d), respectively. (c), (f) Rcontact, Rchannel, and source-drain resistance (Rtotal) as a function of Vbg for 1L and 15L, respectively. Rtotal = 0.01V/Ids, in which Ids is obtained from two-terminal Ids-Vbg measurement. Rcontact of 1L MoS2 FET with Ti contact is around 740 kΩ.µm at Vbg=30 V, while 15L MoS2 FET with Ti contact exhibits a record low Rcontact of ~0.8 kΩ.µm when Vbg> -10 V. on SiO2 substrate. It is observed that mobility of MoS2 FET increases with thickness (for number of layers < 9L) as shown in Fig. 4d. Our FL MoS2 FETs show higher mobility than 1L MoS2 FET, in agreement with reported results [6]. However, for the first time, we present a systematic study of the dependence of mobility on the number of layers of MoS2. Bilayer MoS2 FET exhibits a mobility of 21 cm2/V.s. For few layer MoS2 (5L and 8L), the mobilities are ~55 cm2/V.s, which is nearly 4 times higher than that of 1L MoS2. It is known that scattering from the interface of MoS2SiO2 is the major reason degrading the mobility of 1L MoS2. Hence, with increasing thickness of MoS2, interface scattering is partially screened, thereby leading to the enhancement of mobility that is mostly contributed from the upper layers. For the thickest MoS2 flake (15L), mobility slightly degrades to ~45 cm2/V.s. Hence, FL (5-15L) MoS2 shows good potential for applications in high performance digital circuits in terms of better mobility than that of 1L MoS2. Fig. 5a, d show the transfer characteristics of back-gated (Fig. 5a/Fig. 5d: 1L/15L) MoS2 FETs with Ti contacts. They clearly display n-type behavior. As shown in Fig. 5e, the Ids-Vds curves of (15L) MoS2 FET display a better linear behavior and larger ONcurrent than that of 1L MoS2 FET (Fig. 5b). In general, the linear behavior of Ids-Vds curves of FET indicates that the contact is ohmic in nature. Compared to the small gate modulation of the channel resistance (Rchannel) (Fig. 5c, f), there is a very large gate modulation effect (~106) on the contact resistance (Rcontact) when the back gate voltage (Vbg) is swept from -30 V to 30 V, indicating that (1L or FL)
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Fig. 6 (a) Temperature dependent Rcontact of 1L L and 15L MoS2-Ti contact at Vbg=30V. (b) Band diagram of 1L (toop) and 15L (down, light blue schematic shows Fermi distribution of electrons in contact metal) MoS2 back-gated FETs with Ti contact at ssame gate voltage. back-gated MoS2 FETs operate as unconventionnal Schottky Barrier (SB) FETs, in which switching occurs primarrily by modulating Rcontact rather than Rchannel. Hence, a device w with top gate (with underlap between gate and source/drain) is neeeded to avoid SBFET-like switching. Rcontact of 1L MoS2 FET with Ti contact is MoS2 FET exhibits a around 740 kΩ.µm at Vbg=30 V, while the 15L M record low Rcontact of ~0.8 kΩ.µm when Vbg> -4 V. This record low Rcontact is close to the metal-silicon contacts in CMOS technology [10], and represents a major advancement from ccurrent state-of-theart MoS2 transistors. Compared to FL MoS2 FETs with Au/Ni contact (4-17 kΩ.µm) [11], FL MoS2 FET with T Ti contacts exhibits a smaller Rcontact that shows a smaller dependennce on applied Vbg, indicating that Ti forms better contact with FL MoS2 than that of when Vbg is above a Au/Ni. The lower dependence of Rcontact on Vbg (w certain value) also reflects that Ti can heavily ddope MoS2, thereby resulting in a good contact, which has also beenn confirmed by our previous theoretical work [5]. As shown in Fig. 6a, 15L MoS2-Ti contact haas a smaller Rcontact than that of 1L MoS2-Ti contact, and the Rcontact oof both 1L and 15L MoS2 decreases with increase of temperature due to enhanced thermionic emission over the Schottky barrier (Fig. 6b). At high temperatures, electrons can occupy higher energgy levels leading to more electrons flowing over the Schottky barrier and contributing to the current injection, thereby reducing the contact resistance. However, when temperature is above 300 K, Rcontact of 15L MoS2 exhibits much smaller change (~0.2 kΩ.µm) thaan that of 1L MoS2 (~30 kΩ.µm), indicating that thermionic emission has lower impact on 15L MoS2-Ti contact. This implies that the Schottky barrier of 15L MoS2-Ti contact is much smaller and thinnner than that of 1L MoS2-Ti contact. Therefore, FL MoS2-Ti devvices enable better contacts, in which tunneling through the Schottkyy barrier dominates the drive current due to the small and thin barrier..
Fig. 8 DFT simulation of top contact. (a) ( Side view of the relaxed contact regions at the interface between n MoS2 (3L) –Ti surface. (b) Contour plots of the average electron n density. The contour plot represents the average electron density along a the x-axis. Right hand side shows the plot of average electron n density along the x-y plane corresponding to MoS2 (3L) – Ti system m. (c) Partial density of states (PDOS) of first layer (L1) (with Ti co ontact) MoS2. (d) PDOS of second (L2) and third layer (L3) of MoS S2. Ti only influences the top layer (L1) of MoS2 due to the formatio on of Ti-S bonds. The band gap of first layer (L1) MoS2 vanishes aft fter contact with Ti, while L2 and L3 still have large Schottky barriers (ΦSB). lower Rcontact due to its multiple conduccting channels. However, an Rcontact ~ 53 kΩ.µm (Fig. 7) is measu ured from a 30 nm (~46L) MoS2-Ti contact. Rcontact of this device is significantly higher than that of 5L-15L MoS2-Ti contacts. Thiis high Rcontact of the ~46L MoS2-Ti contact arises due to the fact that t the electrode metal may contact the top several layers only, indiccating that edge-contacts are important for achieving low resistancce. In addition, Vbg cannot modulate the top layers due to the Vbg sccreening, hence resulting in a high Rcontact. Fig. 8a shows the relaxed contact reg gions at the interface between MoS2 (3L) –Ti surface for DFT calculaations. For a top contact (Ti contacting the top layer only), there is a high electron density (0.027 Å-3) between the upper-most MoS2 layeer and Ti, while the electron density stays constant between MoS2 layers l (L1-L2 and L2-L3 in
Charge Injection from Metal too MoS2 For a thick MoS2 flake, MoS2-Ti contact is eexpected to provide
Fig. 7 Rcontact of 30 nm (46L) MoS2-Ti contact. ((a) Ids-Vds curves of 30 nm MoS2 FET after annealing at 420 K at 5×10-6 mbar. Inset shows the optical image of the measured devicce. Contact: 50 nm Ti/100 nm Au. (b) Rcontact, Rchannel, and Rtotal as a ffunction of Vbg.
Fig. 9 DFT simulation of edge contactt. (a) Schematic view of an edge contact. (b) Side view of the rellaxed contact regions at the interface between MoS2 (3L) -Ti. (c) PD DOS of each layer of MoS2 with Ti (L1, L2, L3 from top to botto om). Sulfur atoms can form strong covalent bonds with Ti, hence the MoS2 (edge-contacted) y the PDOS plots of the three loses its band gap, which is reflected by MoS2 layers shown in (c), indicating an ohmic contact.
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Fig. 10 (a) Temperature dependent Ids-Vbg charaacteristics for MoS2 (15L) FET, Vds=0.01 V. (b) Schematic of bandd diagram of MoS2 FET at different Vbg. Fig. 8b). The doping effect on the first MoS2 layeer is also confirmed from the PDOS (Fig. 8c, d). After depositing Ti onto the first layer of MoS2, its band gap vanishes due to the dopinng effect. However, L2 and L3 still have the band gap. Therefore, foor a top contact (Ti contacting the top layer only), the DFT calculatiion (Fig. 8) reveals that Ti solely influences the upper-most layer of M MoS2 leading to the experimentally observed performance degradationn (Fig. 7). To achieve high current, most of the MoS2 layyers should connect to the contact metal from the side or edge (edgee contact shown in Fig. 9a, b). The DFT calculation (Fig. 9c) showss that sulphur atoms can form strong covalent bonds with Ti atom ms, which not only provide access to all available conducting channeels but also reduces the Rcontact. Fig. 10a shows the temperature dependent Ids-Vbg curves for MoS2 (15L) FET. At Vbg-4V indicating that current is dominated by tunneliing when Vbg>-4V. Thus, for a good FL MoS2-Ti contact, tunnelling dominates the current due to sufficient electrostatic doping (Fig.. 10b).
Table I. Rcontact, intrinsic mobility off MoS2 FETs with various thicknesses on SiO2 (90 nm)/Si substrattes. 1L, 2L, 5L and 8L MoS2 FETs have Ti (10 nm)/Au (100 nm) contacts, while 15L and 46L 0 nm) contacts. Mobility is MoS2 FETs have Ti (50 nm)/Au (100 calculated from channel conductancee (measured by four-pointmeasurements)-Vbg plots at Vds= 0.01 V and Vbg is swept from -30 V to 30 V. Note that back-gated devics haave higher ION than top-gated devices, which can be attributed to thee fact that back gate voltage always modulates the Schottky barrier at a S/D regions, while top gate voltages can not thin the Schottky barrier due to the device geometry (Fig.11a) of top-gated devicess. Layer #
1L
2L
5L
8L
15L
Rcontact (KΩ.µm)
740
15.6
1.56
1.24
0.78
53
Mobility (cm2/V.s)
~13
~21
~52
~54
~47
~19
Top gate ION (µA/µm) Vds=1V
1.2 Vtg=0V
N/A
N/A
24 N/A Vtg= -2.2V
N/A
Back gate ION (µA/µm) Vds=1V, Vbg=30V
10
20
46
40
30
46L
6.7
With a top-gate geometry (Fig. 11 1a), it is possible to avoid modulating the Schottky barrier (due to o the underlap between gate and source/drain) and provide better electrostatics e (Fig. 11c). FL MoS2 FET with Ti contact exhibits a ro obust current saturation with an ON/OFF ratio of about 106 (Fig. 11d), 1 and has higher current compared to 1L MoS2 FET with Ti conttact (Fig. 11b). Even without doping in the source/drain area, the ON-current of our device is still comparable to the recently reported K-doped K FL MoS2 FET with ZrO2 (17.5 nm) top dielectric film [12]. Doping can certainly lead to further reduction of contact resistance and hence, to even higher ON-currents in future MoS2 FET devicees.
Summary y In summary, this work presents a high h performance FL MoS2 FET with record low contact resistance (~0.8 8 kΩ.µm) using Ti as contact metal. For FL MoS2 devices, good edg ge contacts can significantly enhance device performance. The ben nefit of making good edge contacts is demonstrated by our top-gateed FL MoS2 FET that exhibit high ON current (24 μA/μm for 5 nm MoS2) even without source/drain doping. As summarized in Table I, few-layer (5L-15L) MoS2 FETs show better potential forr high performance digital circuits due to their small contact resistaances and high mobilities.
Referencess
Fig. 11 (a) SEM image of a top-gated MoS2 FE ET with Ti contact. Top gate dielectric layer is 30 nm HfO2 depositted by atomic layer deposition (ALD) at 200 oC. (b) Ids-Vds curves off top-gated 1L MoS2 FET with Ti contact. Vtg varies from -1 V to 0 V at a step of 0.2 V. (c) Ids-Vtg curve of a top-gate few-layer (5 nm) MoS2 FET with Ti contact, Vds=0.1 V. (d) Ids-Vds curves of top-gateed 5 nm MoS2 FET with Ti contact. Vtg varies from -4.6 V to 2.2 V at a step of 0.4 V. Few layer MoS2-FET with Ti contact exhibitss a perfect current saturation and an ON/OFF ratio of about 106, andd has a higher drivecurrent than that of 1L MoS2 FET as shown in (b)).
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[1] B. Radisavljevic, et al., Nature Nanoteechnology, vol. 6, pp. 147-150, 2011. [2] Y. Yoon, et al., Nano Letters, vol. 11, pp. 3768-3773, 2011. v 85, 2012. [3] K. Kaasbjerg, et al., Physical Review B, vol. [4] M. S. Fuhrer and J. Hone, Nature Nanottechnology, vol. 8, pp. 146-147, 2013. p. 407-410. [5] J. Kang, et al., Tech. Dig. IEDM, 2012, pp [6] S. Kim, et al., Nature Communications, vol. 3, pp. 1011, 2012. [7] E. S. Kim, S. Kim, Y. S. Lee, et al., Tech. Dig. IEDM, 2012, pp. 108-111. ference (DRC), 2012, pp. 65-66. [8] T. N. Adam, et al., Device Research Confe [9] A. Kuc, N. Zibouche, T. Heine, arXiv:110 04.3670 [cond-mat.mtrl-sci] [10] International Technology Roadmap for Semiconductors (2012), http://www.itrs.net/. Source/drain parasitic seeries resistance is in the range of 0.3 -0.5 kΩ.µm (290 Ω.µm, 405 Ω.µm and 467 Ω.µm for Planar, SOI, Multigate low standby power CMOS, respectively), which is dominated by the contact resistance. 3-8569, 2012. [11] H. Liu, et al., ACS Nano, vol. 6, pp. 8563 [12] H. Fang, et al., Nano Letters, pp.1991–1995, 2013.
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