1~99% Input Duty 50% Output Duty Cycle Corrector Hong-Yi Huang Department of Electronic Engineering Fu Jen Catholic University Taiwan, R.O.C.
Chia-Ming Liang Department of Electronic Engineering Fu Jen Catholic University Taiwan, R.O.C.
Wei-Ming Chiu Department of Electronic Engineering Fu Jen Catholic University Taiwan, R.O.C.
e-mail:
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e-mail:
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e-mail:
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Abstract—This work presents a high bandwidth and wide input duty range duty cycle corrector. A combined charge pump stabilizes the current/sink. A second order differential low-pass filter enhances the stability of the closed loop. A simplified low-voltage amplifier increases the input common-mode range. The accuracy of output duty cycle, the operating frequency range and the stability of the circuit are improved. Using 0.18um CMOS process for simulation, the circuit obtains 50% output duty at 800-MHz with 1-99% input duty cycle at a minimum supply voltage of 1.2V. The minimum and maximum operating frequencies are 20-MHz and 2.6GHz at 1.8V supply voltage, respectively. I. INTRODUCTION When the operating frequency of an SOC chip increases, the key design of high-speed digital system is focus on restraining clock skew and jitter. The phase Locked Loops (PLL) and delay Locked Loops (DLL) are commonly used in microprocessors, memory interfaces and communication ICs, etc, as on-chip clock generators. Both of PLL and DLL can only lock the frequency and the phase of input/output signals [1]-[5]. In practical application, duty cycle ratio is one of the important specifications. A pulse width control loop (PWCL) is developed to correct the output signal duty. Ideally, a PWCL circuitry can correct any duty cycle of the input signal to 50% duty cycle in output. Conventional PWCL [6] circuit structure depends on reference frequency of an oscillator. When the oscillator experiences process variation or an improper inverter aspect ratio, an improper reference voltage is produced, leading to a possibly unstable operation. The mutualcorrelated PWCL (MC-PWCL) [7] uses the complementary phases of signals to generate two bias voltages. The two
inputs of the charge pump circuits are complementary signals phase shifted by 180°. This scheme improves the stability of the conventional PWCL, reduces the voltage ripple of the transconductor output and no reference frequency is affected by process variation. Acombined charge pump and miller scheme is applied to improve the performance of MC-PWCL [7]. The design still has limitations in the input duty range, minimum supply voltage, stability and operating frequency. II. CIRCUIT STRUCTURE Fig. 1 shows the circuit structure of 1-99% input duty 50% output duty cycle corrector. The control input stage is similar to a pseudo NMOS logic. The feedback control voltage Vctrl is generated from the OTA to modulate the duty cycle of the input signal. The buffer chains are mutualcorrected structure to generate complementary signals. The phase blending scheme can ensure the signals to have 180° phase shift. The combined charge pump structure [8] can decrease the voltage ripple and generate accurate output signal. The sub-circuits are described as following. A. Combined Charge Pump Fig. 2 plots the combined charge pump. The ratio of current source and current sink is 1:1 to obtain 50% output duty. To maintain constant current source/sink without being affected by short channel modulation, the complementary signals Ckout+ and Ckout- are applied. Either the left side or the right side of the switches is turned on to charge or discharge Vc+ and Vc-. Current I always has one turn-on path [9], thus stabilizing the voltage of nodes A and B. So the nodes A and B can be kept nearly constant leading to constant current/sink. B. Differential Second-order Low-pass Filter
Fig. 1. 1 ~99% input duty 50% output duty cycle corrector.
stable operation when receiving extremely small and large input duty cycle. The differential second-order filter with miller scheme shown in Fig. 3(c) obtains the smallest ripple voltage at the output of the OTA.
Fig. 2. Combined charge pump.
(a)
Fig. 4. Comparisons of stability versus low-pass filters. C. Output Tranconductance Amplifier
(b)
(c) Fig. 3. (a) First-order miller scheme; (b) second-order miller scheme; (c) second-order miller scheme. The structure of the low-pass filter is related to the stability of a PWCL. The traditional first-order low pass filter with miller scheme is shown in Fig. 3(a). Fig. 3(b) plots the second–order low pass filter with miller scheme. Vc+ and Vc- are charged and discharged simultaneously. The gain of Vc+ to Vc- is -1. According to miller theorem, C2 has an equivalent size of its original value. It reduces 75% of total capacitance area compared to the scheme without miller scheme [8]. To enhance the stability, a differential second-order low pass filter shown in Fig. 3(c) is applied. Two bypass capacitors C1 are added to reduce the voltage ripples induced by the charging and discharging currents at Vc+ and Vc-. The second-order low pass filter creates additional pole and zero. The optimal stability can be obtained to decrease the lock-in time. Fig. 4 plots the simulations of Fig. 3(a)-(c). The input frequency is 100MHz with 99% duty cycle. Fig. 3(a) shows that the first-order filter has an unstable result. Fig. 3(b)-(c) demonstrates that the second-order filter still maintains
The stability of a PWCL is proportional to the bandwidth of the OTA and inverse proportional to its dc gain [6]. Fig. 5 demonstrates that the lock-in time for 60-dB and 30-dB OTA gain are 14-us and 7-us, respectively. As the gain is decreased, the error voltage between Vc+ and Vc- is increased leading to a larger voltage ripple at Vctr and larger jitter at Ckout+ and Ckout-. There is an intrinsic trade-off problem between the lock-in time and output jitter. The OTA bandwidth should be as large as possible for high frequency application. The requirement of minimum OTA gain is to maintain acceptable jitter at Ckout+ and Ckoutwhen the PWCL is stabilized.
Fig. 5. Simulations of PWCL versus open loop gain. The OTA compares Vc+ and Vc- and generates output current iout=gm(Vc+-Vc-). According the operation of buffer chain and combined charge pump, Vc+ and Vc- are charged and discharged differentially initiated from an arbitrarily initial condition between GND and VDD. Applying a rail-to-
rail OTA can improve the charging and discharging of Vctr from an arbitrarily initial condition. A rail-to-rail OTA with folded cascode structure has current sources/sinks and output cascode devices. It has a larger minimum supply voltage, larger output resistance and lower bandwidth. Moreover, the minor poles induced by the internal nodes have an effect on the phase shift at higher frequency. Using a single-stage OTA in the PWCL achieves the best stability because it generates only 90 degree of phase shift from a single pole. The single-stage OTA with PMOS or NMOS input pair shown in Fig. 6(a)-(b) has limited input common-mode range (ICMR) which fails to function at the initial condition mentioned above. The simplified complementary OTA shown in Fig.6(c) is applied to obtain rail-to-rail ICMR and output swing. Since a constant gm is not necessary for the PWCL application, the current sources of the OTA are omitted to operate at a minimum supply voltage. Fig. 7 plots the frequency response simulation of the OTAs shown Fig. 6(a)-(c). The three OTAs have equal dc gain. With the parallelism of circuit structure, the complementary OTA has twice of the transconductance and half of the output resistance, leading to twice of the bandwidth at an equal output load. The OTA devices can operate at saturation region at a minimum supply voltage of 0.6V. The constant transconductance (gm) technique is not required for the application in PWCL. The simplified complementary OTA provides satisfied specifications for high stability, high input duty range and wide bandwidth PWCL application.
III. SPICE SIMULATIONS AND COMPARISONS. The 0.18-µm CMOS device models are used for SPICE simulations. The OTA gain is 42dB. The charge pump current is 15uA. Fig. 8(a) and (b) plot the waveforms of 1% and 99% duty cycle of an 800-MHz input signal, respectively. It demonstrates stable operation to obtain 50% output duty cycle.
Fig. 7. OTAs Frequency response.
(a)
(a)
(b)
(b) Fig. 8. Simulations of (a) 1% and (b) 99% input duty cycle 50% output duty cycle at 800-MHz. (c) Fig. 6. (a) PMOS input OP; (b) NMOS input OP and (c) complementary OTA.
Table I lists the summary of input range on various frequencies. The maximum operating frequency to receive 1~99% input duty and generate 50% output duty cycle is 800MHz. Fig. 9 plots maximum operating frequency to
obtain 1~99% input duty and 50% output duty versus minimum supply voltage. The result demonstrates the minimum supply voltage to maintain 800-MHz operation is 1.2V. The circuit still functions to obtain 1~99% input duty 50% output duty at 0.4V. The input duty range is reduced for frequency lower than 30-MHz and higher than 800MHz. Table II lists the summary of the comparisons. This work extends the input duty range to 1~99%. The circuit also has a wider operating frequency range than the others. The power consumption is comparable to the prior work. TABLE I Summary of Input frequency and input duty range. Input Frequency
Input duty range (%), VDD=1.8V 20~80%
2-GHz 1-GHz
20~80%
800-MHz
1~99%
500-MHz
1~99%
200-MHz
1~99%
100-MHz
1~99%
50-MHz
1~99%
30-MHz
1~99%
TABLE II Comparisons of the 50% duty cycle correctors.. Spec. Comparison Process Supply Voltage Ckin (Duty Cycle Range) Charge Pump
Max. Operating Frequency (MHz) Min. Operating Frequency (MHz) Power Consumption
Low Voltage [10] 0.35um CMOS 1.8V Fixed at 50%
Mutual Correlated [7] 0.35um CMOS 3.3V 20%~75%
This Work
0.18um CMOS 1.8V 1%~99%
Push-pull Conventional Combined Charge Pump Charge Charge Pump Pump 800
900
2600
400
300
20
-
2.45mW
2.47mW
REFERENCES
1~99% Duty Input, 50% Duty Output 1000 800 Max. 600 Operation Freq. 400 (MHz) 200 0 1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Power Supply (V)
Fig. 9. Supply voltage versus maximum operating frequency to obtain 1-99% input duty 50% output duty.
IV. SUMMARY A 50% duty cycle corrector is designed and analyzed. The complementary signals with 180° phase shift are generated. A combined charge pump keeps constant current source and sink during operation which increases the accuracy. A differential second-order low-pass filter with miller scheme improves the stability and reduces the lock-in time. A simplified low-voltage rail-to-rail OTA is realized to minimize the supply voltage. The 50% duty cycle corrector has a minimum supply voltage of 1.2V to receive 1~99% input duty signal at 800-MHz. The minimum and maximum operating frequencies to obtain 50% output duty are 20-MHz and 2.6-GHz, respectively.
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