1992 Abstracts - CiteSeerX

ICCAD92, Pages 4-8

Configuring Multiple Scan Chains for Minimum Test Time Sridhar Narayanan, Rajesh Gupta+ and Melvin Breuer Dept. of Electrical Engg.-Systems University of Southern California Los Angeles, CA +IBM East Fishkill Zip 3A1/306, Route 52 Hopewell Jct., NY Abstract To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper we consider the problem of optimally constructing multiple scan chains so as to minimize overall test time. Rather than follow the traditional practice of using equal length chains, we allow the chains to be of different lengths, and show that this can lead to lower test times. The main idea in our approach is to assign those scan elements that are more frequently accessed to shorter scan chains. Given a design with N scan elements, and given that k scan chains are to be used for applying tests, we present an algorithm of complexity 0(kN2) for configuring the chains such that the overall test application time is minimized. By analyzing a range of circuit topologies, we demonstrate test time reductions as large as 40% over equal length chain configurations. References [1] K.-T. Cheng and V.D. Agrawal. A partial scan method for sequential circuits with feedback. IEEE Trans. on Computers, 39(4):544-548, April 1990. [2] R. Gupta, R. Gupta, and M. A. Breuer. The BALLAST methodology for structured partial scan design. IEEE Trans. on Computers, 39(4):538-543, April 1990. [3] P.P. Fasang et al. Automated design for testability of semicustom integrated circuits. In Proc., Int'l Test Conf., pages 558-564, November 1985. [4] S. Bhawmik and P. Palchaudhuri. DFT Expert: Designing testable VLSI circuits. IEEE Design & Test, pages 819, October 1989. [5] S.P.Morley and R.A.Marlett. Selectable length partial scan: a method to reduce vector length. In Proc. Int'l Test Conf ., pages 385-392, November 1991. [6] R.Gupta. Advanced Serial Scan Design for Testability. Ph.D. thesis, Univ. of Southern California, Dept. of Electrical Engg., 1991. CEng. Technical Report 91-10. [7] M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. Computer Science Press, New York, N.Y., 1990. [8] S. Narayanan, R. Gupta, and M.A. Breuer. Optimal configuring of multiple scan chains. Accepted for publication in IEEE Trans. on Computers . [9] F. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. The MIT Press, Cambridge, Massachusetts, 1990.

ICCAD92, Pages 9-12

Overall Consideration of Scan Design and Test Generation Pao-Chuan Chen, Bin-Da Liu and Jhing-Fa Wang Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan 70101, R.O.C. Abstract Different from the previous approaches that enhance the abilities of the test generation algorithm, scan cell selection strategy and structure of scan chain individually, a complete system taking all these factors into account is developed. The goal of this research is to reduce the extra costs caused by the scan design, especially the test application time. Experimental results show that the overall consideration of scan design and test generation can speed up test generation and reduce great amount of test application time. References: [1] E. B. Eicheberger and T. W. Williams, "A logic design structure for LSI testability," in Proc. 14th Design Automation Conf., 1977, pp. 462-468. [2] T. H. Chen and M. Breuer, "Automatic design for testability via testability measures," IEEE Trans. ComputerAided Design, vol. CAD-4, pp. 3-11, Jan. 1985. [3] K. S. Kim and C. R. Kime, "Partial scan by use of empirical testability," in Proc. Int. Conf. on Computer-Aided Design, 1990, pp. 314-317. [4] E. Trischler, "Incomplete scan path with an automatic test generation methodology," in Proc. Int. Test Conf., 1980, pp. 153-162. [5] K. T. Cheng and V. D. Agrawal, "An economical scan design for sequential logic test generation," in Proc. 19th Int. Symp. on Fault-Tolerant Computing, 1989, pp. 28-35. [6] R. Gupta and M. A. Breuer, "BALLAST: A methodology for partial scan design," in Proc. 19th Int. Symp. on Fault-Tolerant Computing, 1989, pp. 118-125. [7] D. H. Lee and S. M. Reddy, "On determining scan flip-flops in partial scan design," in Proc. Int. Conf. on Computer-Aided Design, 1990, pp. 322-325. [8] V. Chickermane and J. H. Patel, "A fault oriented partial scan design approach", in Proc. Int. Conf, on Computer-Aided Design, 1991, pp. 400-403. [9] V. D. Agrawal, K. T. Cheng, D. D. Johnson and T. Lin, "A complete solution to the partial scan problem," in Proc. Int. Test Conf., 1987, pp. 44-51. [10] H. K. T. Ma, S. Devadas, A. R. Newton and A. Sangiovanni-Vincentelli, "An incomplete scan design approach to test generation for sequential machines," in Proc. Int. Test Conf., 1988, pp. 730-734. [11] P. C. Chen, J. F. Wang and B. D. Liu, "Gradually-on structure for scan design,", Electronic Letters, Vol. 28, pp. 868-869, Apr. 1992. [12] P. Goel and B. C. Rosales, "PODEM-X: An automatic test generation system for VLSI logic structures," in Proc. 18th Design Automation Conf., 1981, pp.260-268. [13] P. Goel, "An implicit enumeration algorithm to generate tests for combination logic circuits," IEEE Trans. Comput., Vol.c-30, pp.215-222, Mar. 1981. [14] T., Kelsey and K. Saluja, "Fast test generation for sequential circuits," in Proc. Int. Conf. on Compute-rAided Design, 1989, pp. 354-357.

ICCAD92, Pages 13-16

Configuration of a Boundary Scan Chain for Optimal Testing of Clusters of non Boundary Scan Devices Y. -H. Choi and T. Jung Department of Computer Science, University of Minnesota, Minneapolis, MN 55455 Abstract Testing of boards containing a mixture of boundary scan components and clusters of nonboundary scan devices is an interesting problem. If a tester cannot contact the non-scan circuitry, the inputs and outputs of onboard boundary scan devices may be used as virtual tester pins. In this case, the time for testing the clusters depends on how the boundary scan chips are connected into a longer scan chain. This paper presents a technique for configuring a chain of boundary scan chips to minimize the test time for clusters. References [1] R.G. Bennetts, A. Osseyran, "IEEE Standard 1149.1-1990 on boundary scan: History, literature survey, and current status," Jour. Electronic Testing: Theory and Applications, 2. pp. 11 -25, 1991. [2] R.P. Van Riessen, H.G. Kerhoff, A. Kloppenburg, “Designing and implementing an architecture with boundary scan," IEEE Design & Test of Computers, pp. 9-25, Feb. 1990. [3] P. Hansen, '"Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels", Int. Test Conf., pp. 166-171, 1989. [4] M.F. Lefebvre, '"Test generation: A boundary scan implementation for module interconnect testing", Int. Test Conf., pp. 88-95, 1991. [5] J.-C. Lien, M.A. Breuer, "An optimal scheduling for testing interconnect using boundary scan", Jour. Electronic Testing: Theory and Applications, 2, pp. 117-130,1991.


An Algorithm to Reduce Test Application Time in Full Scan Designs Soo Y. Lee and Kewal K. Saluja Department of Electrical and Computer Engineering, University of Wisconsin – Madison, Madison, WI 53706 Abstract Full scan design technique alleviates the test generation problem for sequential circuits. However scan operations increase the number of test clocks substantially. This paper presents an algorithm to generate a test with fewer test clocks for full scan designs by using combinational and sequential test generation algorithms adaptively. Heuristics combining test measures and scan strategies are introduced. The algorithm, Test Application time Reduction for Full scan designs (TARF), is implemented and tested on a set of ISCAS sequential benchmark circuits. The results show that TARF achieves same test coverage as combinational test generators but with fewer test clocks. References [1] R. Gupta and M. A. Breuer, "Ordering storage elements in a single scan chain," Proc. Intl. Conf. on ComputerAided Design, pp. 408-411, 1991. [2] S. P. Morley and R. A. Marlett, "Selectable length partial scan: A method to reduce vector length," Proc. Intl. Test Conf., pp. 385-392, 1991. [3] T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, "Test compaction for sequential circuits," IEEE Trans. on Computer-Aided Design, vol. 11, no. 2, pp. 260-267, February 1992. [4] A. A. Diwan, "An algorithm for minimizing the number of test cycles," Proc. 4th Intl. Symp. on VLSI Design, pp. 154-156, January 1991. [5] P. Goel and B. C. Rosales, "Test generation & dynamic compaction of tests," Proc. Int. Test Conf., pp. 189192,1979. [6] M. Abramovici, J. J. Kulikowski, P. R. Menon, and D. T. Miller, "SMART and FAST: Test generation for VLSI scan design circuits," IEEE Design and Test of Comp., pp. 43-54, August 1986. [7] I. Pomeranz, L. N. Reddy, and S. M. Reddy, "COMPACTEST: A method to generate compact test sets for combinational circuits," Proc. Intl. Test Conf., pp. 194-203, 1991. [8] D. K. Pradhan and J. Saxena, "A design for testability scheme to reduce test application time," Proceedings VLSI Test Conference, pp. 55-60, April 1992. [9] F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," Proc. Intl. Symp. on Circuits and Systems, pp. 1929-1934, May 1989. [10] T. P. Kelsey, K. K. Saluja, and S. Y. Lee, "An efficient algorithm for sequential circuit test generation," Submitted to IEEE Trans. on Comp. [11] L. H. Goldstein and E. L. Thigpen, "Scoap: Sandia controllability / observability analysis program," Proc. 17th Design Automation Conf., pp. 190-196, June 1980.


New Channel Segmentation Model and Associated Routing Algorithm for High Performance FPGAs Surendra Burman, Chandar Kamalanathan, and Naveed Sherwani Department of Computer Science, Western Michigan University, Kalamazoo, MI 49008 Abstract A new channel segmentation model for high performance FPGAs is presented. In this model, a channel is partitioned into several regions and each region consists of tracks of equal length segments, but segment length is varied uniformly across the regions. Each region is allocated certain number of tracks, however the segments are not arranged in an uniform manner but in a staggered fashion. In order to make optimum use of the new model, we have also developed a routing algorithm. The key feature of our routing algorithm is the assignments of the nets to the appropriate tracks by delay computation and delay matching techniques. Experimental results show that, our model and the algorithm improve the longest net delay by as much as 75.16% and the average net delay by 48.28% as compared to the conventional uniformly segmented model. References [1] ACT Family Field Programmable Gate Array DATABOOK. [2] Surendra Burman, Chandar Kamalanathan. and Naveed Sherwani. "New Channel Segmentation and Associated Routing Algorithm for High Performance FPGAs". The Technical Report TR92/18. [3] A. El Gamal, et. al.. "An Architecture for Electrically Configurable Gate Arrays". IEEE JSSC. Vol. 24. No. 2. April 1989. pp. 394-398. [4] A. Hashimoto and J. Stevens, "Wire Routing by Optimizing Channel Assignment within Large Apertures." The Proc. of 8th ACM/IEEE Design Automation Conference pp. 155-169. 1971. [5] H. Hsieh, et. al. "A 9000-Gate User-Programmable Gate Array." Proceedings of 1988 CICC. May 1988. pp. 15.3.1-15.3.7. [6] J. Greene, V. Roychowdhury. S. Kaptanoglu and A. El. Gamal. "Segmented Channel Routing." Proceedings of Design Automation Conference, June 1990. pp. 567 - 572. [7] Ren-Song Tsay. "Exact Zero Skew". Proceedings of the ICCAD-91. pp. 336-339. 1991. [8] Stephen Brown. Jonathan Rose and Zvonko G. Vranesic. "A Detailed Router for Field-Programmable Gate Arrays", the IEEE Transactions on Computer Aided Design". Vol. II. pp. 620-628. May 1992.


On Channel Segmentation Design for Row-Based FPGAs Kai Zhu and D.F. Wong Department of Computer Sciences, University of Texas at Austin, Austin, Texas Abstract The channel segmentation design problem for row-based FPGAs is to design a segmented channel to maximize the probability of successful routing. In this paper, we present an algorithm which takes an arbitrary net distribution and an integer K (specifying the maximum number of segments allowed in routing a net) as inputs, and automatically generates a segmented channel which is most suitable for K-segment channel routing. Our algorithm was tested extensively over various net distributions. We also present a new algorithm for segmented channel routing based on reducing the problem to the maximum independent set problem for undirected graphs. References [1] Actel Corp., "ACT Family FPGA Databook", 1991. [2] R. Boppana and M.M. Halldorsson, "Approximating Maximum Independent Sets by Excluding Subgraphs", BIT 32(1992), pp. 180-196. [3] A.E. Gamal, et al., "Segmented Channel Routing Is Nearly as Efficient as Channel Routing (and Just as Hard)", in Advanced Research in VLSI, UC Santa Cruz, 1991, pp. 193-211. [4] A. E. Gamal, et. al., "An Architecture for Electrically Configurable Gate Arrays", IEEE Journal of Solid-State Circuits, vol. 24, no.2, pp. 394-398, 1989. [5] J. Greene, et al., "Segmented Channel Routing", DAC90, pp. 567-572. [6] D. Marple and L. Cooke, "An MPGA Compatible FPGA Architecture", First International ACM/SIGDA Workshop on FPGA, 1992,pp. 39-44. [7] Texas Instruments, FPGA Product Description, 1991. [8] K. Zhu and D.F. Wong, "On Channel Segmentation Design for Row-Based FPGA", manuscript, 1992.


VLSI Design Parsing Akhilesh Tyagi Department of Computer Science, University of North Carolina, Chapel Hill, NC 27599-3175 Abstract The term design-parsing refers to the process of parsing a flat netlist or logic description into a behaviorally equivalent flow-graph where the nodes correspond to higher-level primitives such as arithmetic functions and a prespecified set of functions. It us useful in verification, resynthesis and computer-aided design documentation. We present a spatial-entropy based dynamic signature that helps determine the boundaries and types of function blocks. References [1] D. T. Blaauw, D. G. Saab, R. B. Mueller-Thuns, J. A. Abraham, and J. T. Rahmeh. Automatic Generation of Behavioral Models from Switch-Level Descriptions. In Proc. 26th DAC, pages 179-184. 1989. [2] R.P. Brent and H.T. Kung. A Regular Layout for Parallel Adders. IEEE Trans. Computers, pages 260-264, March 1982. [3] J. L. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan-Kaufmann, 1990. [4] G. Kedem, F. Brglez and K. Kozminski. OASIS: A Silicon Compiler for Semicustom Design. In Proc. ISCAS, 1990. [5] A. P. Kostelijk. VERA, A Rule-Based Assistant for VLSI Circuit Design. In VLSI89, pages 89-98. 1989. [6] L.I.S. VLSI Design Tools Reference Manual. Technical Report 87-02-01, NWLIS, University of Washington, Seattle, 1987. [7] C. Mead and L. Conway. Introduction to VLSI Systems. Addison-Wesley, 1980. [8] J. Y. Murzin. FAON, A Functional Abstractor of Netlist. In Seminaire de Programmation Logique, Lannion, May 1986. [9] M. Ohmura, H. Yasuura, and K. Tamaru. Extraction of Functional Information from Combinational Circuits. In Proc. ICCAD, pages 176-179. 1990. [10] A. Rajanala and A. Tyagi. An Area Estimation Technique for Module Generation. In Proc. ICCD. 1990. [11] S. Rajgopal and A. Tyagi. On Probabilistic Switch-Level Simulation for Asynchronous Circuits. In Proc. EDAC, pages 339-343. February 1991. [12] S. Rajgopal and A. Tyagi. Dynamic Distance based BDD Ordering. In Proc. SASIMI '92, pages 54-63. Daichisha Press, Kyoto, April 1992. [13] C. J. Terman. Simulation Tools for Digital LSI Design. PhD thesis, Dept. EE, MIT, Cambridge, MA, 1983. [14] A. Tyagi. An Algebraic Model for Datapath Design Space Exploration. In Proc. ACM Intl Workshop on Formal Methods in VLSI Design, January 1991. available as Dept Computer Science, UNC, Chapel Hill, TR90-009. [15] A. Tyagi. How Many Critical Paths Classify a Function? A Study in Design Space Extraction. In Proc. ISCAS. June 1991. [16] A. Tyagi. A Module Generator Development Environment: Area Estimation and Design-Space Exploration Encapsulation. to appear In Proc. 6th Intl. Conf. on VLSI Design, January 1993. [17] J.D. Ullman. Computational Aspects of VLSI. Computer Science Press. 1984. [18] A.C. Yao. Some Complexity Questions Related to Distributed Computing. In Proc. ACM STOC, pages 209213, 1979.


Aesthetic Routing for Transistor Schematics Tsung D. Lee and Lawrence P. McNamee Computer Science Department, University of California, Los Angeles, Los Angeles, California Abstract A new heuristic routing approach is presented for generating transistor schematic diagrams. The method consists of two steps: global routing and channel routing. The global routing step partitions and routes the interconnections into three levels of abstraction with domain knowledge. It forms desirable intra-block routing styles and local connection patterns, and achieves a reduction of net bends and lengths. Channel routing minimizes net crossovers by applying decycling and ordering techniques achieving non-overpapping routing with a small number of net crossovers. References [1] M. Burstein and R. Pelavin, "Hierarchical Wire Routing," IEEE Trans. on Computer-aided Design, CAD-2, pp. 223-234, 1983 [2] M. Garey and D. Johnson, Computers and Intractability, Bell Telephone Lab., Inc., 1979 [3] D. Heinbuch, CMOS3 Cell Library, AddisonWesley Publishing Co., 1988 [4] A. Kahng, G. Robins, "Iterative Steiner Tree Routing," the Proc. of ICCAD, Nov. 1990 [5] T.D. Lee and L.P. McNamee, "A Transistor Schematic Placement Expert," the Proc. of Ini'l Conf. of Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, June 1991 [6] H. Levy, and D. Low, "A New Algorithm for Finding Small Cycle Cutsets," IBM Tech. Rep. IBM-G320-2721, June 1983 [7] H. Weinblatt, "A New Search Algorithm for Finding the Simple Cycles of a Finite Directed Graph," J. ACM, vol. 19, no. 1, pp.43-56, Jan. 1972


A Tutorial on Logic Synthesis for Lookup-Table Based FPGAs Robert J. Francis Department of Electrical Engineering, University of Toronto Abstract The ability to shorten development cycles has made Field-Programmable Gate Arrays (FPGAs) an attractive alternative to Standard Cells and Mask Programmed Gate Arrays for the realization of ASICs. One important class of FPGAs are those that use lookup tables (LUTs) to implement combinational logic. The ability of a K-input L UT to implement any Boolean function of K variables differentiates the synthesis of L UT circuits from synthesis for conventional ASIC technologies. The major difference occurs during the technology mapping phase. of logic synthesis. For values of K greater than 3, the large number of functions that can be implemented by a K-input L UT makes it impractical to use conventional library-based technology mapping. However, the completeness of the set of functions that can be implemented by a L UT eliminates the need for a library of separate functions. In addition, this completeness can be leveraged to optimize the final circuit. References [1] S. D. Brown, R. J. Francis, J. Rose, Z. G. Vranesic, Field-Programmable gate Arrays, Kluwer Acedemic Publishers, 1992. [2] R. K. Brayton, G. D. Hachtel, A. Sangiovanni-Vincentelli, "Multilevel Logic Synthesis," Proc. of IEEE, Vol. 78, No. 2, Feb. 1990, pp. 264-300. [3] K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching," Proc. 24th DAC, June 1987, pp. 341-347. [4] S. Trimberger, "A Small Complete Mapping LIbrary for Lookup-Table-Based FPGAs," 2nd Intl. Workshop on Field-Programmable Logic and Applications, Aug. 1992. [5] U . Schlichtmann, F. Brglez, M. Hermann, "Characterization of Boolean functions for Rapid Matching in EPGA Technolgy Mapping," Proc, 29th DAC, June 1992, pp. 374-379. [6] R. J. Francis, J. Rose, K. Chung, "Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays," Proc. 27th DAC, June 1990, pp. 613-619. [7] R. Murgai, Y, Nishizaki, N. Shenay, R. K. Brayton, A. Sangiovanni-Vincentelli, "Logic Synthesis for Programmable Gate Arrays," Proc. 27th DAC, June 1990, pp. 620-625. [8] P. Abouzeid, L. Bouchet, K. Sakouti, G. Saucier, P. Sicard, "Lexicographical Expression of Boolean Function for Multilevel Synthesis of high Speed Circuits," Proc. SASHIMI 90, Oct. 1990, pp. 31-39. [9] D. Filo, J. C. Yang, F. Mailhot, G. De Micheli, "Technology Mapping for a Two-Output RAM-based field Programmable Gate Array," Proc. EDAC, Feb. 1991, pp. 534-538. [10] R. J. Francis, J. Rose, Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs," Proc. 28th DAC, June 1991 pp. 227-233. [11] K. Karplus, "Xmap: a Technology Mapper for Table-lookup Field-Programmable Gate Arrays," Proc, 28th DAC, June 1991, pp. 240-243.

[12] N. Woo, "A Heuristic Method for FPGA Technology Mapping Based on Edge Visibility." Proc. 28th DAC, June 1991. pp. 248-251. [13] R. Murgai, N. Shenoy, R.K. Brayton, A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proc. ICCAD, Nov. 1991, pp. 564-567. [14] R. J. Francis, J, Rose, Z. Vranesic, "Technology Mapping of Lookup Table-Based FPGAs for Performance," Proc. ICCAD, Nov. 1991. pp. 568-571.

[15R. Murgai, N. Shenoy, R.K. Brayton, "Performance Directed Synthesis for Table Look Up Programmable," Gate Arrays, Proc. ICCAD, Nov. 1991 pp. 572-575 [16] K. C. Chen, "Logic Minimization of Lookup-Table Based FPGAs," 1st Intl Workshop on FPGAs, Feb. 1992, pp. 71-76.

[17] P. Sawkar, D. Thomas "Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays," Proc, 29th DAC, June 1992, pp. 368-373. [18] J. Cong, T. Ding, A. Kahng, P. Trajmar "Graph Based FPGA Technology Mapping for Delay Optimization," Proc. ICCD, Oct. 1992. [19] E. J. McClusky, Logic Design Principles, Prentice Hall, 1986. [20] C. E. Shannon, "The Synthesis of Two-Terminal Switching Circuits," Bell Syst. Tech. Journal, Vol. 28, 1949, pp. 5998. [21] M. R. Garey, D. S. Johnson, Computers and Intractability, A Guide to the Theory of NP-Completeness, W. H. Freeman and Co., 1979. [22] R. J. Francis, Technology Mapping for Lookup Table-Based FPGAs, Ph.D. Thesis in preparation, University of Toronto, Department of Electrical Engineering.


An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs Jason Cong and Yuzheng Ding Department of Computer Science, University of California, Los Angeles, CA 90024 Abstract In this paper we present a polynomial time technology mapping algorithm, called Flow-Map, that optimally solves the LUT based FPGA technology mapping problem for depth minimization for general Boolean networks. This theoretical breakthrough makes a sharp contrast with the fact that conventional technology mapping problem in library-based designs is NP-hard. A key step in Flow-Map is to compute a minimum height K feasible cut in a network, solved by network flow computation. Our algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several postprocessing operations. We tested the Flow-Map algorithm on a set of benchmarks and achieved reductions on both the network depth and the number of LUTs in mapping solutions as compared with previous algorithms. References [1] Hill, D., "A CAD System for the Design of Field Programmable Gate Arrays," Proc. ACM/IEEE Design Automation Conference, pp.187-192, 1991. [2] Xilinx, The Programmable Gate Array Data Book, Xilinx, San Jose (1989). [3] Francis, R. J., J. Rose, and Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs," Proceedings 28th ACM/IEEE Design Automation Conference, pp. 613-619,1991. [4] Karplus, K., "Xmap: A Technology Mapper for Tablelookup Field-Programmable Gate Arrays," Proc. 28th ACM/IEEE Design Automation Conference, pp. 240-243, 1991. [5] Murgai, R., et al, "Logic Synthesis Algorithms for Programmable Gate Arrays," Proc. 27th ACMIIEEE Design Automation Conf., pp. 620-625,1990. [6] Murgai, R., N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proc. Int'l Conf. Computer-Aided Design, pp. 564-567, Nov., 1991. [7] Sawkar, P. and D. Thomas, "Technology Mapping for Table-Look-Up Based Field Programmable Gate Arrays," ACM/SIGDA Workshop on Field Programmable Gate Arrays, pp. 83-88, Feb. 1992. [8] Woo, N.-S., "A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility," Proc. 28th ACM/IEEE Design Automation Conference, pp. 248-251, 1991. [9] Chen, K. C., J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar, "DAG-Map: Graph-based FPGA Technology Mapping for Delay Optimization," IEEE Design and Test of Computers, Sep.1992. [10] Francis, R. J., J. Rose, and Z. Vranesic, "Technology Mapping of Lookup Table-Based FPGAs for Performance," Proc. Int'l Conf. Computer-Aided Design, pp. 568-571, Nov., 1991. [11] Murgai, R., N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Performance Directed Synthesis for Table Look Up Programmable Gate Arrays," Proc. Int'l Conf. Computer-Aided Design, pp. 572-575, Nov., 1991. [12] Bhat, N. and D. Hill, "Routable Technology Mapping for FPGAs," First Int'l ACM/SIGDA Workshop on Field Programmable Gate Arrays, pp. 143-148, Feb. 1992. [13] Schlag, M., J. Kong, and P. K. Chan, "Routability-Driven Technology Mapping for Lookup Table-Based FPGAs," Proc. 1992 IEEE International Conference on Computer Design, Oct. 1992. [14] Detjens, E., G. Gannot, R. Rudell, A. SangiovanniVincentelli, and A. Wang, "Technology Mapping in MIS," Proc. IEEE Int'l Conf. on Computer-Aided Design, pp.116-119,1987. [15] Keutzer, K., "DAGON: Technology Binding and Local Optimization by DAG Matching," Proc. 24th ACM/IEEE Design Automation Conference, pp. 341-347,1987. [16] Francis, R. J., J. Rose, and Z. Vranesic, "Technology Mapping for Delay Optimization of Lookup Table-Based FPGAs," MCNC Logic Synthesis Workshop, 1991. [17] Roth, J. P. and R. M. Karp, "Minimization Over Boolean Graphs," IBM Journal of Research and Development, pp. 227-238, April 1962.

[18] Hoover, H. J., M. M. Klawe, and N. J. Pippenger, "Bounding Fan-out in Logic Networks," Journal of Association for Computing Machinery, Vol. 31, pp. 13-18, Jan. 1984. [19] Wang, A., "Algorithms for Multi-level Logic Optimization," U.C.Berkeley Memorandum No. UCB/ERL M89/50, April 1989. [20] Cong, J. and Y. Ding, "An Optimal Technology Mapping Algorithm fo Delay Optimization in Lookup-Table Based FPGA Designs," in UCLA Computer Science Department Technical Report CSD-920022, (May 1992). [21] Ford, L. R. and D. R. Fulkerson, Flows in Networks, Princeton Univ. Press, Princeton, N.J. (1962). [22] Schlag, M., P. Chan, and J. Kong, "Empirical Evaluation of Multilevel Logic Minimization Tools for a Field Programmable Gate Array Technology," Proc. 1st Int'l Workshop on Field Programmable Logic and Applications, Sept. 1991.


Rectification Method for Lookup-Table Type FPGA's Yuji Kukimoto Department of EECS. University of California. Berkeley, CA 94720 Masahiro Fujita Processor Laboratory, Fujitsu Laboratories Ltd., Kawasaki 211, Japan Abstract Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for look-up table type FPGA's. Instead of changing the netlist of a circuit, we only modify functionality realized by look-up tables and keep the netlist equal so that there will be no change on the delay of the circuit. We formalize the problem using characteristic functions and present a redesign method based on Boolean relation techniques. References [1] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of 27th ACM/IEEE Design Automation Conference, pages 40-45, June 1990. [2] R. K. Brayton and F. Somenzi. Boolean relations and the incompletely specification of logic networks. In Proceedings of International Conference on Very Large Scale Integration, pages 231-240, August 1989. [3] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C35(8):677-691, August 1986. [4] E. Cerny and M. A. Marin. An approach to unified methodology of combinational switching circuits. IEEE Transactions on Computers, C-26(8):745-756, August 1977. [5] J. Cong, A. Kahng, K.-C. Chen, and P. Trajmar. Graph based FPGA technology mapping for delay optimization. In Proceedings of ACM Workshop on Field-Programmable Gate Arrays, February 1992. [6] M. Damiani and G. De Micheli. Recurrence equations and the optimization of synchronous logic circuits. In Proceedings of 29th ACM/IEEE Design Automation Conference, pages 556-561, June 1992. [7] M. Damiani and G. De Micheli. Synthesis and optimization of synchronous logic circuits from recurrence equations. In Proceedings of the European Conference on Design Automation (EDAC92), pages 226-231, March 1992. [8] D. Filo, J. C.-Y. Yang, F. Mailhot, and G. De Micheli. Technology mapping for a two-output RAM-based field programmable gate array. In Proceedings of European Conference on Design Automation, pages 534-538, February 1991. [9] R. Francis, J. Rose, and Z. Vranesic. Chortle-crf: Fast technology mapping for lookup table-based FPGAs. In Proceedings of 28th ACM/IEEE Design Automation Conference, pages 227-233, June 1991. [10] R. J. Francis, J. Rose, and K. Chung. Chortle: A technology mapping program for lookup table-based field programmable gate arrays. In Proceedings of 27th ACM/IEEE Design Automation Conference, pages 613-619, June 1990. [11] R. J. Francis, J. Rose, and Z. Vranesic. Technology mapping of lookup table-based FPGAs for performance. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 568-571, November 1991. [12] M. Fujita, T. Kakuda, and Y. Matsunaga. Redesign and automatic error correction of combinational circuits. In Proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, pages 253-262. North Holland, May 1990. [13] M. Fujita and Y. Matsunaga. Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 560-563, November 1991. [14] M. Fujita, Y. Tamiya, Y. Kukimoto, and K.C. Chen. Application of boolean unification to combinational logic synthesis. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 510-513, November 1991.

[15] L. Guerra and Y. Watanabe. Local transformations on multi-output nodes using boolean relations. EE290ls project report, UC Berkeley, May 1992. [16] K. Karplus. Xmap: a technology mapper for table-lookup field-programmable gate arrays. In Proceedings of 28th ACM/IEEE Design Automation Conference, pages 240-243, June 1991. [17] Y. Kukimoto and M. Fujita. Reduction of critical path delay by optimizing boolean relations. In Proceedings of ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems: Tau92, March 1992. [18] R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. Logic synthesis for programmable gate arrays. In Proceedings of 27th ACM/IEEE Design Automation Conference, pages 620-625, June 1990. [19] R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. Improved logic synthesis algorithms for table look up architectures. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 564-567, November 1991. [20] R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. Performance directed synthesis for table look up programmable gate arrays. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 572-575, November 1991. [21] H. Savoj and R. K. Brayton. Observability relations and observability don't cares. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 518-521, November 1991. [22] F. Somenzi and R. K. Brayton. An exact minimizer for boolean relations. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 316-319, November 1989. [23] Y. Watanabe and R. K. Brayton. Heuristic minimization of boolean relations. In Proceedings of MCNC International Workshop on Logic Synthesis, May 1991. [24] Y. Watanabe and R. K. Brayton. Incremental synthesis for engineering changes. In Proceedings of MCNC International Conference on Logic Synthesis, May 1991. [25] N.-S. Woo. A heuristic method for FPGA technology mapping based on the edge visibility. In Proceedings of 28th ACM/IEEE Design Automation Conference, pages 248-251, June 1991.


AWE Macromodels of VLSI Interconnect for Circuit Simulation Seok-Yoon Kim, Nanda Gopal, and Lawrence T. Pillage Computer Engineering Research Center, The University of Texas at Austin, Austin, Texas Abstract Asymptotic Waveform Evaluation (AWE) has been successfully applied to the evaluation of linear(ized) models of digital system interconnect. What remains is to interface AWE models with the nonlinear models of drivers and terminations that must be taken into account in order to obtain accurate timing information of the overall circuit/system. This paper describes an approach for obtaining time-domain macromodels of linear RLC interconnect that can be easily integrated into any circuit simulator. Based on generalized n-port descriptors, the technique can also be utilized to efficiently synthesize accurate driving-point models that reflect the loading characteristics of complex interconnect systems. References [1] D. F. Anastasakis, N. Gopal, S. Y. Kim, and L. T. Pillage. On the stability of approximations in Asymptotic Waveform Evaluation. In Proc. 29th ACM/IEEE Des. Auto. Conf., Jun 1992. [2] Desoer and E. Kuh. Basic Curcuit Theory. McGraw-Hill, 1969. [3] C. T. Dikmen et al. Piecewise linear Asymptotic Waveform Evaluation for transient simulation of electronic circuits. In Proc. IEEE Int'l. Symp. Ckt. Sys., Jun 1991. [4] N. Gopal, E. Tuncer, D. P. Neikirk, and L. T. Pillage. Evaluation of high-performance interconnect using lumped models. IEEE Trans. Ckt. Sys. (submitted). [5] X. Huang. Pade approximation of linear(ized) circuit responses. PhD thesis, Carnegie Mellon Univ., Nov 1990. [6] T. Kailath. Linear Systems. Prentice-Hall, Inc., 1980. [7] S. Kumashiro, R. Rohrer, and A. Strojwas. A new efficient method for the transient simulation of 3D interconnect structures. In IEDM Tech. Dig., 1990. [8] L. W. Nagel. Spice2, a computer program to simulate semiconductor circuits. Technical Report TR-ERL-M520, UC-Berkeley, May 1975. [9] L. T. Pillage and R. A. Rohrer. Asymptotic Waveform Evaluation for timing analysis. IEEE Trans. ComputerAided Des., 9, 1990. [10] PSPICE USERS' MANUAL. Version 4.03. Microsim Corp., Jan 1990. [11] V. Raghavan and R. A. Rohrer. AWESpice: A general tool for the efficient and accurate simulation of interconnect problems. in Proc. 29th ACM/IEEE Des. Auto. Conf., Jun 1992. [12] C. L. Ratzlaff, N. Gopal, and L. T. Pillage. RICE: Rapid Interconnect Circuit Evaluator. In Proc. 28th ACM/IEEE Des. Auto. Con., Jun 1991. [13] T. K. Tang, M. S. Nakhla, and R. Griffith. Analysis of lossy multiconductor transmission lines using the Asymptotic Waveform Evaluation technique. IEEE Trans. Microwave Th. tech., 39(12) Dec 1991.


Extension of the Asymptotic Waveform Evaluation Technique with the Method of Characteristics J. E. Bracken Carnegie Mellon University Pittsburgh PA, 15213 V. Raghavan Performance Signal Integrity Pittsburgh PA, 15213 R. A. Rohrer Carnegie Mellon University Pittsburgh PA, 15213 Abstract Methods for simulating distributed elements-such as systems of coupled, lossy transmission lines-with the Asymptotic Waveform Evaluation (AWE) technique have been described in [2] , [13] . One problem with these methods is that they use complex exponentials to approximate pure delays in the time responses of transmission lines. The approximation can lead to spurious ringing in the simulation results. In this paper, we describe how this problem can be overcome within the context of a SPICE-based simulator. The generalized method of characteristics [4] is used to derive an equivalent circuit model for a system of coupled lines. This allows the pure delay to be factored out; AWE can then be used to approximate the characteristic admittance, as well as the propagation functions of the lines. The AWE approximation can be simulated efficiently within a modified version of SPICE. Examples are presented to demonstrate that this technique is both accurate, while being faster than other existing methods. References [1] M. M. Alaybeyi, J. E. Bracken, J. Y Lee, V Raghavan, R. J. Trihy and R. A. Rohrer. "Exploiting partitioning in asymptotic waveform evaluation (AWE)." Proc. IEEE Custom IC Conf. 1992. [2] J. E. Bracken, V Raghavan and R. A. Rohrer. "Simulating distributed elements with asymptotic waveform evaluation." Proc. IEEE Intl. Microwave Symp.1992. [3] F Y Chang. "Transient analysis of lossless coupled transmission lines in a nonhomogenous dielectric medium." IEEE Trans. Microwave Theory Tech. MTT 18:616-626, Sept., 1970. [4] F. Y Chang. "The generalized method of characteristics for waveform relaxation analysis of lossy coupled transmission lines." IEEE Trans. Microwave Theory Tech. MTT 37(12):2028-2038, Dec, 1989. [5] C. W. Ho, A. E. Ruehli and P A. Brennan. "The modified nodal approach to network analysis." IEEE Trans. Circuit Theory. CAS-22:504-509, June, 1975. [6] X. Huang, V Raghavan and R. A. Rohrer. "AWEsim: A program for the efficient analysis of linear(ized) circuits." Tech. Digest of the IEEE Intl. Conf. on Computer-Aided Design, pages 534-537. November, 1990. [7] X. Huang. Padé Approximation of Linear(ized) Circuit Responses. Ph.D. thesis, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, November, 1990. [8] J. S. Roychowdhury and D. 0. Pederson. "Efficient transient simulation of lossy interconnect." 28th ACM/IEEE Design Automation Conf. Proc., pages 740-745.1991. [9] S. Lin and E. S. Kuh. "Pade approximation applied to transient simulation of lossy coupled transmission lines." Proc. 1992 IEEE Multi-Chip Module Conf. March, 1992. [10] L. T. Pillage and R. A. Rohrer. "Asymptotic waveform evaluation for timing analysis." IEEE Trans. ComputerAided Design. 9(4):352-366, April, 1990. [11] T. L. Quarles. The SPICE3 Implementation Guide. Technical Report ERL-M89/44, UC-Berkeley, April, 1989. [12] V Raghavan and R. A. Rohrer. "AWESpice: A general tool for the efficient and accurate simulation of interconnect problems." 29th ACM/IEEE Design Automation Conf. Proc. 1992.

[13] T. K. Tang and M. S. Nakhla. "Analysis of high speed VLSI interconnects using the asymptotic waveform evaluation technique." IEEE Trans. Computer-Aided Design. 11(3):341-352, March, 1992.


Numerical Integration Algorithms and Asymptotic Waveform Evaluation (AWE) M. Murat Alaybeyi Carnegie Mellon University, Pittsburgh, PA 15213 John Y. Lee Performance Signal Integrity, Inc, Pittsburgh, PA 15213 Ronald A. Rohrer Carnegie Mellon University Pittsburgh, PA 15213 Abstract An intuitive relationship between numerical integration algorithms and AWE is established. A small number of data points generated during a brief fixed timestep numerical integration of linear(ized) circuits are used to form Sampled Waveform Integration, Correction and Extrapolation (SWICE) models. This method preserves the efficiency of the AWE technique, while increasing the accuracy and generality. The strengths of such an approach are illustrated from a theoretical view, as well as with practical examples. References [1] John Lee and Ronald A. Rohrer. AWESymbolic: Compiled Circuit Analysis using Asymptotic Waveform Evaluation. 29th ACM/ IEEE Design Automation Conference Proceedings. 1992. Submitted for publication. [2] C.T. Dikmen, M.M. Alaybeyi, S. Topcu, A. Atalar, E. Sezer, M.A. Tan, R.A. Rohrer. Piecewise Linear Asymptotic Waveform Evaluation for Transient Simulation of Electronic Circuits. Proceedings of the IEEE International Symposium on Circuits and Systems, pages 854-857. June, 1991. [3] Tak K. Tang and Michel Nakhla. Analysis of High Speed VLSI Interconnects Using The Asymptotic Waveform Evaluation Technique. IEEE Trans. Computer-Aided Design. Submitted for Publication,1991. [4] Michel Nakhla and Linchao Lu. Time-domain Analysis of Distributed Networks. Proceedings of the IEEE International Symposium on Circuits and Systems. May, 1991. [5] E. S. Kuh and R. A. Rohrer. The State-Variable Approach to Network Analysis. Proceedings of the IEEE. 53(7), July, 1965. [6] Lawrence T. Pillage and Ronald A. Rohrer. Asymptotic Waveform Evaluation for Timing Analysis. IEEE Trans. ComputerAided Design. 9(4):352-366, April, 1990. [7] S. Lin and E.S. Kuh. Pade Approximation Applied to Transient Simulation of Lossy Coupled Transmission Lines. Proceedings of the 1992 IEEE Multi-Chip Module Conference, pages 52-55.1992. [8] Jiri Vlach and Kishore Singhal. Electrical/Computer Science and Engineering Series Computer Methods for Circuit Analysis and Design. Van Nostrand Reinhold Company, 1983. [9] Vivek Raghavan and Ronald A. Rohrer. AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems. 29th ACM/IEEE Design Automation Conference Proceedings. 1992. Submitted for publication. [10] Xiaoli Huang. Pade Approximation of Linear(ized) Circuit Responses. PhD thesis, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, November, 1990. [11] Xiaoli Huang and Vivek Raghavan and Ronald A. Rohrer. AWEsim: A program for the efficient Analysis of Linear(ized) circuits. Technical Digest of the IEEE International Conference on Computer-Aided Design, pages 534-537. November, 1990.


Timing Distribution in VHDL Behavioral Models Ashish S. Gadagkar, James R. Armstrong Bradley Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA Abstract This paper describes a new CAD tool, TIMESPEC; developed for solving the timing distribution problem of allocating realistic delays to the internal primitives (RTL models) of a digital device by using the linear programming approach. The inconsistencies in the manufacturer's specifications are also detected and corrected. TIMESPEC enables the use of imbedded timing in behavioral VHDL models and thus the end-to-end delays for all the paths in the digital device are made available. An interface is provided with an X-windows based graphical tool, the Modeler's Assistant which allows enumeration of all the input-to-output paths in the device. Thus a CAD tool is made available to system or chip designers/modelers for building accurate and synthesizable VHDL models. References 1. B. Harding, "System Simulation Assures that Chips Play Together," Computer Design, 1989, Aug. l, pp.70-84. 2. P. D. Linderman, "Top-Down Design Synthesis Using VHDL," WESCON 1990, pp.382-383. 3. N. D. Dutt, T. Hadley, D. D. Gajski, "An Intermediate Representation for Behavioral Synthesis," 27th ACM/IEEE Design Automation Conference, 1990, pp14-19. 4. N. D. Dutt, D. D. Gajski, "Designer Controlled Behavioral Synthesis," 26th ACM/IEEE Design Automation Conference, 1989, pp.754-757. 5. J. R. Armstrong, "Chip Level Modeling with VHDL," Prentice Hall, New Jersey, 1989. 6. B. Singh, "A Parametrized CAD tool for VHDL Model Development with X-Windows," Masters Thesis, Virginia Polytechnic Institute and State University, 1990. 7. S. K. Sherman, "Algorithms for Timing Requirement Analysis and Generation," 25th ACM/IEEE Design Automation Conference, 1988, pp.724-727. 8. H. P. Williams, "Model Building in Mathematical Programming," Wiley, New York, 1985. 9. M. S. Bazaraa, J. J. Jarvis, "Linear Programming and Network Flows," Wiley, New York, 1977. 10. G. Hadley, "Linear Programming," Addison-Wesley, Massachussets,1962. 11. H. P. Kuenzi, H. G. Tzschach, C. A. Zehnder, "Numerical Methods of Mathematical Optimization," Academic Press, New York, 1971. 12. W. H. Press, B. P. Flannery, S. A. Teukolsky, W. T. Vetterling, "Numerical Recipes: The Art of Scientific Computing," Cambridge University Press, New York, 1986.

13. N. Deo, "Graph Theory with Applications to Engineering and Computer Science," Prentice Hall, New Jersey, 1974. 14. T.Asano, S. Sato, "Long Path Enumeration Algorithms for Timing Verification on Large Digital Systems," 5th Quadranneil Int'l Conf. on the Theory and Applications of Graphs with special emphasis on Algorithms and Computer Science, Michigan, June 4-8,1984.


McPOWER: A Monte Carlo Approach to Power Estimation Richard Burch*, Farid Najm*, Ping Yang*, and Timothy Trick** *Semiconductor Process & Design Center, Texas Instruments Inc., Dallas, Texas **Electrical Engineering Dept., University of Illinois at Urbana-Champaign, Urbana, IL Abstract Excessive power dissipation in integrated circuits causes overheating and can lead to soft errors and/or permanent damage. The severity of the problem increases in proportion to the level of integration, so that power estimation tools are badly needed for present-day technology. Traditional simulation-based approaches simulate the circuit using test/functional input pattern sets. This is expensive and does not guarantee a meaningful power value. Other recent approaches have used probabilistic techniques in order to cover a large set of inputs patterns. However, they trade-of accuracy for speed in ways that are not always acceptable. In this paper, we investigate an alternative technique that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists o f applying randomly-generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. We present the algorithm and experimental results, and discuss the superiority of this new approach. References [1] S. M. Kang, "Accurate simulation of power dissipation in VLSI circuits," IEEE Journal o f Solid State Circuits, vol. SC-21, no. 5, pp. 889-891, Oct. 1986. [2] G. Y. Yacoub and W. H. Ku, "An accurate simulation technique for short-circuit power dissipation based on current component isolation," IEEE International Symposium on Circuits and Systems, pp. 1157-1161,1989. [3] A-C. Deng, Y-C. Shiau, and K-H. Loh, "Time domain current waveform simulation of CMOS circuits," IEEE International Conference on Computer-Aided Design, pp. 208-211, Nov. 7-10, 1988. [4] M. A. Cirit, "Estimating dynamic power consumption of CMOS circuits," IEEE International Conference on Computer-Aided Design, pp. 534-537, Nov. 9-12, 1987. [5] F. Najm, "Transition density, a stochastic measure of activity in digital circuits," 28th ACM-IEEE Design Automation Conference, San Francisco, CA, pp. 644-649, June 17-21, 1991. [6] C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation," IEEE European Solid State Circuits Conference, pp. 61-64, Grenoble, France, 1990. [7] H. J. M. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE Journal of Solid-State Circuits, vol. SC-19, no. 4, pp. 468-473, Aug. 1984. [8] F. Najm, "Transition density, a new measure of activity in digital circuits," To appear in IEEE Transactions on Computer-Aided Design, 1992. [9] I. R. Miller, J. E. Freund, and R. Johnson, Probability and Statistics for Engineers. Englewood Cliffs, NJ: Prentice Hall, 1990. [10] A. Hald, Statistical Theory with Engineering Applications. New York: John Wiley & Sons, 1952. [11] S. M. Ross, Stochastic Processes. New York: John Wiley & Sons, 1983. [12] A. Papoulis, Probability, Random Variables, and Stochastic Processes, 2nd Edition. New York, NY: McGrawHill Book Co., 1984. [13] F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," IEEE International Symposium on Circuits and Systems, pp. 695-698, June 1985.


Exhaustive Simulation Need Not Require an Exponential Number of Tests Daniel Brand IBM Research Division Yorktown Heights, NY 10598, U.S.A. Abstract Simulation is today the most common form of verification. One disadvantage of simulation is the excessive number of tests needed for complete coverage. However, as will be shown, the number of tests may be substantially reduced if test case generation is combined with a structural analysis. The resulting set of test cases for exhaustive simulation may be smaller than exponential, which might make exhaustive simulation feasible. Even if the set of test cases is still too large, choosing tests from this reduced set results in better coverage than otherwise. References [1] D.A. Basin, P.D. Vecchio, "Verification of Combinational Logic in Nuprl", Lecture Notes in Computer Science, M. Leeser and G. Brown (Eds.) Springer Verlag, July 1989. [2] R. Betancourt, "Derivation of Minimal Test Sets for Unate Logical Circuits", IEEE Transactions on Computers, Vol. C-20, pp. 1264-1269, Nov. 1971.

[3] J.P. Billon, J.C. Madre, "Original Concepts of PRIAM, an Industrial Tool for Efficient Formal Verification of Combinational Circuits", The Fusion of Hardware Design and Verification, G.J. Milne (ed.), North Holland, 1988. [4] D. Brand, "Exhaustive Simulation Need Not Require an Exponential Number of Tests", IBM Research Report, RC 17619, February 1992. [5] R.K. Brayton, G.D. Hachtel, C.T. McMullen, A.L. Sangiovanni-Vincentelli, "Logic Minimization Algorithms for VLSI Synthesis", Kulver Academic Publishers, 1984. [6] R.E. Bryant, "A Methodology for Hardware Verification Based on Logic Simulation", CMU-CS-87-128, June 1987. [7] R.E. Bryant, "Formal Verification of Memory Circuits by Switch-Level Simulation", IEEE Transactions on CAD, Vol. 10, No.1, January 1991, pp. 94-102. [8] S.Devadas, H.K. Ma, A.R. Newton, "On the Verification of Sequential Machines at Different Levels of Abstraction", IEEE Transactions on CAD, Vol 7, pp. 713-722, June 1988. [9] S.H. Hong, R.G. Cain, D.L. Ostapko, "MINI; A Heuristic Approach For Logic Minimization", IBM Journal of Research and Development, Vol. 18, pp. 443-458, Sept 1984. [10] S.H. Hwang, A.R. Newton, "An Efficient Verifier for Finite State Machines", IEEE Transaction on CAD, Vol. 10, No.3, March 1991. [11] IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985, IEEE August 1985. [12] A.A. Malik, R.K. Brayton, A.R. Newton, A. Sangiovanni-Vincentelli, "Reduced Offset for Minimization of Binary-Valued Functions", IEEE Transactions on CAD, Vol. 10, No.4, April 1991, pp. 413-426. [13] V.Pitchumani, E.P. Stabler, "A formal Method for Computer Design Verification", Proceedings of 19th Design Automation Conference, 1982, pp. 809-814. [14] K. Supowit, S.J. Friedman, "A new Method for Verifying Sequential Circuits", Proceedings of 23rd Design Automation Conference, 1986, pp. 200-207.

ICCAD, Pages 104-111

A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis Alexandre Yakovlev Dept. of Computing Science, The University, Newcastle upon Tyne, NE1 7RU, UK Luciano Lavagno Dept. of Electrical Engineering, University of California, Berkeley, CA 94720 Alberto Sangiovanni-Vincentelli Dept. of Electrical Engineering, University of California, Berkeley, CA 94720 Abstract The paper introduces a unified framework to verify directly if a format circuit specification admits a correct implementation under unbounded gate and wire delay models. We describe both low-level (analysis-oriented) and high-level (specification-oriented) models for asynchronous circuits and the environment where they operate, together with strong equivalence results between the properties at the two levels. One interesting side result is the precise characterization of classical static and dynamic hazards in terms of our model. Consequently the designer can check the specification and directly decide if the behavior of any implementation will depend, e.g., on the delays of the signals described by such specification. References [1] E. Best and K. Voss. Free choice systems have home states. Acta Informatica, 21:89-100,1984. [2] T. A. Chu. Synthesis of self-timed control circuits from graphs: an example. In Proceedings of the International Conference on Computer Design, pages 565571,1986. [3] V 1. Varshavsky et al. Self timed Control of Concurrent Processes. Kluwer Academic Publisher, 1990. (Russian edition: 1986). [4] R.M. Keller. A fundamental theorem of asynchronous parallel computation. LNCS, 24:103-112,1975. [5] M. A. Kishinevsky, A. Y Kondratyev, A. R. Taubin, and V 1. Varshavsky. On self :timed behavior verification. In ACM Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1992. [6] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous circuits. In Proceedings of the Design Automation Conference, June 1991. [7] R. E. Miller. Switching theory, volume 2. Wiley and Sons, 1965. [8] D. E. Muller and W. C. Bartky. A theory of asynchronous circuits. In Annals of Computing Laboratory of Harvard University, pages 204-243,1959. [9] L. Y Rosenblum and A. V Yakovlev. Signal graphs: from self-timed to timed ones. In International Workshop on Timed Petri Nets, Torino, Italy, 1985. [10] A. V Yakovlev. Analysis of concurrent systems through lattices. Theoretical Computer Science, Submitted for publication. [11] A. V Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli. A unified signal transition graph model for asynchronous control circuit synthesis. Technical Report UCB/ERL M92/78, U.C. Berkeley, July 1992.


A Generalized State Assignment Theory for Transformations on Signal Transition Graphs Peter Vanbekbergen1, Bill Lin1, Gert Goossens1, Hugo De Man 1,2 1 IMEC Laboratory, Leuven, Belgium 2 ESAT Laboratory, Katholieke Universiteit, Leuven, Belgium Abstract In this paper, we propose a global assignment theory for "encoding" state graph transformations. A constraint satisfaction framework is proposed that can guarantee necessary and sufficient conditions for a state graph assignment to result in a -transformed state graph that is race-free. Performing transformations at the state graph level has the advantage that the requirements imposed on the initial STG are very weak. Unlike previous methods, the initial STG need not be a live, safe, nor a free choice net. The only requirement is that the corresponding initial state graph is finite, connected, and has a consistent state assignment. Hence, a very broad range of signal transition graphs can be synthesized. The transformations achievable using the proposed framework correspond to very complex transformations on signal transition graphs. Even transformations that convert a free choice net into a correct non-free choice net and a 1-safe net into a correct 2-safe net are feasible. Addition of transitions that do not follow the Petri net firing rule is also possible. Even though our method can search a large solution space, we will show that it is possible to solve the problem in an exact way in acceptable CPU times in many practical cases. References [1] T. A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, June 1987. [2] J. E. Hopcroft and J. D. Ullman. Introduction to automata theory, languages and computation. In AddisonWesley. Reading, Mass., 1979. [3] T. Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on CAD, 11(l), January 1992. [4] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous circuits. In Proceedings of the Design Automation Conference, June 1991. [5] L. Lavagno, C. W. Moon, R. K. Brayton, and A. Sangiovanni-Vincentelli. Solving the state assignment problem for signal transition graphs. In Proceedings of the Design Automation Conference, June 1992. [6] T. Murata. Petri nets: Properties, analysis and applications. Proceedings of the IEEE, pages 541-580, April 1989. [7] J. H. Tracey. Internal state assignments for asynchronous sequential machines. IEEE Transactions on Electronic Computers, EC-15(4):551-560, August 1966. [8] S. H. Unger. Asynchronous Sequential Switching Circuits. Wiley Interscience, 1969. [9] P. Vanbekbergen. Optimized synthesis of asynchronous control circuits from graph-theoretic specifications. In Proceedings of the International Conference on Computer-Aided Design, pages 184-187, November 1990. [10] P. Vanbekbergen. Synthesis of Asynchronous Control Circuits from Graph-Theoretic specifications. PhD thesis, Catholic University of Leuven, ESAT, 1992. To appear. [11] V.I. Varshavsky, M.A. Kishinevsky, A.Y. Kondratyev, L.Y Rosenblum, and A.R. Taubin. Models for specification and analysis of processes in asynchronous circuits. Soviet Journal of Computer and Systems Sciences, July 1989. [12] A. V. Yakovlev and A. Petrov. Petri nets and parallel bus controller design. In International Conference on Application and Theory of Petri Nets, Paris, France, June 1990.


On the Verification of State-Coding in STGs Kuan-Jen Lin and Chen-Shang Lin Department of Electrical Engineering, National Taiwan University Abstract One primary property for an Signal Transition Graph (STG) to be synthesized in an asynchronous circuit is the realizable state coding (RSC) - more relaxed than USC. A procedure and its theoretical basis have been developed to verify the RSC property of a STG which contains multi-cycle signals and has a underlying free-choice Petri net. The procedure is carried out wholly on STG domain and is successful to verify the RSC of benchmarks[3]. References [1] T. A. Chu, "Synthesis of Self-Timed Control Circuits from Graphical Specifications", PhD thesis, MIT, June, 1987. [2] T. H.-Y. Meng, Robert W. Brodersen, David G. Messerschimitt, "Automatic Synthesis of Asynchronous Circuits from High-Level Specification," IEEE Trans. on CAD., pp. 1185-1205, No. 11, 1989. [3] L. Lavagno and Cho W. Moon, "Private Communication". [4] Peter Vanbekbergen, Francky Catthoor, Jef Van Meerbergen, Hugo DE Man, "Optimized Synthesis of Asynchronous Control Circuits from Graph-theoretic Specifications," Proceeding of the International Conference on Computer-Aided Design, pp. 184-187, 1990. [5] K. J. Lin and C. S. Lin, "Automatic Synthesis of Asynchronous Circuits," Proceeding of 28th Design Automatic Conference, pp. 296-301, 1991. [6] L. Lavagno, K. Keutzer, A. Sangiovanni-Vincentelli, "Algorithms for Synthesis of Hazard-free Asynchronous Circuits," Proceeding of 28th Design Automatic Conference, pp. 302-308, 1991. [7] Cho W. Moon, Paul R. Stephan and Robert K. Brayton, "Synthesis of Hazard-free Asynchronous Circuits from Graphical Specifications," Proceeding of the International Conference on Computer-Aided Design, pp. 322-325, 1991. [8] K. J. Lin and C. S. Lin, "A Realization Algorithm of of Asynchronous Circuits from STG," Proceeding of 1992 European Conference on Design Automation, pp. 322-326. [9] J. L. Peterson, "Petei net theory and the modeling of system," prentice Hall, 1981. [10] K. J. Lin, "Automatic Synthesis of Asynchronous Circuits," Ms. thesis, EE Department of National Taiwan University, 1990. [11] K. J. Lin and C. S. Lin, "The verification of State-Coding in STGs," Technical report, EE Department of National Taiwan University, 1992.


Verifying Clock Schedules Thomas G. Szymanski, AT&T Bell Laboratories, Murray Hill, NJ 07974 Narendra Shenoy University of California Berkeley, CA 94720 Abstract Many recent papers have formulated both timing verification and optimization as mathematical programming problems. Such formulations correctly handle level-sensitive latches, long and short path considerations, and sophisticated multi-phase clocking schemes. This paper deals with the computational aspects of using such a formulation for verifying clock schedules. We show that the formulation can have multiple solutions, and that these extraneous solutions can cause previously published algorithms to produce incorrect or misleading results. We characterize the conditions under which multiple solutions exist, and show that even when the solution is unique, the running times of these previous algorithms can be unbounded. By contrast, we exhibit a simple polynomial time algorithm for clock schedule verification. The algorithm was implemented and used to check the timing of all the circuits in the ISCAS-89 suite. Observed running times are linear in circuit size and quite practical. References [BSM92] Timothy M. Burks, Karem A. Sakallah, and Trevor N. Mudge. Multi-phase retiming using minTc. In ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992. [IL90] Alexander T. Ishii and Charles E. Leiserson. A timing analysis of level-clocked circuitry. In William J. Dally, editor, Proceedings of the Sixth MIT Conference, Advanced Research in VLSI, pages 57-69. MIT Press, 1990. [LB92] Wei-Han Lien and Wayne Burleson. Wave-domino logic: Timing analysis and applications. In ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992. [SBSV92] Narendra Shenoy, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. A pseudo-polynomial algorithm for verification of clocking schemes. In ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992. [SM090] Karem A. Sakallah, Trevor N. Mudge, and Oyekunle A. Olukotun. checkTc and minTc: timing verification and optimal clocking of synchronous digital circuits. In Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pages 552-555, November 1990. [SM092] Karem A. Sakallah, Trevor N. Mudge, and Oyekunle A. Olukotun. Analysis and design of latch-controlled synchronous digital circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 11(3):322-333, March 1992. [Szy92] Thomas G. Szymanski. Computing optimal clock schedules. In Proceedings of the IEEE/ACM Design Automation Conference, volume 29, pages 399-404, June 1992. [TL91] Ren-Song Tsay and Ichiang Lin. A system timing verifier for multi-phase level-sensitive clock designs. Technical Report RC 17272, IBM, October 1991.


Graph Algorithms for Clock Schedule Optimization Narendra Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Department of EECS, University of California, Berkeley, CA Abstract Performance driven synthesis of sequential circuits relies on techniques such as optimal clocking, retiming and resynthesis. In this paper we address the optimal clocking problem and demonstrate that it is reducible to a parametric shortest path problem. We use constraints that take into account both the short and long paths. The main contributions are efficient graph algorithms to solve the set of constraints necessary for correct clocking. References [1] M. R. Dagenais and N. C. Rumin. Automatic Determination of Optimal Clocking Parameters in MOS VLSI Circuits. In Advanced Research in VLSI: Proc. of the 5th MIT Conference, pages 19-33,1988. [2] R. B. Hitchcock. Timing Verification and Timing Analysis Program. In Proceedings of the Design Automation Conference. IEEE/ACM, 1982. [3] A. T. Ishii, C. E. Leiserson, and M. C. Papaefthymiou. Optimizing Two-Phase Level-Clocked Circuitry. Advanced Research in VLSI and Parallel Systems, 1992. [4] N. P. Jouppi. Timing Verification and Performance Improvement of MOS VLSI Designs. PhD thesis, Stanford University, Stanford CA-94305, October 1984. [5] E. L. Lawler. Combinatorial Optimization: networks and Matroids. Holt, Rinehart and Winston,1976. [6] J. K. Ousterhout. A Switch-Level Timing Verifier for Digital MOS VLSI. IEEE Transactions on ComputerAided Design, CAD-4(3):336-349, July 1985. [7] K. Sakallah, T. N. Mudge, and 0. A. Olukotun. Check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 552-555.IEEE, 1990. [8] E. Sentovich et al. Sequential Circuit Design Using Synthesis and Optimization. In Proceedings of the International Conference on Computer Design, 1992. [9] N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. Graph Algorithms for Clock Schedule Optimization. Technical report, University of California, Technical Report UCB/ERL M92/79,1992. [10] T. G. Szymanski. LEADOUT: A Static Timing Analyzer for MOS Circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 130-133. IEEE, 1986. [11] T. G. Szymanski. Computing Optimal Clock Schedules. In Proceedings of the Design Automation Conference, pages 399-404.IEEE/ACM,1992. [12] S. H. Unger and C. J. Tan. Clocking Schemes for High-Speed Digital Systems. IEEE Transactions on Computers, C-35(10):880-895, October 1986. [13] D. Wallace and C. H. Sequin. ATV: An Abstract Timing Verifier. In Proceedings of the Design Automation Conference, pages 154-159. IEEE/ACM, 1988. [14] N. Weiner and A. Sangiovanni-Vincentelli. Timing Analysis in a Logic Synthesis Environment. In Proceedings of the Design Automation Conference, pages 655-661. IEEE/ACM, 1989.


Identification of Critical Paths in Circuits with Level-Sensitive Latches Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge The University of Michigan Abstract This paper describes an approach to timing verification of circuits with level-sensitive latches which focuses on the critical paths that constrain the operating speed of these circuits. The timing model we use has been referred to as the SMO model and was originally described in [1]. In this work, we show that three types of critical paths can arise in the SMO formulation; verifying their timing is sufficient to ensure correct operation. We present an algorithm for identifying these paths and discuss its relationship to other approaches to solving the SMO model equations. Finally, we present results which demonstrate our algorithm on circuits from the ISCAS89 benchmark suite. References [1] K. A. Sakallah, T. N. Mudge, and O. A. Olukotun, "checkTc and minTc: Timing verification and optimal clocking of synchronous digital circuits," ICCAD-90 Digest of Technical Papers, November 1990. [2] T. G. Szymanski, "Verifying Clock Schedules," ICCAD90 Digest of Technical Papers, 1992. [3] N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A pseudo-polynomial algorithm for verification of clocking schemes," ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992. [4] F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," ISCAS89 Proceedings, 1989. [5] T. G. Szymanski, "Computing Optimal Clock Schedules," Design Automation Conference Proceedings, 1992


Using Constraint Geometry to Determine Maximum Rate Pipeline Clocking Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah EECS Department, University of Michigan, Ann Arbor Abstract Geometric knowledge of the shape of the feasible region formed by pulse width, setup, and hold constraints, is used directly by a new efficient (cubic complexity) algorithm, Gpipe, to determine the maximum rate for single-phase clocking of a given pipeline. The pipeline model uses levelsensitive latches as synchronizers and can allow wave pipelining. Gpipe is also used to explore the effect of removing nonsynchronizing and/or synchronizing latches on the maximum clock speed of the pipeline. A simple test shows which latches, if any, to remove to guarantee no decrease and permit a possible increase in the clock rate. References [1] K. A. Sakallah, T. N. Mudge, T. M. Burks, and E. S. Davidson, "Optimal Clocking of Circular Pipelines", in Proc. ICCD '91, pp. 642-646, October 1991. [2] K. A. Sakallah, T. N. Mudge, T. M. Burks, and E. S. Davidson, "Optimal Clocking of Circular Pipelines", Technical Report CSE-TR-97-91, University of Michigan, Dept of EECS, Ann Arbor, MI 48109-2122, June 1991. [3] D. Wong, G. D. Micheli, and M. Flynn, "Inserting Active Delay Elements to Achieve Wave Pipelining", ICCAD89 Digest of Technical Papers, pp. 270-273, 1989.


HIMALAYAS- A Hierarchical Compaction System with a Minimized Constraint Set Jin-fuw Lee and Donald T. Tang IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 Abstract A new hierarchical compactor, Himalayas (HIerarchical MAcro LAYout ASsembler), has been developed for constructing big macro layouts. The hierarchical compaction problem is formulated as an integer linear programming (ILP) problem. In this paper, we present two novel algorithms to reduce the problem size, in order to make ILP approach practical. The first algorithm reduces the number of variables to a small set of pitch variables, while the second algorithm reduces the number of equations by restricting the constraint generation within a small set of regions, called the minimum cover. These reductions bring in considerable saving in computation time for layouts with cell repetitions, or cell alignments. As a result, ILP method can be used to solve the compaction problem for very big macros. Experimental results for MCNC benchmark examples are also given. References 1. D. Boyer, "Symbolic compaction benchmarks", Proc. Int. Conf. on Computer Design, pp. 186-191; 209-217, 1987. 2. C. Kingsley, "A Hiererachical, error-tolerant compactor", Proc. 21th Design Automation Conf., pp. 126-132, 1984. 3. P. Eichenberger and M. Horowitz, "Toroidal compaction of symbolic layouts for regular structures", Proc. ICCAD, pp. 142-145, 1987. 4. K. Mehlhorn and W. Rulling, "Compaction on the torus", IEEE trans on CAD, vol. 9, No. 4, pp. 389- 397, Apr. 1990. 5. D. Marple, M. Smulders and H. Hegen, "Tailor: A layout system based on trapezoidal corner stitching", IEEE trans on CAD, vol. 9, No. 1, pp. 66- 90, Jan. 1990. 6. C. S. Bamji and R. Varadarajan, "Hierarchical pitchmatching compaction using minimum design", Proc. 29th Design Automation Conf., pp. 311-317, 1992. 7. W. Kim, J. Lee and H. Shin, "A new hierarchical layout compactor using simplified graph model", Proc. 29th Design Automation Conf., pp. 323-326, 1992. 8. H. Shin, A. L. Sangiovanni-Vincentelli, and C. H. Sequin, "Two-dimensional module compactor based on zone-refining", Proc. Int. Conf. on Computer Design, pp. 201-203, 1987. 9. C. Lo and R. Varadarajan, "An O(n1.5 log n) 1-d compaction algorithm", Proc. 27th Design Automation Conf., pp. 382-387, 1990. 10. D. Marple, "A hierarchy preserving hierarchical compactor", Proc. 27th Design Automation Conf., pp. 375-381, 1990. 11. C. Bamji, C. Hauck, and J. Allen, "A design-by-example regular structure generator", Proc. 27th Design Automation Conf., pp. 16-22, 1990. 12. M. Y. Hsueh, "Symbolic layout and compaction of integrated circuits", ERL Memo, UCB/ERL M79/80, Univ. of Berkeley, Dec. 1979. 13. J. F. Lee, "A new framework of design rules for compaction of VLSI layouts", IEEE trans on CAD, vol. 7, No. 11, pp. 1195- 1204, Nov 1988. 14. Optimization Subroutine Library, IBM manual SC23-0519-02


Cloning Techniques for Hierarchical Compaction Ravi Varadarajan and Cyrus S. Bamji Cadence Design Systems, 555 River Oaks Parkway, San Jose, CA 95134, Abstract True hierarchical compaction maintains input layout hierarchy as well as abutment constraints between cells. The bottleneck for hierarchical compaction is the time taken to analyze the system of equations which must be solved via linear programming methods. Because of the computational complexity of linear programming, it is essential to keep this system of equations as small as possible. With over the cell routing the amount of interaction between levels of hierarchy increases considerably. This causes a substantial rise in the number of constraints and so the time taken by the compaction process is significantly increased. A novel method for handling over the cell routing, termed cloning, is described. This approach allows for efficient compaction of arbitrary hierarchies containing over the cell routing without significantly degrading the run time performance of the hierarchical compactor. References [1] C. Bamji and R. Varadarajan. Hierarchical pitch-matching compaction using minimimum design. In ACM IEEE 29th DAC, 1992. [2] J. Doenhardt and T. Lengauer. Algorithmic aspects of one dimensional layout compaction. IEEE Transactions on CAD, CAD-6, 1987. [3] Y. Liao and C. Wong. An algorithm to compact VLSI symbolic layouts with mixed constraints. IEEE Transactions on CAD, CAD-2, 1983. [4] D. Marple. A hierarchy preserving hierarchical compactor. In ACM IEEE 27th DAC, 1990.


An Optimal Chip Compaction Method Based on Shortest Path Algorithm with Automatic Jog Insertion Toru Awashima, Wataru Yamamoto, Masao Sato, and Tatsuo Ohtsuki Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan Abstract A new one-dimensional compaction method for layout patterns including rectilinear macro-cells on any number of layers is presented in this paper. The algorithm is based on the shortest path search on a constraint graph. It generates an optimal layout pattern in the smallest area by introducing effective jogs in O(N log N) time, where N is the number of line segments of the input pattern and inserted jogs. The jogs are inserted by means of an enhanced plane-sweep method developed in the field of computational geometry. Performance data of an experimental program show its efficiency. References [1] W.-K. Chen, Theory of Nets: Flows in Networks, A Wiley-Interscience Publication, 1990. [2] C.-K.Cheng and D. N. Deutsch, "Improved Channel Routing by Via Minimization and Shifting," Proc. 25th DA Conf., pp.677-680, 1988. [3] G. B. Dantzig, W. 0. Blattner, and M. R. Rao, "All Shortest Routes from a Fixed Origin in a Graph," Proc. Int. Symp. Theorie des Graphes, pp.85-90, 1966. [4] H. Imai, "Notes on the One-Dimensional Compaction Problem of LSI Layouts Viewed from Network Flow Theory and Algorithms," Trans. IECE Japan, Vol.E69, No.10, Oct. 1986. [5] M. Ohmura et al., "Hierarchical Floor-planning and Detailed Global Routing with Routing-Based Partitioning," Proc. ISCAS 90, pp.1640-1643, 1990. [6] J. Royle, M. Palczewski, H. VerHeyen, N. Naccache, and J. Soukup, "Geometrical Compaction in One Dimension for Channel Routing," Proc. 24th DA Conf., pp.140-145, 1987. [7] M. Sato and T. Ohtsuki, "Enhanced Plane-Sweep Methods for LSI Pattern Design Problems," Technical Report, IECE of Japan, No.CAS86-199, pp.87-94, Jan. 1987. [8] W. L. Schiele, "Automatic Design Rule Adaptation of Leaf Cell Layouts," Integration the VLSI Journal, No.3, pp.93112, 1985. [9] X.-M. Xiong and E. S. Kuh, "Nutcracker: An Efficient and Intelligent Channel Spacer," Proc. 24th DA Conf. , pp.298-304, 1987. [10] X.-M. Xiong and E. S. Kuh, "Geometric Compaction of Building-Block Layout," Proc. CICC'89, May 1989.


MOSAIC: A Tile-Based Datapath Layout Generator Goro Suzuki*,Tetsuya Yamamoto*, Kyoji Yuyama**, Kotaro Hirasawa*** * Hitachi Research Laboratory, Hitachi Ltd., Hitachi-shi, Japan ** Device Development Center, Hitachi Ltd., Tokyo, Japan *** Omika Works, Hitachi Ltd., Hitachi-shi, Japan Abstract A the-based datapath layout generator is proposed. MOSAIC achieves a new routing technique which uses bus patterns pre-placed all over the leaf cell and joins these segments based on module schematic information. With this routing technique, a high layout density can be achieved. Based on experience, the layout density of the 120MHz microprocessor datapath module was 10,000-20,000 transistors/mm2 in 0.5 micron three-metal Bi-CMOS technology. Leaf cells are not only used in one module design, but are reusable across multiple module designs. Only 100 kinds of leaf cells were needed for 300 module designs. References [1] H.S. Law et al., "An Intelligent Composition Tool for Regular and Semi-regular VLSI Structures", Proc. of International Conference on Computer Aided Design, pp.169-171 (1985, Oct.) [2] R. Barth et al.," A Structural Representation for VLSI Design", Proc. of 25th Design Automation Conference, pp.237-242 (1988, June) [3] R.Barth et al., "Parameterized Schematics", Proc. of 25th Design Automation Conference, pp.243-249 (1988, June) [4] R.Barth et al., "Patchwork: Layout from Schematic Annotations", Proc. of 25th Design Automation Conference, pp.250-255 (1988, June) [5) D. Curry et al. "Schematic Specification of Datapath Layout", Proc. of International Conference on Computer Aided Design, pp.28-34 (1989, Oct.) [6] N. Matsumoto et al., "Data Path Generator Based on Gate-level Symbolic Layout", Proc. of 27th Design Automation Conference, pp388-393 (1990, June) [7] A. Hashimoto et al., "Wiring Routing Channel Assignment within Large Apertures", Proc. of 8th Design Automation Conference, pp.155-169 (1971, June) [8] E. Barke, "A Network Comparison Algorithm for Layout Verification of Integrated Circuits", IEEE Trans. on Computer Aided Design, ppl35-141 (1984, Apr.) [9] C. Ebeling et al., "Validating VLSI Circuit Layout by Wirelist Comparison", Proc. of International Conference on Computer Aided Design, pp 172-173 (1983, Nov.)


Automatic Compositional Minimization in CTL Model Checking Massimiliano Chiodo Magneti Marelli, Pavia, Italy Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton Department of EECS, University of California, Berkeley, CA 94720 Abstract We describe a method for reducing the complexity of CTL model checking on a system of interacting finite state machines. The method consists essentially of reducing each component machine with respect to the property we want to verify, and then verifying the property on the composition of the reduced components. The procedure is fully automatic and produces an exact result. We assess the potential of our approach on real-world examples, and demonstrate the method on a circuit. References [1] D. Arnett, "A High Performance Solution for In-Vehicle Networking - `Controller Area Network (CAN),"' SAE Technical Paper Series, 870823, Apr. 1987. [2] R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, C35(8), pp. 677-691, Aug. 1986. [3] J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," in Proc. of 27th Design Automation Conference, pp. 46-51, June 1990. [4] J. R. Burch, E. M. Clarke, and D. E. Long, "Representing Circuits More Efficiently in Symbolic Model Checking," in Proc. of 28th Design Automation Conference, pp. 403-407, June 1991. [5] M. Chiodo, T. R. Shiple, A. Sangiovanni-Vincentelli, and R. K. Brayton, "Automatic Reduction in CTL Compositional Model Checking," Memorandum No. UCB/ERL M92/55, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, Jan. 1992. [6] E. M. Clarke, E. A. Emerson, and P. Sistla, "Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications," ACM Trans. Prog. Lang. Syst., 8(2), pp. 244-263,1986. [7] E. M. Clarke, D. E. Long, and K. L. McMillan, "Compositional Model Checking," in Proc. of the 4th Annual Symposium on Logic in Computer Science, Asilomar, CA, June 1989. [8] E. M. Clarke, O. Grumberg and D. E. Long, "Model Checking and Abstraction," in Proc. of Principles of Programming Languages, Jan. 1992. [9] O. Coudert, C. Berthet, and J. C. Madre, "Verification of Synchronous Sequential Machines Based on Symbolic Execution," in Lecture Notes in Computer Science: Automatic Verification Methods for Finite State Systems, vol. 407, editor J. Sifakis, Springer-Verlag, pp. 365-373, June 1989. [10] E. A. Emerson, "Temporal and Modal Logic," in Handbook of Theoretical Computer Science, editor J. van Leeuwen, Elsevier Science Publishers BX, pp. 995-1072,1990. [11] S. Graf and B. Steffen, "Compositional Minimization of Finite State Systems," in Lecture Notes in Computer Science: Proc. of the 1990 Workshop on Computer-Aided Verification, vol. 531, editors R. P Kurshan and E. M. Clarke, SpringerVerlag, pp. 186-196, June 1990. [12] O. Grumberg and D. E. Long, "Model Checking and Modular Verification," in Lecture Notes in Computer Science: Proc. CONCUR '91: 2nd Inter. Conf. on Concurrency Theory, vol. 527, editors J. C. M. Baeten and J. F. Groote, Springer-Verlag, Aug. 1991. [13] J. E. Hopcroft, "An n log n Algorithm for Minimizing the States in a Finite Automaton," in The Theory of Machines and Computation, New York: Academic Press, pp. 189-196, 1971. [14] R. P. Kurshan and K. L. McMillan, "A Structural Induction Theorem for Processes," in Proc. of 8th ACM Symp. on Principles of Distributed Computing, Aug. 1989. [15] R. P. Kurshan, "Analysis of Discrete Event Coordination," in Lecture Notes in Computer Science: Proc. REX Workshop on Stepwise Refinement of Distributed Systems, Models, Formalisms; Correctness, vol. 430, editors J. W. de Bakker, W. -P. de Roever, and G. Rozenberg, SpringerVerlag, May 1989.

[16] Z. Manna and A. Pneuli, "Verification of Concurrent Programs: The Temporal Framework," in The Correctness Problem in Computer Science, editors R. S. Boyer and J. Strother Moore, Int. Lecture Series in Computer Science, London: Academic Press, pp. 215-273,1981. [17] E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Sequential Circuit Design Using Synthesis and Optimization," in Proc. of International Conference on Computer Design, Oct. 1992. [18] H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit State Enumeration of Finite State Machines using BDDs," in Proc. of IEEE International Conference on Computer-Aided Design, pp. 130-133, Nov. 1990. [19] P Wolper and V Lovinfosse, "Verifying Properties of Large Sets of Processes with Network Inv ariants," in Lecture Notes in Computer Science: Automatic Verification Methods for Finite State Systems, vol. 407, editor J. Sifakis, Springer-Verlag, pp. 68-80, June 1989.


Verification of Systems Containing Counters Enrico Macii, Bernard Plessier, Fabio Somenzi University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO 80309 Abstract Systems containing counters have very large and deep state spaces, and the verification of properties on these systems can be very expensive in terms of memory space and computation time. We present a technique to automatically reduce the state space associated with the system on which some properties, that can express both safeness and fairness constraints, have to be proved. In particular, we give a set of conditions upon which some counters can be reduced to three state, non-deterministic machines, and the controllers can be simplified by removing the redundancy induced by their interaction with the counters, so that the verification of tasks can be more easily performed. References [1] R. P. Kurshan, "Analysis of Discrete Events Coordination", LNCS, Vol. 430, pp. 414-453,1990. [2] Z. Har El, R. P. Kurshan, "Software for Analytical Development of Communications Protocols", AT&T Tech. Journal, pp. 45-59, January 1990. [3] O. Coudert, C. Berthet, J. C. Madre, "Verification of Sequential Machines Using Boolean Functional Vectors", International Workshop on Applied Formal Methods for Correct VLSI Design, pp. 111-118, November 1989. [4] H. Cho, G; D. Hachtel, S. W. Jeong, B Plessier, E. Schwarz, F. Somenzi, "ATPG Aspects of FSM Verification", ICCAD-90, pp. 134-137, November 1990. [5] C. Mead, L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980. [6] S. Devadas, K. Keutser, A. S. Krishnakumar, "Design Verification and Reachability Analysis Using Algebraic manipulation", ICCD-91, pp. 150-158, October 1991. [7] J. R. Burch, E. M. Clarke, K. L. McMillan, D. Dill, "Sequential Circuit Verification Using Symbolic Model Checking", DAC90, pp. 46-51, June 1990. [8] A. Ghosh, S. Devadas, "A Mixed Depth-First/Breadth-First Traversal Technique for Sequential Logic Verification", MCNC Workshop on Logic Synthesis, Vol. 3, May 1991. [9] E. M. Clarke, O. Grunberg, D. E. Long, "Model Checking and Abstraction", SPPL-98, January 1991.


Automatic Generation and Verification of Sufficient Correctness Properties for Synchronous Processors Filip Van Aelten, Stan Y. Liao, Jonathan Allen, Srinivas Devadas Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Abstract We present a general strategy for automatically generating and verifying sufficient correctness properties for a broad class of synchronous processors. Given a particular specification and implementation pair, we show how basic correctness properties can be algorithmically translated into a set of Computation Tree Logic (CTL) formulae which are sufficient for equivalence between the behavioral and logic descriptions. Preliminary experimental results on the verification of microcoded and array processors are presented. References [1] F. Van Aelten, J. Allen, and S. Devadas. Verification of Relations between Synchronous Machines. In Proceedings of the International Conference on Computer Aided Design, pages 380-383, November 1991. [2] Filip Van Aelten. Automatic Procedures for the Behavioral Verification of Digital Designs. Ph.D Dissertation, MIT, June 1992. [3] J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential Circuit Verification Using Symbolic Model Checking. In Proceedings of the 27th Design Automation Conference, pages 46-51, June 1990. [4] E. M. Clarke and O. Grumberg. Research on Automatic Verification of Finite-State Concurrent Systems. In Annual Reviews of Computer Science, volume 2, pages 269-290, 1987. [5] A. Cohn. A Proof of Correctness of the VIPER Microprocessor: The First Level. In G. Birtwistle and P.A. Subrahmanyam, editors, VLSI Specification, Verification and Synthesis, pages 27-71. Kluwer Academic Publishers, 1988. [6] O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Using Boolean Functional Vectors. In IMEC-IFIP Int'l Work shop on Applied Formal Methods for Correct VLSI Design, pages 111-128, November 1989. [7] G. Goossens, J. Rabaey, J. Vandewalle, and H. De Man. An Efficient Microcode Compiler for Application Specific DSP Processors. In IEEE Transactions of Computer-Aided Design, pages 925-937, September 1990. [8] P. Hilfinger. A High-Level Language and Silicon Compiler for Digital Signal Processing. In Proceedings of the Custom Integrated Circuits Conference, pages 213-216, May 1985. [9] W. Hunt. FM8501: A Verified Microprocessor. University of Texas, Austin, Tech. Report 47, 1985. [10] J. Joyce. Formal Verification and Implementation of a Microprocessor. In G. Birtwistle and P.A. Subrahmanyam, editors, VLSI Specification, Verification and Synthesis, pages 129-157. Kluwer Academic Publishers, 1988. [11] S. Y. Kung. VLSI Array Processors. Prentice-Hall, Englewood Cliffs, N. J., 1988. [12] F. T. Leighton. Introduction to Parallel Algorithms and Atchitectures: Arrays, Trees, Hypercubes. Morgan Kaufmann, San Mateo, Calefornia, 1992. [13] S. Y. Liao. Automatic Generation and Verification of Synchronous Array Processors. Master's thesis, Massachusetts Institute of Technology, August 1992.


Verification of Asynchronous Interface Circuits with Bounded Wire Delays Srinivas Devadas MIT, Cambridge Kurt Keutzer Synopsys, Inc. Sharad Malik Princeton University Albert Wang Synopsys, Inc. Abstract We address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table, under the fundamental mode of operation. We give a procedure to extract the complete set of possible flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence. References [1] M. C. Browne, E. M. Clarke, and D. L. Dill. Automatic Circuit Verification Using Temporal Logic: Two new examples. In Proceedings of Int'l Conference on Computer Design: VLSI in Computers, October 1985. [2] R. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. In IEEE Transactions on Computers, volume C-35, pages 677-691, August 1986. [3] J. Burch. Delay Models for Verifying Speed Dependent Asynchronous Circuits. In Proceedings, Tau 92: 1992 ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992. [4] O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Using Boolean Functional Vectors. In IMEC-IFIP Int'l Workshop on Applied Formal Methods for Correct VLSI Design, pages 111-128, November 1989. [5] S. Devadas, K. Keutzer, S. Malik, and A. Wang. Event Suppression: Improving the Efficiency of Timing Simulation for Synchronous Digital Circuits. In Proceedings of the Brown/MIT Advanced Research in VLSI and Parallel Systems, pages 195-209, March 1992. [6] S. Devadas, K. Keutzer, S. Malik, and A. Wang. Verification of Asynchronous Circuits with Bounded Wire Delays. In Massachusetts Institute of Technology Technical Report, March 1992. [7] S. Devadas, H-K. T. Ma, and A. R. Newton. On the Verification of Sequential Machines at Differing Levels of Abstraction. In IEEE Transactions on Computer-Aided Design, pages 713-722, June 1988. Correction in May 1989. [8] D. L. Dill. Trace Theory for the Automatic Hierarchical Verification of Speed-Independent Circuits. MIT Press, 1987. [9] D. L. Dill. Timing Assumptions and Verification of Finite-State Concurrent Systems. In Proceedings of the Workshop on Automatic Verification Methods for Finite State Systems, Volume 407 of Lecture Notes in Computer Science, June 1989. [10] A. D. Friedman and P. R. Menon. Theory and Design of Switching Circuits. Computer Science Press, 1975. [11] A. Ghosh, S. Devadas, and A. R. Newton. Verification of Interacting Sequential Circuits. In Proceedings of the 27th Design Automation Conference, pages 213-219, June 1990.

[12] N. Ishiura, Y. Deguchi, and S. Yajima. Coded Time-Symbolic Simulation using Shared Binary Decision Diagrams. In Proceedings of the 27th Design Automation Conference, pages 130-135, June 1990. [13] N. Ishiura, M. Takahashi, and S. Yajima. Time-Symbolic Simulation for Accurate Timing Verification. In Proceedings o f the 26th Design Automation Conference, pages 497-502, June 1989. [14] L. Lavagno, K. Keutzer, and A. SangiovanniVincentelli. Algorithms for synthesis of hazardfree asynchronous circuits. In Proceedings o f the Design Automation Conference, June 1991. [15] S. H. Unger. Asynchronous Sequential Switching Circuits. Wiley Interscience, 1969.


Delay and Bus Current Evaluation in CMOS Logic Circuits A. Nabavi-Lishi and Nicholas Rumin Microelectronics and Computer Systems Lab, Department of Electrical Engineering, McGill University, Montreal, Canada Abstract An accurate and fast analytical technique is presented for computing the delay and the maximum supply current in a CMOS inverter. It accounts for the effects o f input slope, output load, transistor size, and short-circuit current. The accuracy is within 10% of the HSPICE level-3 model and the speed is more than 3 orders of magnitude faster than HSPICE. An extension of this technique is shown for the calculation of the delay and the maximum supply current of a chain of inverters, without recourse to integration. An efficient method is also presented to compute the total current wave form of the chain. The relative speed of computing current wave form exceeds 2 orders of magnitude compared to HSPICE. References [1] N. Hendestierna and K. O. Jeppson, "CMOS circuit speed and buffer optimization, " IEEE Trans. ComputerAided Design, pp. 270-281, Mar. 1987. [2] T. Sakurai, and A.R. Newton, "Alpha-Power law MOSFET model and its applications to CMOS inverter delay and other formulas, " IEEE J. Solid-State Circuits, vol. 25, No. 2, pp. 584-593, April 1990. [3] T. Sakurai, and A. R. Newton, "Delay analysis of series-connected MOSFET circuits", IEEE J. Solid-State Circuits, vol. 26, No. 2, pp. 122-130, Feb. 1991. [4] A. M. Martinez, "Quick estimation of transient currents in CMOS integrated circuits, " IEEE J. Solid-State Circuits, vol.24, No.2, pp. 520-531, Apr. 1989. [5] D. Stark, and M. Horowitz, "Analyzing CMOS power supply networks using ARIEL, " IEEE Design Automation Conference, pp.460-464, June 1988. [6] S. Chowdhury, and J. S. Barkatullah, "Estimation of maximum currents in MOS IC logic circuits, " IEEE Trans. on Computer- Aided Design, vol. 9, No. 6, pp. 642-654, June 1990. [7] U. Jagau, "SIMCURRENT-an efficient program for the estimation of the current flow of complex CMOS circuits, " IEEE Int. Conf. on Computer-Aided Design, pp. 396-399, Nov. 1990. [8] A. Nabavi-Lishi, N. C. Rumin, "A CMOS inverter analytical model for delay and current evaluation, " submitted to IEEE Trans. On Computer-Aided Design, April 1992. [9] A. Nabavi-Lishi, N. Rumin, "Delay and current evaluation in CMOS combinational circuits," in prepration. [10] HSPICE Users' Manual, H9001, Meta-Software, Inc., 1990. [11] A. Nabavi-Lishi, N. C. Rumin, "Simultaneous delay and maximum current calculation in CMOS gates, " IEE Electronics Letters, vol. 28, No. 7, pp. 682-684, March 1992.


Power Estimation Tool for Sub-Micron CMOS VLSI Circuits F. Rouatbi, B. Haroun, A. J. Al-Khalili Department of Electrical Engineering, Concordia University, Montreal, Quebec Abstract Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. Previous approaches for switch level current simulations used simple current models that did not match accurately the supply current. In this paper, we present a detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3, at peak values and 5% on the average current. Our current model accounts for short-channel effects, input rise times, short-circuit and dynamic current and circuit topology. Moreover, our model produces piecewise linear current waveforms and hence can be easily incorporated in any switch-level simulator. Using our models in an event driven simulator we achieved 3-4 orders of magnitude speed-up relative to SPICE LEVEL 3. Our results for current waveform accuracy outperform previously published methods and in particular for complex CMOS circuits. References [1] S. Chowdhury, J. S. Barkatullah," Estimation of Maximum currents in MOS IC logic circuits" IEEE Transactions on CAD, Vol. 9, NO. 6, June 90, pp. 642-654 [2] A. Chang, Y. Shiau, K. Loh, "Time Domain current waveform Simulation of CMOS Circuits", IEEE Transactions on CAD, 88, pp. 208-211 [3] D.A. Haeusseler, K.F. Poole, "CURRANT: a current prediction software tool using a switch-level simulator", SOUTHEASTCON 89 Proceedings, vo1.3, 89, pp. 946-948 [4] U. Jagau, K.P. Dyck, H. Grabinski, H.J. Iden, and M. Kuboschek, "Power distribution strategies Based on current Estimation and simulation of lossy transmission lines in conduction with power isolation circuits ", IEEE Conference WSI,1990, pp. 288-297 [5] S. M. Kang, H. Y. Chen, "A Global Delay Model for Domino CMOS Circuits with Application To transistor Sizing", International Journal of Circuit Theory and Applications, Vol. 18, 90, pp. 289-306 [6] T. Sakurai, A. Richard Newton, "Delay Analysis of Series-Connected MOSFET Circuits", IEEE Journal of Solid-State Circuits, Vol. 26, NO. 2, February 1991, pp. 122-131 [7] N. Hendenstierna, K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization", IEEE Transactions on CAD, Vol. CAD-6, NO 2, March 1987, pp. 269-281 [8] Harry J. M. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits", IEEE Journal of solid state circuits, Vol. 19, No. 4, August 1984, 468-473 [9] K. Toh, P. Ko, and R. G. Meyer, "An engineering model for short-channel MOS devices", IEEE Journal of solid-state circuits, Vol. 23, No. 4, August 1988, pp. 950-958. [10] John K. Ousterhout, "Switch-Level Delay Models for Digital MOS VLSI", IEEE 21st Design automation conference, 1984, pp. 542-548 [11] J. E. Hall, D.E. Hocevar, P Yang, M. J. McGraw, "SPIDER - A CAD System for Modeling VLSI Metallization Patterns", IEEE Transactions on CAD, VOL. CAD-6, No. 3, November 1987, pp. 1023-1031. [12] J. H. Wang, J. T. Fan, W. S. Feng, "A Novel Current Model for CMOS Gates", IEEE International Symposium on Circuits and Systems, Vol. 5 pp. 2132-2133, 1992 [13] Maple, version 4.2, Watcom, University of Waterloo. [14] F. Rouatbi, B. Haroun, A.Alkhalili, "Supply Current Simulation for Sub-micron CMOS VLSI circuits", submitted to IEEE transactions on CAD, Jul. 92.


A Probabilistic Timing Approach to Hot-Carrier Effect Estimation Ping-Chung Li, Georgios I. Stamoulis, and Ibrahim N. Hajj Coordinated Science Laboratory and ECE Department, University of Illinois Urbana, IL Abstract In this paper a new approach is presented for estimating hot-carrier induced degradation in MOS transistor circuits. The approach uses probabilistic timing simulation techniques to estimate the cumulative effects of all possible inputs on HCE degradation in each transistor in the circuit in a single run rather than using exhaustive or Monte Carlo simulations. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks. References [1] S. Aur, D. Hocevar, and P. Yang. Hotron - a circuit hot electron effect simulator. Proc. IEEE ICCAD, pages 256259, November 1987. [2] W. J. Hsu, S. M. Gowda, and B. J. Sheu. Vlsi circuit design with built-in reliability using simulation techniques. Proc. IEEE CICC, pages 19.3.1-19.3.4, May 1990. [3] Y. Leblebici and S. M. Kang. An integrated hot-carrier degradation simulator for vlsi reliability analysis. Proc. IEEE ICCAD, pages 400-403, November 1990. [4] M. M. Kuo, K. Seki, P. M. Lee, J. Y. Choi, P. K. Ko, and C. Hu. Simulation of mosfet lifetime under ac hotelectron stress. IEEE Trans. Electron Devices, 35:1004-1011, July 1988. [5] Y. Leblebici, P. C. Li, S. M. Kang, and I. N. Hajj. Hierarchical simulation of hot-carrier induced damages in vlsi circuits. Proc. IEEE CICC, pages 29.3.1-29.3.4, May 1991. [6] Y. H. Shih. Computationally efficient methods for accurate timing and reliability simulation of ultra-large MOS circuits. PhD thesis, University of Illinois at UrbanaChampaign, July 1991. [7] F. Najm, R. Burch, P. Yang, and I. N. Hajj. Probabilistic simulation for reliability analysis of cmos vlsi circuits. IEEE Transactions on CAD, 9:439-450, April 1990. [8] C. Hu, S. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill. Hot-electron-induced mosfet degradation model, monitor and improvement. IEEE Trans. Electron Devices, ED-32:375-384, February 1985. [9] T. C. Ong, K. S. Seki, P. K. Ko, and C. Hu. P-mosfet gate current and device degradation. Proc. IEEE Rel. Phys. Symp., pages 178-182, March 1989. [10] B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M. C. Jeng. Bsim: Berkeley short-channel igfet model for mos transistors. IEEE Journal of Solid-State Circuits, SC-22:558-564, August 1987. [11] Y. Leblebici and S. M. Kang. A one-dimensional mosfet model for simulation of hot-carrier induced device and circuit degradation. Proc. IEEE International Symp. on Circuits and Systems, pages 109-112, May 1990. [12] G. I. Stamoulis. New techniques for probabilistic simulation of VLSI CMOS circuits. Master thesis, University of Illinois at Urbana-Champaign, September 1991.


CRIS : A Test Cultivation Program for Sequential VLSI Circuits Daniel G. Saab Center For Reliable and High Performance Computing, Coordinated Science Laboratory, University of Illinois Urbana, IL Youssef G. Saab Department of Computer Science, University of Missouri Columbia, Missouri Jacob A. Abraham Computer Engineering Research Center, University of Texas at Austin, Austin, TX Abstract This paper discusses a novel approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses hierarchical simulation technique in the analysis to drastically reduce the memory requirement, thus allowing the test generation for large VLSI circuits. The algorithms are at the switch level so that general MOS digital designs can be handled, and both stuck-at and transistor faults are handle accurately. The approach has been implemented in a hierarchical test generation system, CRIS, that runs under UNIX on SPARC workstations. CRIS has been used successfully to generate tests with high fault coverage for large combinational and sequential circuits. References [1] H-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovani-Vicentelli, "Test Generation for Sequential Circuits," IEEE, Transactions on Computer Aided-Design., vol. CAD-7, pp. 1081-1093, Oct. 1988. [2] T. M. Niermann and J. H. Patel, "HITEC: A Test Generation Package for Sequential Circuits," European Design Automation Conference, pp. 214-218, 1991. [3] W.-T. Cheng, "The BACK Algorithm for Sequential Test Generation," International Conference on Computer Aided Design, pp. 214-218, 1991. [4] Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990. [5] J. Galiay et al., "Physical Versus Logic Fault Models in MOS LSI Circuits, Impact on their Testability," Int. Symp. Fault Tolerant Computing, pp. 195-202, 1979.. [6] R. L. Wadsack, "Fault Modeling and Simulation of CMOS and MOS Integrated Circuits," The Bell System Tech. Journal, pp. 1449-1474, June 1978.. [7] Y. M. El-Ziq, "Automatic Test Generation for Stuck-Open Faults in CMOS VLSI," Design Automation Conference, pp. 347-352, June 1981.. [8] M. K. Reddy, S. M. Reddy, and P. Agrawal, "Transistor Level Test Generation for MOS Circuits," Design Automation Conference, pp. 825-828, 1985.. [9] S. Seshu and D. N. Freeman, "The diagnosis of asynchronous sequential switching systems," IRE Transactions on Electronic Computing, vol. EC-11, pp. 459-465, August 1962. [10] K.-T. Cheng and V. D. Agrawal, Unified Methods for VLSI Simulation and Test Generation. Boston, MA: Kluwer Academic Publishers, 1989. [11] D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning. Massachusetts: AddisonWesley, 1989. [12] F. Brglez, D. Bryan, and K. Kozminski, ''Combinational Profiles of Sequential Benchmark Circuits," in Proceedings of the 1989 Int. Symp. on Circuits and Systems, Portland, Oregon, May 1989.

[13] J. P. Cohoon and W. D. Paris, "Genetic Placement," in Proc. of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 422-425, November 1986. [14] F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. of the Int. Test Conf., pp. 785-794, 1985.


Portable Parallel Test Generation for Sequential Circuits Balkrishna Ramkumar Dept. of Electrical & Computer Engg., University of Iowa, Iowa City, Iowa Prithviraj Banerjee Center for Reliable & High-Perf. Computing, University of Illinois, Urbana, IL Abstract We report a new parallel test generation algorithm, ProperTEST, for sequential circuits that is portable across a range of MIMD parallel architectures. It uses prioritized execution to ensure consistent speedups as the number of processors is increased. This consistency is achieved without loss in fault coverage with increase in number of processors. This also enables the use of parallel processing to improve the fault coverage when the execution time is bounded. Results on ISCAS 89 benchmark programs are provided on a shared memory machine, a message passing machine and a network of Sun workstations. ProperTEST was run unchanged on these different architectures. References [1] Fenton, W., Ramkumar, B., Saletore, V.A., Sinha A.B., Kale, L.V. Supporting Machine Independent Programming on Diverse Parallel Architectures. In ICPP, Aug. 1991. [2] Goel, P. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Trans. Comp., C-30:215-222, Mar. 1981. [3] Goldstein, L.H., Thigpen, E.L. SCOAP: Sandia Controllability/Observability Analysis Program. In Proceedings of the 17th DAC, Jun. 1980. [4] Niermann, T. Techniques for Sequential Circuit Automatic Test Generation. PhD thesis, Dept. of Elec. & Comp. Engg., Univ. of Illinois at Urbana-Champaign, Sep. 1990. [5] Ramkumar, B., Banerjee P. ProperCAD: A Portable Object-oriented Parallel Environment for V LSI CAD. In ICCD, Oct. 1992. [6] Saletore, V.A. Machine Independent Parallel Execution of Speculative Computations. PhD thesis, Dept. of Elec. & Comp. Engg., Univ. of Illinois at Urbana-Champaign, 1991.


AUTOMATIC TEST GENERATION FOR LINEAR DIGITAL SYSTEMS WITH BILEVEL SEARCH USING MATRIX TRANSFORM METHODS R. K. Roy,* A. Chatterjee, † J. H. Patel, ‡ J. A. Abraham,§ and M. A. d'Abreu† *C &C Research Labs, NEC USA, 4 Independence Way, Princeton, NJ 08540 † General Electric R&D Center, I River Road, Schenectady, NY 12301 ‡ CRHC, University of Illinois, 1101 W. Springfield, Urbana, IL 61801 § CERC, University of Texas, 2201 Donley Drive, Ste. 395, Austin, TX 78758 Abstract Linear state variable digital systems, commonly implemented in bit-serial architecture using silicon compilers, are difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, and high latency. A novel hierarchical testing approach, based on matrix manipulation and constrained low-level test generation, is reported here. FEAST (Functional Extractor and Sequential Test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. CREST (Constrained Sequential Test generator) operates at the low level description of the individual modules, and generates test sets satisfying constraints imposed by the high-level modules and their interconnection structure. The new approach was found to perform better when compared to automatic test generation at the gate level using existing algorithms for several large circuits. References [1] A. E. Casavant et. al., "A synthesis environment for designing DSP systems," IEEE Design Test Comp., pp. 3544, Apr. 1989. [2] P. B. Denyer and D. Renshaw, VLSI Signal Processing, A bit-Serial Approach. Reading, MA: Addison-Wesley, 1985. [3] R. Jain et. al., "Custom design of a VLSI PCMFDM transmultiplexor from system specification to circuit layout using a computer-aided design system," IEEE J. Solid State Circuits, vol. SC-21, pp. 73-85, Feb. 1986. [4] R. I. Hartley and P. F. Corbett, "A digit-serial silicon compiler," Proc. 25th Design Automation Conf., pp. 646649, 1988. [5] A. F. Murray, P. B. Denyer, and D. Renshaw, "Self-testing in bit-serial VLSI parts: high coverage at low cost," Proc. Intl. Test Conf., pp. 260-268, 1983. [6] S. G. Smith and P. B. Denyer, Serial-Data Computation. Boston, MA: Kluwer Academic Publishers, 1988. [7] N. Kanopoulos and G. T. Mitchell, "Design for testability and self-testing approaches for bit-serial signal processors," IEEE Design and Test Comp., pp. 52-59, May 1984. [8] T. M. Niermann and J. H. Patel, "HITEC: A test generation package for sequential circuits," Proc. European Design Automation Conf., pp. 214-218, 1991. [9] W.-T. Cheng, "The BACK algorithm for sequential test generation," Proc. Intl. Conf. Computer Design, pp. 6669, 1988. [10] C.-T. Chen, Linear System Theory and Design. New York: Holt, Rinehart and Winston, 1970. [11] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York, NY: Computer Science Press, 1990. [12] T. M. Niermann, W.-T. Cheng, and J. H. Patel, "Proofs: A fast memory efficient fault simulator for sequential circuits," Proc. 27th Design Automation Conf., pp. 535-540, 1990. [13] G. H. Golub and C. F. Van Loan, Matrix Computations. Baltimore, MD: Johns Hopkins University Press, 1983. [14] R. K. Roy, "Automatic Test Generation for Bit-serial VLSI Digital Signal Processors," Ph.D. Dissertation, University of Illinois at Urbana-Champaign, Feb. 1992.


AN EFFECTIVE METHODOLOGY FOR FUNCTIONAL PIPELINING Tsing-Fa Lee1, Allen C-H. Wu2, Daniel D. Gajski2 and Youn-Long Lin1 1 Dept. of Computer Science, Tsing Hua University, Taiwan 30043, R.O.C. 2 Dept. of Information and Computer Science, UC Irvine, CA 92717, U.S.A. Abstract We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPP) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations. References [1] R. Cytron, Compiler-time Scheduling and Optimization for Asynchronous Machines, PhD thesis, Univ. of Illinois at Urbana-Champaign, 1984. [2] P. G. Paulin and J. P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's," IEEE Trans. Computer-Aided Design, pp. 661-679, June 1989. [3] C. T. Hwang, Y. C. Hsu and Y. L. Lin, "Scheduling for Functional Pipelining and Loop Folding," Proc. 28th Design Automation Conf., June 1991. [4] S. Y. Kung, H. J. Whitehouse and T. Kailath, VLSI and Modern Signal Processing, Prentice Hall, pp. 258-264, 1985. [5] N. Park and A. C. Parker, "Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications," IEEE Trans. Computer-Aided Design, pp. 356-370, March 1988. [6] K. K. Parhi and D. G. Messerschmitt, "Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding," IEEE Trans. Computers, pp. 178-195, February 1991. [7] R. Potasman, J. Lis, A. Nicolau and D. Gajski, "Percolation Based Synthesis," Proc. 27th Design Automation Conf., pp. 444-449, June 1990. [8] D. J. Mallon and P. B. Denyer, "A New Approach to Pipeline Optimisation," Proc. European Conf. on Design Automation, pp. 83-88, March 1990.

ICCAD92. Pages 234-237

A Scheduling Method by Stepwise Expansion in High-Level Synthesis Hironori Komi, Shoichiro Yamada*, Kunio Fukunaga Department of Electrical Engineering University of Osaka Prefecture Sakai, Osaka 593, JAPAN *Department of Electrical Engineering Osaka City University Osaka 558, JAPAN Abstract This paper proposes a fast heuristic method for the scheduling problem minimizing hardware costs of functional units, registers, and busses on the basis of an integer linear programming (ILP) model. In our method, the total computation time can be much reduced compared to the general ILP method, since we reduce the number of the integer variables which appear in the ILP formulation by introducing a stepwise expansion approach. Results obtained for a practical scheduling problem indicate that the computation time of the proposed method is linear to the number of the control steps, and we can find optimal or near-optimal solutions. References [1] C.T.Hwang, J.H.Lee, and Y.C.Hsu, "A Formal Approach to the Scheduling Problem in High Level Synthesis," IEEE Trans. Computer-Aided Design, pp.464-475, April 1991. [2] C.H.Gebotys, and M.I.Elmasry, "Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis," Proc. 28th ACM/IEEE Design Automation Conference, pp.2-7, 1991. [3] J.H.Lee, Y.C.Hsu, and Y.L.Lin, "A New Integer Linear Programming Formulation for the Scheduling Problem in Data Path Synthesis," Proc. of ICCAD-89, pp.20-23, 1989. [4] S.Y.Kung, H.J.Whitehouse, and T.Kailath, "VLSI and Modern Signal-Processing," Pretice Hall, pp.258-264, 1985. [5] T.Ibaragi and M.Fukushima, "FORTRAN77 Optimization Program," Iwanami-shoten, pp.395-452, 1991.


OPTIMAL SYNTHESIS OF MULTICHIP ARCHITECTURES Catherine H. Gebotys Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario. N2L 3G1 Canada Abstract A global optimization approach to high level synthesis of VLSI multichip architectures is presented in this paper. This research is important for industry since it is well known that these early high level decisions have the greatest impact on the final VLSI implementation. Optimal application-specific architectures are synthesized here to minimize latency given constraints on chip area, I/O pin count and interchip communication delays. A mathematical integer programming (IP) model for simultaneously partitioning, scheduling, and allocating hardware (functional units, I/O pins, and interchip busses) is formulated. By exploiting the problem structure (using polyhedral theory), the size of the search space is decreased and a new variable selection strategy is introduced based on the branch and bound algorithm. Multichip optimal architectures for several examples are synthesized in practical cpu times. Execution times are comparable to previous heuristic approaches, however there are significant improvements in optimal schedules and allocations of multichips. This research breaks new ground by l. simultaneously partitioning, scheduling, and allocating in practical cpu times, 2. guaranteeing globally optimal architectures for multichip systems for a specific objective function, and 3. supporting interchip communication delay, interchip bus allocation, and other complex interface constraints. References 1. C. H.Gebotys, M.I.Elinasry, Optimal VLSI Architectural Synthesis: Area, Performance, Testability, Kluwer,1992. 2. H. El-Rewini, T.G.Lewis, "Scheduling Parallel Program Tasks onto Arbitrary Target Machines", Journal of Parallel and Distributed Computing, 9, 138-153, 1990. 3. K.Kucukcakar, A.C.Parker, "CHOP: A Constraint-Driven System-Level Partitioner", DAC, 514-519,1991. 4. E.D.Lagnese, "Architectural Partitioning for Systems Level Design of Integrated Circuits", CMUCAD-89-27, Carnegie Mellon University, PhD Thesis,1989. 5. R.Gupta,G.DeMicheli,"VULCAN - A System for High-Level Partitioning of Synchronous Digital Circuits", Tech.Rept.CLSTR-91-471,1991. 6. S.Prakash, A.C.Parker, "Synthesis of Application-Specific Multiprocessor Architectures", DAC, 8-13,1991. 7. A.Brooke, D.Kendricke, A.Meeraus, "GAMS/MINOS Users Manual", Scientific Press,1988. 8. G.L.Nemhauser, L.A.Wolsey, Integer and Combinatorial Optimization, Wiley Interscience, 1988. 9. C.H.Gebotys, M.I.Elmasry, "Optimal Synthesis of High-Performance Architectures ", IEEE Journal of Solid State Circuits, 27, 3, 389-397,1992. 10. C-T.Hwang, J-H.Lee, Y-C.Hsu, "A Formal Approach to the Scheduling Problem in High-Level Synthesis ", IEEE Transactions on CAD, 10, 4, 464-475, 1991. 11. R.Gupta, G.DeMicheli, "Partitioning of Functional Models of Synchronous Digital Systems", ICCAD,1990.


Analytic Macromodeling and Simulation of Tightly-Coupled Mixed Analog-Digital Circuits Yu-Hsu Chang, Andrew T. Yang NSF Center for the Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of Washington, Seattle, Washington Abstract We present an approach for accurate macromodeling and efficient simulation of mixed analogdigital circuits with tight feedback. The approach is based on the efficient integration of the analog simulator with an analytic digital macromodel via the mixed A/D circuit partitioning, error and timestep control, and latency checking - schemes. While maintaining accuracy constraints at every timepoint, this approach efficiently decouples the digital processing completely from the iteration-based analog algorithms. The waveform informations of the digital subcircuits are provided at each timepoint by an accurate digital macromodel, which is derived analytically from the technology files. Therefore, advanced CMOS technologies can be incorporated easily. This proposed technique has been integrated into MISIM, a flexible CAE system for mixed A/D verification and rapid technology characterization. Several mixed A/D benchmark circuits have been tested and the results show that MISIM provides accurate mixed A/D simulation capability with a speed advantage of up to three orders of magnitude over SPICE3. References [1] E. L. Acuna, J. P Dervenis, A. J. Pagones, F. L. Yang, and R. A. Saleh, "Simulation techniques for mixed analog/digital circuits", IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 353-363, April 1990. [2] D. Overhauser, I. Hajj, Y.-F. Hsu, "Automatic mixed-mode timing simulation," The Proc. of the International Conference on Computer-Aided Design, pp. 84-87, 1989. [3] M. Rumsey and J. Sackett, "An ASIC methodology for mixed analog-digital simulation," The Proc. of the 26th Design Automation Conference, pp. 618-621, 1989. [4] C. Visweswariah and R. A. Rohrer, "Piecewise Approximate Circuit Simulation," IEEE Trans. on ComputerAided Design, vol. 10, no. 7, July 1991. [5] Y.-H. Shih, "Computationally efficient methods for accurate timing and reliability simulation of ultra-large MOS circuits," Ph.D. dissertation, University of Illinois at Urbana-Champaign, July 1991. [6] Y.-H. Shih and S.M. Kang, "ILLIADS: a new fast MOS timing simulator using direct equation-solving approach," The Proc. of the 28th Design Automation Conference, pp. 20-25,1991. [7] A. T. Yang, J. T. Yao, R. R. Daniels, J. P Harrang, "An integrated approach to circuit modeling and simulation", The Proc. of the 7th International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits, pp.196-197,1991. [8] A. T. Yang, C. H. Chan, J. T. Yao, "Modeling and simulation of high-frequency integrated circuits based on scattering parameters", The Proc. of the 28th Design Automation Conference, pp. 752-757,1991.


Automatic Differentiation in Circuit Simulation and Device Modeling Peter Feldmann, Robert Melville, Shahriar Moinian AT&T Bell Laboratories Abstract Automatic differentiation is introduced as a technique for accurate and reliable computation of partial derivatives in device models used by circuit simulation. First, the requirements for derivative computations in several simulation algorithms are reviewed, then two automatic differentiation methods are discussed. The application of automatic differentiation to circuit simulation and device modeling is demonstrated through several circuit analysis examples. References [1] A. Griewank, ed., "Automatic Differentiation of Algorithms: Theory, Implementation, and Application.", SIAM, 1991. [2] L. B. Rall, "Automatic Differentiation: Techniques and Applications," Lecture Notes in Computer Science No. 120, Springer, 1981. [3] B. Speelpenning, "Compiling fast Partial Derivatives of Functions given by Algorithms," Ph.D. Dissertation (1980), Department of Computer Science, University of Illinois at Urbana Champaign, Urbana, IL 61801. [4] B. W. Char et al. "Maple V Language Reference Manual", Springer-Verlag, 1991. [5] R. C. Melville, P. Feldmann, S. Moinian, "Sframe, a C++ based environment for circuit simulation," Proc. of Int. Conf. on Computer Design, Cambridge, MA, 1992. [6] C. W. Ho, A. E. Ruehli, and P. A. Brennan, "The Modified Nodal Approach to Network Analysis," IEEE Trans. Circuits Syst., vol. CAS-22, pp. 504-509, Jan. 1975. [7] Bank, R.E. and D.J. Rose, "Global Approximate Newton Methods", Numerische Mathematik, 37, 1981, pp. 279295. [8] J.M. Ortega and W. C. Rheinboldt, Iterative Solutions of Nonlinear Equations in Several Variables, New York, NY: Academic Press, 1969. [9] S. W. Director and R. A. Rohrer, "Automated network design - the frequency domain case," IEEE Transactions on Circuit Theory, Vol. CT 16, pp. 330-337, August 1969. [10] Lj. Trajkovic, R. C. Melville, S-C. Fang, "Passivity and No-Gain Properties Establish Global Convergence of a Homotopy Method for DC Operating Points," Proc. IEEE Int. Symp. on Circuits and Systems, New Orleans, LA., May, 1990. [11] Lj. Trajkovic, R. C. Melville, and S. C. Fang, "Finding DC Operating Points of Transistor Circuits Using Homotopy Methods," Proc. IEEE Int. Symp. on Circuits and Systems, Singapore, 1991. [12] Lj. Trajkovic, R. C. Melville, and S. C. Fang, "Improving DC Convergence in a Circuit Simulator Using a Homotopy Method," IEEE Custom Integrated Circuits Conference, San Diego, CA, 1991. [13] C. B. Garcia and W. I. Zangwill, Pathways to Solutions, Fixed Points, and Equilibria, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1981, pp. 1-23. [14] Allgower, E.L. and K. Georg, Numerical Continuation Methods; An Introduction Springer-Verlag, Springer Series in Computational Mathematics, Number 13, 1990. [15] S. L. Richter and R. A. DeCarlo, "Continuation Methods: Theory and Applications," IEEE Trans. Circuits Syst., vol. CAS-30, pp. 347-352, June 1983. [16] L. Watson, S. Billups, and A. Morgan, "ALGORITHM 652 HOMPACK: A Suite of Codes for Globally Convergent Homotopy Algorithms," ACM Transactions of Mathematical Software, vol. 13, no. 3, pp. 281-310, Sep. 1987. [17] Rheinboldt, W. and J. V. Burkhardt, "A Locally Parameterized Continuation Process", ACM Transactions on Mathematical Software, Vol. 9, No. 2, June 1983, pp. 215-235. [18] Brokaw, A.P., "A Simple Three-terminal IC Bandgap Reference," IEEE JSCC, vol. SC-9, pp. 388-393, Dec. 1974. [19] B.W. McNeill, "A High-Frequency Complementary-Bipolar Array for Fast, Analog Circuit", CICC 87 Digest of Technical Papers, pp. 635-638, Mar., 1987.


A Methodology for Improved Circuit Simulation Efficiency Via Topology-Based Variable Accuracy Device Modeling Kimon W. Michaels and Andrzej J. Strojwas Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Abstract We have developed a general and efficient preprocessing algorithm which can increase circuit simulation efficiency. The algorithm identifies significant devices based upon circuit topology. Device model complexity and error tolerances are varied based upon device significance which results in a reduction in the required model evaluation time. Bibliography [1] L. W. Nagel, SPICE2: A Computer Program To Simulate Semiconductor Circuits. Ph.D. thesis, Univ. of California, Berkeley, UCB/ERL M520, May 1975. [2] A. D. Stein, A Digital Transient Simulation Strategy for Integrated Circuits, Ph.D. thesis, Carnegie Mellon Univ., CMUCAD-91-41, May 1991. [3] T. L. Quarles, Analysis of Performance and Convergence Issues for Circuit Simulation. Ph.D. thesis, Univ. of California, Berkeley, UCB/ERL M89/42, April 1989. [4] C. Visweswariah, IBM Corp. Private communication. [5] R. Erwe and N. Tanabe, Efficient simulation of MOS circuits, IEEE Trans. on CAD, vol. 10., pp. 541-544, April 1991. [6] F. A. Lindholm, S. W. Director, and D. L. Bowler, Assessing model adequacy and selecting model complexity in integrated-circuit simulation, IEEE Jour. on Solid-State Circuits, vol. SC-6, pp. 213-222, Aug. 1971. [7] T. Van Nguyen, Transient Sensitivity Computation and Applications, Ph.D. thesis, Carnegie Mellon Univ., CMUCAD-91-40, May 1991. [8] S: Even, Graph Algorithms. New York: Computer Science, 1979. [9] B. J. Sheu, D. L. Scharfetter, P k. Ko, and M.-C. Jeng, BSIM: Berkeley short-channel IGFET model for MOS transistors, IEEE Jour. of Solid-State Circuits, vol. SC22, pp. 558-566, Aug. 1987. [10] H. K. Gummel and H. C. Poon, An integral charge control model of bipolar transistors, The Bell System Technical Journal, pp. 115-120, Jan. 1970.


ETA.: Electrical-Level Timing Analysis Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, and Lawrence T. Pillage The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, TX Abstract A timing analyzer is described which performs timing analysis considering electrical-level details such as input signal slope, gate input distinction, charge sharing, and interconnect, while also taking into account such high-level concerns as path sensitization. The circuit examples given demonstrate the importance of an accurate delay calculation in correctly finding the longest statically sensitizable path. References [1] J. K. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI," IEEE Trans. Computer Aided Design, vol. CAD-4, no. 3, pp. 336-349, Jul. 1985. [2] M. A. Horowitz, Timing Models for Mos Circuits, Ph.D. Thesis, Stanford University, Jan. 1984. [3] L. Pillage and R. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. ComputerAided Design, vol. 9, no. 4, pp. 352-366, Apr. 1990. [4] P. R. O'Brien and T. L. Savarino, "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation," in Proc. of the International Conference on Computer-Aided Design, pp. 512-515, Nov. 1989. [5] N. Gopal, D. P. Neikirk, L. T. Pillage, "Evaluating RC-Interconnect Using Moment-Matching Approximations," in Proc. of the International Conference on Computer-Aided Design, pp. 74-77, Nov. 1991. [6] Ronald A. Rohrer, Hassan Nosrati, and Kenneth W. Heizer, "Quasi-Static Control of Explicit Algorithms for Transient Analysis," IEEE Trans. Computer-Aided Design, vol. CAD-3, no. 3, pp. 226-234, Jul. 1984. [7] H. Shichman, and D. Hodges, "Modeling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuits," IEEE J. Solid-State Circuits, vol. SC-3, no. 3, Sep. 1968, pp. 285-289. [8] Douglas R. Holberg, "Efficient Gate Delay Models for Synthesis and Timing Analysis," Ph.D. Dissertation, University of Texas at Austin, 1992. [9] C. Visweswariah, R. A. Rohrer, "SPECS2: An Integrated Circuit Timing Simulator," in Proc. of the International Conference on Computer-Aided Design, pp. 94-97, Nov. 1987. [10] Basant R. Chawla, Hermann K. Gummel, and Paul Kozak, "MOTIS--An MOS Timing Simulator," IEEE Transactions on Circuits and Systems, vol. CAS-22, no. 12, pp. 901-910, Dec. 1975. [11] Y. H. Kim, "ELOGIC: A Relaxation-Based Switch-Level Simulation Technique," Technical Report M86/2, ERL, Univ. of California, Berkeley, 1986. [12] R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, vol. C-35, no. 8, pp. 677-691, Aug. 1985. [13] Yun-Cheng Ju and Resve A. Saleh, "Incremental Techniques for the Identification of Statically Sensitizable Critical Paths," in Proc. 28th ACM/IEEE Design Automation Conference, pp. 541-546, Jul. 1991. [14] F. Brglez, H. Fujiwara, "A Neutral Netlist of 10 Combinational Circuits," Special Session on ATPG and Fault Simulation, in Proc. IEEE International Symposium Circuit and Systems, Kyoto, Japan, Jun. 1985.


An Optimal Probe Testing Algorithm for the Connectivity Verification of MCM Substrates So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu CSE Department, University of California, San Diego, La Jolla, CA Abstract The k-probe testing methodology is an effective approach to detect open and short faults in MCM substrates. We propose an algorithm which. generates the minimum number of tests for complete open fault coverage. For k equals two, the algorithm is able to reduce the test size by up to 50% comparing with that generated by an ordinary approach. A multi-dimensional traveling salesman problem formulation is devised to optimize probe routes. The approach has been tested on existing substrate testers, and has achieved excellent results. References [1] J.C. Crowell, R.J. Keogh, and J.A. Conti, "Moving Probe Bare Board Tester Offers Unlimited Testing Flexibility," Industrial Electronics Equipment Design, McGraw-Hill, Sep. 1984. [2] S.D. Golladay, N.A. Wagner, J.R. Rudert and R.N. Schmidt, "Electron-Beam Technology for Open/Short Testing of Multi-Chip Substrates," IBM J. Res. Develop. vol. 34, no. 2/3, pp. 250-259, March/May 1990. [3] W. H. Kautz," Testing for Faults in Wiring Networks," IEEE T. on Computers, Vol. c.-23, NO. 4, pp. 358-363 April 1974. [4] S. Kirkpatrick, C. D. Gelatt, Jr, and M. P. Vecchi, "Optimization by Simulated Annealing," Science, vol 220, pp. 671-680, May 13, 1983. [5] S. Lin, "Computer Solutions of the traveling salesman problem," Bell Syst. Tech. J. vol. 44, pp.2245 - 2269, 1965. [6] S. Lin and B. W. Kernighan, "An Effective Heuristic Algorithm for The Traveling Salesman Problem," Operations Research, vol. 21, pp. 498 - 516, 1973. [7] Robert H. Parker, " Bare Die Test," Proceedings IEEE Multi-Chip Module Conference, pp. 24-27, March 1992. [8] L.T. Wang, M. Marhoefer, and E.J. McCluskey, "A SelfTest and Self-Diagnosis Architecture for Boards Using Boundary Scans," Proc., First European Test Conf., Paris France pp. 119-126, April 1989.


E-PROOFS: A CMOS Bridging Fault Simulator Gary S. Greenstein Sunrise Test Systems, Sunnyvale, CA 94086 Janak H. Patel ECE Department University Of Illinois, Urbana-Champaign Urbana, Illinois 61801 Abstract This paper addresses the problem of bridging fault simulation under the conventional voltage testing environment. A new method is proposed to provide electrical-level simulation accuracy, without paying the associated performance penalties. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by only performing electrical-level simulation in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCM0S circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time. References [1] M. Abramovici and P. Menon. "A practical approach to fault simulation and test generation for bridging faults", IEEE Transactions on Computers, pages 658-663, Sept. 1985. [2] J. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, 1988. [3] E. Acuna, J. Devernis, A. Pagones, F. Yang, and R. Saleh. "Simulation techniques for mixed analog/digital circuits," IEEE Journal of Solid-State Circuits, pages 353-363, Apr 1990. [4] G. Choi and R. Iyer. "FOCUS: An experimental environment for fault-sensitivity analysis," To appear in IEEE Transactions on Computers, 1992. [5] J. Ferguson and T. Larrabee. "Test pattern generation for realistic bridge faults in CMOS IC's," In Proceedings of the IEEE International Test Conference, pages 492-499, Sept. 1991. [6] G. S. Greenstein. CMOS Bridging Fault Simulation. Master's thesis, University of Illinois at UrbanaChampaign, 1992. [7] Y.-C. Ju, F. Yang, and R. Saleh. "Mixed-mode incremental simulation and concurrent fault simulation," In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 158-161, Nov. 1990. [8] T. Lee and I. Hajj. "A switch-level matrix approach to transistor-level fault simulation," In Proceedings o f the IEEE International Conference on Computer-Aided Design, pages 554-557, Nov. 1991. [9] T. Niermann. Techniques For Sequential Circuit Automatic Test Generation. PhD thesis, University of Illinois at Urbana-Champaign, 1991. [10] T. Niermann, W. Cheng, and J. Patel. "PROOFS: A fast, memory-efficient sequential circuit fault simulator," IEEE Transactions on Computer-Aided Design, pages 198-207, Feb. 1992. [11] R. Rajsuman, Y. Malaiya, and A. Jayasumana. "Limits of switch level analysis for bridging faults," IEEE Transactions on Computer-Aided Design, pages 807-811, July 1989. [12] T. Storey and W. Maly. "CMOS bridging fault detection," In Proceedings of the IEEE International Test Conference, pages 1123-1132, Sept. 1990.

ICCAD92, Pages 272- 279

On the Generation of Small Dictionaries for Fault Location Irith Pomeranz and Sudhakar M. Reddy Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA Abstract Fault location based on a fault dictionary is considered. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed ' dynamically, without the use of precomputed knowledge, before the overall effort exceeds the effort of computing a dictionary, is studied. Experimental results on ISCAS85 circuits show that for relatively small numbers of diagnoses, a precomputed dictionary is more efficient. A method to derive small dictionaries without losing resolution of modeled faults is then proposed. Methods to compact the resulting dictionary further, using compaction techniques generally applied to fault detection, are then described. Experimental results are presented to demonstrate the effectiveness of the methods presented. Internal observation points to increase the resolution of the test set are also considered. References [1] M. Abramovici, M.A. Breuer and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990. [2] R. E. Tulloss, "Size Optimization of Fault Dictionaries", 1978 Semiconductor Test Conference, 1978, pp. 264265. [3] R. E. Tulloss, "Fault Dictionary Compression: Recognizing when a Fault May Be Unambiguously Represented by a Single Failure Detection", 1980 Test Conf., Nov. 1980, pp. 368-370. [4] J. Richman and K. R. Bowden, "The Modern Fault Dictionary", 1985 Intl. Test Conf., Sept. 1985, pp. 696-702. [5] V. Ratford and P. Keating, "Integrating Guided Probe and Fault Dictionary: An Enhanced Diagnostic Approach", Intl. Test Conf.,1986, pp. 304-311. [6] P. G. Ryan, S. Rawat and W. K. Fuchs, "Two-Stage Fault Location", 1991 Intl. Test Conf., Oct. 1991, pp. 963968. [7] J. Savir and J. P. Roth, "Testing for, and Distinguishing between Failures", 12th Intl. Symp. on Fault-Tolerant Computing, June 1982, pp. 165-172. [8] M. Marzouki, J. Laurent and B. Courtois, "Coupling Electron-Beam Probing with Knowledge-Based Fault Localization", 1991 Intl. Test Conf., Oct. 1991, pp. 238-247. [9] D. S. Ha and V. P. Kumar, "On the Design of High-Yield Reconfigurable PLAs", IEEE Trans. on Computers, April 1990, pp. 470-479. [10] I. Pomeranz, L. N. Reddy and S. M. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits", 1991 Intl. Test Conf., Oct. 1991, pp. 194-203. [11] V. D. Agrawal, "Sampling Techniques for Determining Fault Coverage in LSI Circuits", Journal of Digital Systems, vol. V, pp. 189-202,1981. [12] I. Pomeranz and S. M. Reddy, "On Dictionary-Based Fault Diagnosis in Digital Logic Circuits", Technical report No. 9-5-1991, Elect. & Comput. Eng. Dept., U. of Iowa. [13] I. Pomeranz, S.M. Reddy and R. Tangirala, "On Achieving Zero Aliasing for Modeled Faults", European Conf. on Des. Autom. , March 1992, pp. 291-299.


Efficient Partitioning and Analysis of Digital CMOS-Circuits U. Hubner, H.T. Vierhaus German National Research Center for Computer Science, Institute for System Design Technology, Sankt Augustin, Germany Abstract Considerable work has been done in the area of performance optimization for ATPG algorithms. Whereas the application of high-performance algorithms is often limited to trivial gates as ANDS, ORs, and XORs, the cell libraries of silicon vendors contain more sophisticated structures. As a step towards the automatic test generation for even irregular transistor structures, a library independent algorithm is presented for the partitioning and analysis of switch level CMOS circuits. References [1] Michael Boehner, `LOGEX - An Automatic Logic Extractor from Transistor to Gate Level for CMOS Technology', ACM/IEEE Design Automation Conference 1988, pp 517-522 [2] Michel Dagenais, `Efficient Algorithmic Decomposition of Transistor Groups into Series, Bridge, and Parallel Combinations', IEEE Transactions on Circuits and Systems, Vol. 38, No. 6, June 1991, pp. 569-581 [3] Uwe Glaser, Uwe Hubner and H.T. Vierhaus, 'Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects', Proc. of the International Test Conference 1992 [4] Noriyoshi Itazaki and Kozo Kinoshita, `Test Pattern Generation for Circuits with Tri-State Modules by ZAlgorithm', IEEE Transactions on Computer-Aided Design, Vol. 8, No. 12, December 1989 [5] Kuen-Jong Lee, Rajiv Gupta and Melvin A. Breuer, `A New Method for Assigning Signal Flow Directions to MOS Transistors', International Conference on Computer-Aided Design, November 1990, PP. 492-495 [6] R. E. Miller, `Switching Theory', Vol. I, John Wile y and Sons, New York, 1965, p. 173 [7] Vasant B. Rao and Timothy N. Trick, `Network Partitioning and Ordering for MOS VLSI Circuits', IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 1, January 1987 [8] J.Paul Roth, `Diagnosis Of Automata Failures: A Calculus And A Method', IBM Journal, July 1966


Efficiency Improvements for Force-Directed Scheduling W.F.J. Verhaegh1, P.E.R. Lippens1, E.H.L. Aarts1,2, J.H.M. Korst1, A. van der Werf1, J.L. van Meerbergen1 1 Philips Research Laboratories, Eindhoven, The Netherlands 2 Eindhoven University of Technology, Eindhoven, The Netherlands Abstract Force-directed scheduling, introduced by Paulin and Knight, is a technique which schedules operations under time constraints in order to achieve schedules with a minimum number of resources. The worst case time complexity of the algorithm is cubic in the number of operations. This is due to the computation of the changes in the distribution functions needed for the force calculations. We present an incremental way to compute the changes in the distribution functions, based on gradual time frame reduction. This reduces the time complexity of the algorithm to quadratic in the number of operations, without any loss in effectiveness or generality of the algorithm. Implementations show a substantial CPU-time reduction of forcedirected scheduling, which is illustrated by means of some industrially relevant examples. References [1] R.J. Cloutier and D.E. Thomas. The combination of scheduling, allocation, and mapping in a single algorithm. In Proc. of the 27th DAC, pp. 71-76, 1990. [2] M.R. Garey and D.S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. W.H. Freeman and Company, New York, 1979. [3] T. Kim, J.W.S. Liu, and C.L. Liu. A scheduling algorithm for conditional resource sharing. In Proc. of the ICCAD, pp. 84-87, 1991. [4] S.Y. Kung, H.J. Whitehouse, and T. Kailath. VLSI and Modern Signal Processing, pp. 258-264. Englewood Cliffs, NJ: Prentice Hall, 1985. [5] P.E.R. Lippens, J.L. van Meerbergen, A. van der Werf, W.F.J. Verhaegh, B.T. McSweeney, J.O. Huisken, and O.P. McArdle. PHIDEO: a silicon compiler for high speed algorithms. In Proc. of the EDAC, pp. 436-441, 1991. [6] M.C. McFarland, A.C. Parker, and R. Camposano. The high-level synthesis of digital systems. Proc. of the IEEE, 78(2):301-318, 1990. [7] A. Olah, S.H. Gerez, and S.M. Heemstra de Groot. Scheduling and allocation for the high-level synthesis of DSP algorithms by exploitation of data transfer mobility. In Proc. Computer Systems and Software Engineering (CompEuro), pp. 145-150, 1992. [8] P.G. Paulin. High-Level Synthesis of Digital Circuits using Global Scheduling and Binding Algorithms. PhD thesis, Carleton University, Ottawa, Canada, 1988. [9] P.G. Paulin and J.P. Knight. Force-directed scheduling in automatic data path synthesis. In Proc. of the 24th DAC, pp. 195-202, 1987. [10] P.G. Paulin and J.P. Knight. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. on CAD, 8(6):661-679, 1989. [11] L. Stok and R. van den Born. EASY: multiprocessor architecture optimization. In Proc. of the Int. Workshop Logic and Architecture Synthesis for Silicon Compilers, pp. 313-328, 1988. [12] W.F.J. Verhaegh, E.H.L. Aarts, J.H.M. Korst, and P.E.R. Lippens. Improved force-directed scheduling. In Proc. of the EDAC, pp. 430-435, 1991. [13] P.H.N. de With. Motion-adaptive intraframe transform coding of video signals. Philips Journal of Research 44, pp. 345-364,1989.


Area Optimization of Multi-Functional Processing Units A. van der Werf1, M.J.H. Peek2, E.H.L. Aarts1,2, J.L. Van Meerbergenl , P.E.R. Lippensl, W.F.J. Verhaeghl 1 Philips Research Laboratories, P.O. Box 80000, 5600 JA Eindhoven, The Netherlands 2 Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands Abstract Functions executed by a multifunctional processing unit (PU) correspond to clusters of operations in the specification, which are represented as Signal Flow Graphs (SFGs). Because of high-throughput demands, the operations of each SFG are executed in parallel. Since only one of the SFGs is executed at the same time, operations belonging to different SFGs can be executed on the same operator. In this paper, we concentrate on the most important part of the mapping of several SFGs onto one PU, which is the assignment of the SFGs' operations to the PU's operators, given a number of allocated operators. The problem is to find an operator assignment that minimizes the silicon area that is occupied by the PU's interconnection consisting of multiplexers and wires. Here, we present an approach based on local search algorithms such as iterative improvement and simulated annealing. Although these algorithms are known to be generally applicable, we show that detailed knowledge of the operator assignment problem is required to obtain good results within acceptable CPU time limits for large problem instances. References [1] S.M.C. Borgers, W.A.L. Heijnemans, E. de Niet en P.H.N. de With, "An experimental digital VCR with 40mm drum, single actuator and DCT-based bit-rate reduction", IEEE Transactions on Consumer Electronics, Vol. 34, No. 3, August 1988, pp. 597-605. [2] P.E.R. Lippens, J.L. van Meerbergen, A. van der Werf, W.F.J. Verhaegh, B.T. McSweeney, J.A. Huisken, O.P. McArdle, "PHIDEO: A Silicon Compiler for High Speed Algorithms", in Proceedings of the EDAC 1991, pp. 436-441. [3] Charles E. Leiserson, James B. Saxe, "Retiming Synchronous Circuitry", Algorithmica, Vol. 6, No. 1, 1991, pp. 5-35. [4] M.R. Garey, D.S. Johnson, Computers and Intractability: a Guide to the Theory of NP-Completeness, W.H. Freeman and Co., New York, 1979. [5] M. Yannakakis, "The Analysis of Local Search Problems and their Heuristics", Lecture Notes in Computer Science, No. 415, pp. 298-310. [6] E.H.L. Aarts, J.H.M. Korst, Simulated Annealing and Boltzmann Machines, John Wiley & Sons, Chichester, 1989. [7] P.J.M. van Laarhoven, E.H.L. Aarts, Simulated Annealing: Theory and Applications, Reidel, Dordrecht, 1987. [8] S. Note, F. Catthoor, H. De Man, "Definition and Assignment of Complex Data-Paths Suited for High Throughput Applications", in Proceedings of the ICCAD 1989, pp. 108 [9] N. Park, F.J. Kurdahi, "Module Assignment and Interconnect Sharing in Register-Transfer Synthesis of Pipelined Data Paths", in Proceedings of the ICCAD 1989, pp. 1619. [10] S. Devadas, A.R. Newton, "Algorithms for Hardware Allocation in Data Path Synthesis", IEEE Transactions on Computer Aided Design, Vol. 8, No. 7, July 1989, pp. 768-781. [11] C.-M. Chu, J.M. Rabaey, "Hardware Selection and Clustering in the HYPER Synthesis System", in Proceedings of the EDAC 1992, pp. 176-180. [12] J.W. Greene, K.J. Supowit, "Simulated Annealing without Rejected Moves", IEEE Transactions on ComputerAided Design, Vol. 5, No. 1, January 1986, pp. 221-228.


HYPER-LP: A System for Power Minimization Using Architectural Transformations Anantha P. Chandrakasan*, Miodrag Potkonjak**, Jan Rabaey*, Robert W. Brodersen* *EECS Department, University of California at Berkeley **C & C Research Laboratories, NEC USA, Princeton ABSTRACT The increasing demand for "portable" computing and communication, has elevated power consumption to be the most critical design parameter. An automated high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The sources of power consumption are reviewed and the effects of architectural transformations on the various power components are presented. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives (local and global), and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area. References [1] A. Chandrakasan, S. Sheng, R.W. Brodersen, "Design Considerations for a Future Multimedia Terminal", in Third Generation Wireless Information Network, edited by D. Goodman and S. Nanda, Kluwer Academic Publishers, 1992. [2] A. Chandrakasan, S. Sheng, R. Brodersen, "Low-power CMOS Digital Design", IEEE Journal of Solid-state circuit, pp. 473-484, April 1992. [3] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, MA, 1988. [4] F. Najm, "Transition Density, A Stochastic Measure of Activities in Digital Circuits", DAC, pp. 644-649,1991. [5] A. Ghosh, S. Devadas, K. Keutzer, J. White, "Estimation of Average Switching Activity in Combinational and Sequential Circuits", DAC, pp. 253-259,1992. [6] A. Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen, "An Approach to Power Minimization Using Transformations", IEEE VLSI Signal Processing Workshop, 1992. [7] R. W. Brodersen, (ed.), "Anatomy of a Silicon Compiler", Klewer Academic Publishers, 1992. [8] A. Salz, M. Horowitz, "IRSIM: An Incremental MOS Switch-level Simulator", Proceedings of the 26th ACM/IEEE Design Automation Conference, June 1989, pp. 173-178. [9] M. Potkonjak and J. Rabaey, "Optimizing the Resource Utilization Using Transformations", Proc. IEEE ICCAD Conference, Santa Clara, pp. 88-91, November 1991. [10] J. Rabaey, C. Chu, P Hoang, M. Potkonjak, "Fast Prototyping of Data Path Intensive Architecture", IEEE Design and Test, Vol. 8, No. 2, pp. 40-51,1991. [11] D. Schultz, "The Influence of Hardware Mapping on High-Level Synthesis", M.S. report, U.C. Berkeley, 1992. [12] W.H. Press, B.P. Flannery, S.A. Teukolsky, W.T. Vetterling: "Numerical Recipes in C", Cambridge University Press, 1988.


Maximally Fast and Arbitrarily Fast Implementation of Linear Computations Miodrag Potkonjak C&C Research Laboratories, NEC USA, Princeton, NJ Jan Rabaey Department of EECS, University of California, Berkeley, CA ABSTRACT Linear systems are the most often used type of systems in many engineering and scientific areas. By establishing a relationship between the basic properties of linear computations and several optimizing transformations, it is possible to optimally speed-up linear computations with respect to those transformations while keeping the latency fixed. Furthermore, arbitrarily fast, asymptotically optimal implementations can be obtained by adding retiming and loop unrolling to the transformations set and trading latency for throughput. The proposed techniques have yielded results superior to the best published previously on all benchmark examples. Finally, the presented approach is also applicable to general (non-linear) computations. References [1] AX Aho, J.D. Ullman: "Principles of Compiler Design", Addison-Wesley, Reading, MA, 1977. [2] A. Borodin, I. Munro: "The Computational Complexity of Algebraic and Numeric Problems", American Elsevier Pub, New York, NY, 1975. [3] R. Camposano, R. Walker: "A Survey of high-level synthesis systems", Kluwer, Boston, 1991. [4] A. Fettweis: "Digital Filter Structures Related to Classical Filter Network", Archiv Electronic Ubertragungstechnic, Vol. 25, pp. 7989,1971. [5] C.N. Fischer, R.J. Le Blank: "Crafting a Compiler", The Benjamin/Cummings Publishing Co., Menlo Park, CA, 1985. [6] C.E. Leiserson, J.B. Saxe: "Retiming Synchronous Circuitry", Algorithmica, Vol. 6, pp. 5-35, 1991 [7] D.A. Lobo, B.M. Pangrle: "Redundant Operation Creation: A Scheduling Optimization Technique", 28th ACM/IEEE Design Automation Conference, pp. 775-778, 1991 [8] AX Oppenheim, R.W. Shafer: "Discrete-time Signal Processing", Prentice Hall, Englewood Cliffs, NJ, 1989. [9] M. Potkonjak, J. Rabaey: "Optimizing Resource Utilization Using Transformations", IEEE ICCAD91, pp. 88-91, 1991. [10] M. Potkonjak, J. Rabaey: "Maximally Fast and Arbitrarily Fast Implementation of Linear Computations", NEC Technical Report #92-551004, 1992. [11] H. Trickey: "Flamel: A high-Level Hardware Compiler", IEEE Transaction on CAD, Vol. 6, No. 2, pp. 259269, 1987. [12] J.D. Ullman: "Computational Aspects of VLSI", Computer Science Press, Rockville, MD, 1984.


Lazy-Expansion Symbolic Expression Approximation in SYNAP Steven J. Seda 1, Marc G. R. Degrauwe 2, Wolfgang Fichtner 1 1 Integrated Systems Laboratory, Swiss Federal Institute of Technology (ETH), CH-8092 Zurich, Switzerland 2 Swiss Center for Electronics and Microtechnology (CSEM), Inc. CH-2007 Neuchatel, Switzerland Abstract A lazy-expansion technique for generating small approximate symbolic analog circuit analysis expressions is described. Statistics for this technique as implemented in the symbolic analysis program SYNAP are presented and show a two order-of-magnitude speed improvement (on larger circuits as compared with traditional full-expansion techniques. This technique also allows larger circuits to be analyzed. Also presented are SYNAP'S methods for eliminating pole and zero movement at the design point and for handling variables representing device mismatches. References [1] S. Seda, M. Degrauwe, and W. Fichtner. A symbolic analysis tool for analog circuit design automation. In Proc. IEEE Int'l Conf. on Computer-Aided Design, pp. 488-491, Santa Clara, Nov. 1988. [2] J. Jongsma, C. Meixenberger, B. Goffart, J. Litsios, M. Pierre, S. Seda, G. Di Domenico, P. Deck, L. Menevaut, and M. Degrauwe. An open design tool for analog circuits. In Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 2000-2003, 1991. [3] G. Gielen and W. Sansen. Symbolic Analysis for Automated Design of Analog Integrated Circuits. Kluwer, 1991. [4] F. Fernandez, A. Rodriguez-Vazquez, and J. Huertas. Interactive ac modeling and characterization of analog circuits via symbolic analysis. The Kluwer International Journal on Analog Integrated Circuits and Signal Processing, 1(3):183-208, Nov. 1991. [5] H. Y. Koh, C. H. Sequin, and P. R. Gray. OPASYN: A compiler for CMOS operational amplifiers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(2):113-125, Feb. 1990. [6] R. Sedgewick. Algorithms. Addison-Wesley, 1983. [7] J. Vlach and K. Singhal. Computer Methods for Circuit Analysis and Design. Van Nostrand Reinhold, 1983. [8] M. Degrauwe, O. Nys, E. Dijkstra, J. Rijmenants, S. Bitz, B. Goffart, E. Vittoz, S. Cserveny, C. Meixenberger, G. van der Stappen, and H. Oguey. IDAC: An interactive design tool for analog CMOS circuits. IEEE Journal of Solid-State Circuits, 22(6):1106-1116, Dec. 1987. [9] G. Gielen, P. Wambacq, and W. Sansen. Symbolic approximation strategies and the symbolic analysis of large and nonlinear circuits. In Proc. IEEE Int'l Symposium on Circuits and Systems, pp. 806-809,1991.


Accurate Simplification of Large Symbolic Formulae F. V. Fernández, A. Rodriguez-Vázquez, J. D. Martin and J. L. Huertas Dept. of Analog Circuit Design, Centro Nacional de Microelectrónica, Sevilla, SPAIN Abstract This paper presents simplification techniques for nested symbolic expressions obtained by hierarchical analysis procedures. An algorithm is presented where potential ranges of variation in the symbolic parameter values are considered to perform simplifications. In our approach, the relative significance of each expression at the different nested levels is evaluated prior to performing simplification. Thus, only those terms with little influence on the top expression are eliminated. References [1] S. Seda et al.: "A Symbolic Analysis Tool for Analog Circuit Design Automation", Proc. IEEE ICCAD, pp.488491,1988. [2] G. Gielen, H. Walsharts and W.Sansen: "ISAAC: A Symbolic Simulator for Analog Integrated Circuits" IEEE J. Solid State Circuits, Vol. 24, pp. 1587-1597, Dec. 1989. [3] F. V. Fernández, A. Rodríguez-Vázquez and J. L. Huertas: "Interactive AC Modeling and Characterization of Analog Circuits via Symbolic Analysis", Analog Integrated Circuit and Signal Processing, Vol. l, pp. 183-208, Kluwer, Nov. 1991. [4] A. Konczykowska and M. Bon: "Automated Design Software for Switched-Capacitor IC's with Symbolic Simulator SCYM-BAL", Proc. 25th Design Automation Conf., pp. 363-368,1988. [5] F. V Fernández, A. Rodríguez-Vázquez and J. L. Huertas: "Design and Applications of Symbolic Analysis Tools for Analog Integrated Circuits" Int. Workshop Symbolic Methods, Oct. 1991. [6] G. Gielen and W. Sansen: "Symbolic Analysis for Automated Design of Analog Integrated Circuits". Kluwer,1991. [7] A. Liberatore, S. Manetti and M. Piccirilli: "A Symbolic Approach to the Time-Domain Analysis of Nonlinear or Switched Networks", Proc. Int. Workshop Symbolic Methods, Oct. 1991. [8] G. Wierzba: "Sspice User Manual", Version 1.0, Michigan State University, Feb. 1991. [9] J. Starzyk and A. Konczykowska: "Flowgraph Analysis of Large Electronic Networks", IEEE Trans. on Computer-Aided Design, Vol. CAS-33, No. 3, pp. 301-315, March 1986. [10] M. M. Hassoun and P M. Lin: "A New Network Approach to Symbolic Simulation of Large-Scale Networks", Proc. IEEE Int. Symp. Circuits and Systems, pp. 806-809,1989. [11] F. V. Fernández et al.: "On Simplification Techniques for Symbolic Analysis of Analog Integrated Circuits", Proc. IEEE Int. Symp. Circuits and Systems, pp.1149-1152,1992. [12] E. Sánchez-Sinencio, R.L. Geiger and H. Nevarez-Lozano: "Generation of Continuous-Time Two Integrator Loop OTA Filter Structures", IEEE Trans. on CAS, Vol. 35, pp. 936-946,1988.


Behavioral Simulation for Noise in Mixed-Mode Sampled-Data Systems Edward W. Y Liu, Alberto L. Sangiovanni-Vincentelli Department of EECS, University of California, Berkeley, CA 94720 Abstract In this paper a "direct" noise analysis approach for mixed-mode systems is presented with experimental results compared with results from the traditional Monte Carlo approach. The direct approach computes noise effects by performing arithmetic on moments of distribution functions that characterize electronic noise. One key advantage of this approach is its ability to compute low error probabilities. From experimental results, it is shown that very low order moments, such as second order, are sufficient for a good estimate of noise effects. References [1] E. Liu, A. Sangiovanni-Vincentelli, G. Gielen, and P Gray "A Behavioral Representation for Nyquist Rate A/D Converters", Proc. IEEE ICCAD, November 1991. [2] G. Gielen, E. Liu, A. Sangiovanni-Vincentelli, and P Gray "Analog Behavioral Models for Simulation and Synthesis of Mixed-Signal Systems", Proc. European Design Automation Conference, March 1992. [3] E. Liu, G. Gielen, A. Sangiovanni-Vincentelli, and P Gray "Behavioral Modeling and Simulation of Data Converters", Proc. IEEE International Symposium on Circuits and Systems, May 1992. [4] E. Liu and A. Sangiovanni-Vincentelli, "Behavorial Representation for VCO and Detectors in Phase-Lock Systems", Proc. Custom Integrated Circuits Conference, May 1992. [5] P R. Gray and R. G. Meyer. Analysis and Design of Analog Integrated Circuits, 2nd edition, p. 637, John Wiley & Sons, 1984 [6] L. Nagel, "SPICE2: A Computer Program to Simulate Semiconductor Circuits," Memo No. ERL-M520, Dept. of EECS, U. C. Berkeley, 1975. [7] J. Vandewalle, H. De Man, and J. Rabaey "The adjoint switched capacitor network and its application to frequency, noise and sensitivity analysis", Circuit Theory and Applications, Vol 9, 77-88 (1981), Wiley, 1981 [8] S. Ross, A First Course in Probability, 2nd edition, p. 211. Macmillan Publishing Company, New York, 1984. [9] Y Gendai, Y Komatsu, S. Hirase, M. Kawata "An 8b 504MHz ADC," Proc. IEEE ISSCC, pp. 172-174, Feb. 1991. [10] A. Matsuzawa, S. Nakashima, I. Hidaka, S. Sawada, H. Kodaka, S. Shimada "A 6b 1Ghz Dual-Parallel A/D Converter," Proc. IEEE ISSCC, pp. 174-175, Feb. 1991. [11] S. M. Sze. VLSI Technology, p. 226, McGraw-Hill Book Company, 1983 [12] W. Press, B. Flannery, S. Teukolsky, W. Vetterling Numerical Recipes in C, p. 305, Cambridge University Press, 1989.


An Efficient Multi-View Design Model for Real-Time Interactive Synthesis Allen C-H Wu, Tedd S. Hadley, Daniel D. Gajski Department of Information and Computer Science, University of California, Irvine, CA, Abstract This paper describes an efficient multi-view design model for real-time interactive synthesis of behavioral descriptions into layout data. We present a hybrid data structure which combines all o the design data needed throughout multiple levels of abstraction, including behavior, structure, and floorplan, into a single unified view. We also gave a detailed time and space complexity analysis of the proposed design model, showing that at provides fast updating capabilities for incremental design changes but does not require an exorbitant amount of memory space. These features make this design model ideal for user-controlled synthesis systems that support incremental design and re-design tasks. Furthermore, the simplicity of the data structure allows easy implementation, maintenance, and extendibility. References [1] R.L. Blackburn, D.E. Thomas, P.M. Koenig, "CORAL II: Linking Behavior and Structure in an IC Design System," in Proc. 25th DAC, 1988. [2] C.M. Chu, et. al., "HYPER: An Interactive Synthesis Environment for High Performance Real Time Applications", in Proc. ICCD-89, 1989. [3] D.D. Gajski, et. al., High-Level Synthesis: Introduction to Chip and System Design, Kluwer, 1992. [4] T. Hadley and D.D. Gajski, "A Decision Support Environment for Behavioral Synthesis," Tech. Report 91-17, ICS Dept. U.C. Irvine, 1991. [5] T. Hadley, A C-H Wu, and D.D. Gajski, "An Efficient Multi-View Design Model for Real-Time Interactive Synthesis," Tech. Report 92-35, ICS Dept. U.C. Irvine, 1992. [6] D.W. Knapp and A.C. Parker, "A Unified Representation for Design Information," in Proc. of the 7th CHDL-85, 1985. [7] D.W. Knapp, "An Interactive Tool for Register-Level Structure Optimization," in Proc. 26th DAC, 1989. [8] M.C. McFarland, A.C. Parker, R. Camposano, "Tutorial on High-Level Synthesis," in Proc. 25th DAC, 1988. [9] C. Ramachandran, et. al., "Accurate Lauout Area and Delay Modeling for System Level Design," in Proc. ICCAD, 1992. [10] R.A. Walker et al., "Increasing User Interaction During High-Level Synthesis", in Proc. Micro-92. [11] A. C-H Wu, V. Chaiyakul and D. D. Gajski, " Layout Area Models for High-Level Synthesis," in Proc. ICCAD, 1991. [12] V. Chaiyakul, A. C-H Wu and D. D. Gajski, "Timing Models for High-Level Synthesis," in Proc. EuroDAC, 1992.


Equivalent Design Representations and Transformations for Interactive Scheduling Roger P. Ang, Nikil D. Dutt Department of Information and Computer Science, University of California, Irvine, CA 92717 Abstract High-level synthesis (HLS) requires more designer interaction to better meet the needs of experienced designers. However, attempts to create a highly interactive synthesis process are hampered by incompatibility of various representations used during synthesis. To overcome thin problem, equivalent representations are needed, as well as equivalence-preserving synthesis transformations. We present the Structured Finite State Machine (SFSM) design model for scheduled behavior, show its equivalence to the Control/Data Flow Graph (CDFG) model, and define primitive behavior-preserving transformations for scheduling. We have integrated this model and these transformations into the BIF interactive environment to enable manual rescheduling of a design. References [1] A. Aho, R. Sethi, J. Ullman, Compilers: Principles, Techniques and Tools, Addison-Wesley, 1986. [2] R. Ang and N. Dutt, "Transformations Supporting Interactive Rescheduling for High-Level Synthesis", Tech. Report 92-20, University of California at Irvine, Feb. 1992. [3] J. Bhasker and H. Lee, "An Optimizer for Hardware Synthesis," IEEE Design and Test of Computers, pp. 20-36, Oct. 1990. [4] R. Brayton, et. al., "Multi-level Logic Synthesis," Proceedings of the IEEE, Feb. 1990. [5] R. Camposano, "Behavior-Preserving Transformations for High-Level Synthesis", LNCS 408, pp. 106-128, Springer Verlag, 1990. [6] N. Dutt, J. Cho, and T. Hadley, "A User Interface for VHDL Behavioral Modeling," Proceedings of CHDL, 1991. [7] N. Dutt, T. Hadley and D. Gajski, "An Intermediate Representation for Behavioral Synthesis," Proceedings of DAC, pp.14-19, 1990. [8] D. Gajski, N. Dutt, A. Wu, S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer, 1992. [9] M. Leeser and W. Wolf, "Behavior FSMs for High-Level Verification and Synthesis," ACM International Workshop on Formal Methods in VLSI Design, Jan., 1991. [10] S. Malik et. al, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques.", IEEE Trans. on CAD, pp. 74-84, Jan. 1991. [11] P. Michel, U. Lauther and P. Duzy, The Synthesis Approach to Digital System Design, Kluwer, 1992. [12] A. Orailoglu and D. Gajski, "Flow Graph Representation," Proceedings of DAC, pp. 503-509, 1986. [13] M. Potkonjak and J. Rabaey, "Optimizing Resource Utilization using Transformations", Proceedings of ICCAD, pp. 88-91,1991. [14] L. Ramachandran and D. Gajski, "An Algorithm for Component Selection in Performance Optimized Scheduling," Proceedings of ICCAD, pp. 92-96, 1991. [15] R. Walker and D. Thomas, "Behavioral Level Transformations in the CMU-DA System", Proceedings of DAC, 1983. [16] R. Walker and D. Thomas, "Behavioral Transformation for Algorithmic Level IC Design", IEEE Trans. on CAD, pp. 1115-1128, Oct., 1989.


FICOM.- A Framework for Incremental Consistency Maintenance in MultiRepresentation, Structural VLSI Databases Robert C. Armstrong and Jonathan Allen Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Abstract This paper presents a framework for VLSI design databases which supports fine-grained incremental consistency maintenance between different views of a design. The framework provides for structural views of a design such as logic or circuit schematic, symbolic layout, and physical layout, and supports representation of geometric design rule constraints between design objects. A prototype interactive design system is presented which provides a user interface to three structural view types: gate and circuit schematics, and symbolic layouts. Features of the prototype system are automatic propagation of incremental operations between views and highspeed on-line generation and evaluation of geometric design rule constraints. References [1] Per Andersson. Design representation in Movie. IEEE Transactions on CAD, 10(3):335-45, 1991. [2] Per Andersson and Lars Philipson. Movie - An interactive environment for silicon compilation tools. IEEE Transactions on CAD, 8(6):693-701, 1989. [3] Robert C. Armstrong. A Formal Approach to Incremental Consistency Maintenance in Multirepresentation VLSI Databases. PhD thesis, MIT, 1992. [4] John F. Beetem. Structured Design of Electronic Systems Using Isomorphic Multiple Representations. PhD thesis, Stanford University, 1981. [5] Rajiv Bhateja and Randy H. Katz. VALKYRIE: A validation subsystem of a version server for computer-aided design data. In Proc. 24th ACM/IEEE Design Automation Conference, pages 321-7, 1987. [6] Andrea Casotto, A. Richard Newton, and Alberto Sangiovanni-Vincentelli. Design management based on design traces. In Proc. 27th ACM/IEEE Design Automation Conference, pages 136-41, 1990. [7] James Daniell and Stephen W. Director. An object oriented approach to CAD tool control. IEEE Transactions on CAD, 10(6):698-713, 1991. [8] David S. Harrison, Peter Moore, Rick L. Spickelmier, and A. Richard Newton. Data management and graphics editing in the Berkeley design environment. In Proc. IEEE International Conference on CAD, pages 24-7, 1986. [9] Ernst Siepmann. A data management interface as part of the framework of an integrated VLSI-design system. In Proc. IEEE International Conference on CAD, pages 284-7, 1989. [10] Ernst Siepmann and Gerhard Zimmermann. An object-oriented datamodel for the VLSI design system playout. In Proc. 26th ACM/IEEE Design Automation Conference, pages 814-17, 1989. [11] Mario Silva, David Gedye, Randy Katz, and Richard Newton. Protection and versioning for OCT. In Proc. 26th ACM/IEEE Design Automation Conference, pages 264-9, 1989. [12] P. van der Wolf, G. W. Sloof, and P. Dewilde. Meta data management in the NELSIS CAD framework. In Proc. 27th ACM/IEEE Design Automation Conference, pages 142-49, 1990. [13] Flavio R. Wagner and Arnaldo H. Viegas de Lima. Design version management in the GARDEN framework. In Proc. 28th ACM/IEEE Design Automation Conference, pages 704-10, 1991.


False Loops through Resource Sharing Leon Stok IBM TJ Watson Research Center, Yorktown Heights, NY Abstract This paper describes the effects of false loops caused by resource sharing. When a separate controller and data path are constructed, two types of false loops can be distinguished: the ones that go through the controller and the ones that loop around in the data path. The paper describes a model to detect both types of loops during the resource sharing phase. Based on this model an algorithm is described which prevents false loops in the combinatorial network to be constructed, while maintaining as much freedom as possible for the resource sharing. Experiments show that the loop-,free data-paths do not need more functional units than the ones that contain false loops. References [1] D. Brand and V. Iyengar. Timing analysis using functional analysis. IEEE Trans. on Computers, 37(10):13091314, October 1988. [2] R. Camposano, R. Bergamaschi, C. Haynes, M. Payer, and S. Wu. The IBM High-level Synthesis System, pages 79-104. Kluwer Academic Publishers, 1991. [3] R. Hitchcock Sr., G. Smith, and D. Cheng. Timing analysis of computer hardware. IBM J. Res. Develop., 26(1), January 1982. [4] HLSW. Benchmarks for the Fifth International Workshop on High-level Synthesis. University of California at Irvine, Available by email from [email protected], Irvine, 1991. [5] W. Kautz. The necessity of closed circuit loops in minimal combinatorial circuits. IEEE Transactions on Computers, pages 162-164, February 1970. [6] P. McGeer and R. Brayton. Integrating Functional and Temporal Domains in Logic Design. Kluwer Academic Publishers, Boston, 1991. [7] T. Philips. New algorithms to color graphs and find maximum cliques. Technical report, IBM TJ Watson Research Center, IBM Research Report, Computer Science, Yorktown Heights, 1990. [8] L. Stok. Architectural Synthesis and Optimization of Digital Systems. PhD Thesis, Eindhoven University of Technology, Eindhoven, March 1991. [9] C. Tseng and D. Siewiorek. Automated synthesis of data paths in digital systems. IEEE Trans. on Comp. Aided Design, CAD-5(3):379-395, July 1986. [10] A. Veen. The misconstrued semicolon. PhD Thesis, Eindhoven University of Technology, Eindhoven, 1985.


Timing Analysis in High-Level Synthesis Andreas Kuehlmann, Reinaldo A. Bergamaschi IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y., U.S.A. Abstract This paper presents a comprehensive timing model for behavioral-level `specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same logic synthesis procedure applied after behavioral synthesis. The timing network is built only once for a given behavioral description. Several parameters are used to explore different scheduling possibilities as well as different optimization modes (area, delay, without changing the network. The use of the timing model in conjunction with a path-based scheduling algorithm is presented. Results for several benchmarks attested the accuracy of this approach. References [1] T. M. McWilliams, "Verification of timing constaints on large digital systems," in Proceedings of the 17th ACM/IEEE Design Automation Conference, (Minneapolis), pp. 139-147, ACM/IEEE, June 1980. [2] T. I. Kirkpatrick and N. R. Clark, "PERT as an aid to logic design," IBM Journal of Research and Development, vol. 10, pp. 135-141, March 1966. [3] R. B. Hitchcock, "Timing verification and the timing analysis program," in ACM IEEE Nineteenth Design Automation Conference Proceedings, (Las Vegas, Nevada), ACM/IEEE, June 1982. [4] G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Digest of Technical Papers o f the IEEE International Conference on Computer-Aided Design, pp. 274-277, IEEE, 1987. [5] R. Zahir and W. Fichtner, "Specification of timing constaints for controller synthesis," in International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, ACM/IEEE, August 1990. [6] R. Jain, M. J. Mlinar, and A. C. Parker, "Area-time model for synthesis of non-pipelined designs," in Proceedings of the IEEE International Conference on Computer-Aided Design, IEEE, November 1988. [7] P. G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Transactions on Computer-Aided Design, vol. CAD-8, pp. 661-679, June 1989. [8] F. Brewer and D. Gajski, "Chippe: A system for constaint driven behavioral synthesis," IEEE Transactions on Computer-Aided Design, vol. 9, pp. 681-695, July 1990. [9] S. Note, F. Catthoor, G. Goossens, and H. J. D. Man, "Combined hardware selection and pipelining in highperformance data-path design," IEEE Transactions on Computer-Aided Design, vol. 11, pp. 413-423, April 1992. [10] J. Darringer, D. Brand, J. V. Gerbi, W. Joyner, and L. Trevillyan, "LSS: A system for production logic synthesis," IBM Journal of Research and Development, vol. 28, September 1984. [11] R. Camposano, R. A. Bergamaschi, C. Haynes, M. Payer, and S. M. Wu, "The IBM high-level synthesis system," in High-Level VLSI Synthesis (R. Camposano and W. Wolf, eds. ), pp. 79-104, Kluwer Academic Publishers, 1991. [12] R. A. Bergamaschi, R. Camposano, and M. Payer, "Scheduling under resource constraints and module assignment," INTEGRATION, the VLSI Journal, vol. 12, pp. 1-19, December 1991. [13] R. Camposano, "Path-based scheduling for synthesis," IEEE Transactions on Computer-Aided Design, vol. CAD-10, pp. 85-93, January 1991. [14] R. A. Bergamaschi, "The effects of false paths in high-level synthesis," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, (Santa Clara, California), pp. 80-83, IEEE, November 1991. [15] D. Brand and V. S. Iyengar, "Timing analysis using functional relationships," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 126-129, IEEE, November 1986. [16] A. C. Parker, J. T. Pizarro, and M. Mlinar, "MAHA: A program for datapath synthesis," in Proceedings of the 23rd ACM/IEEE Design Automation Conference, ACM/IEEE, June 1986.


Accurate Layout Area and Delay Modeling for System Level Design C. Ramachandran1, F. J. Kurdahi1, D. D. Gajski2, A. C.-H. Wu2, and V. Chaiyakul2 1 ECE Department 2 ICS Department University of California, Irvine, CA 92717 Abstract We discuss the problem of estimating design quality measures to accurately reflect design tradeoffs and efficiently explore the design space. Specifically, we are interested in predicting the layout area and delay of a given structural RT level design. Clearly, current RT level cost measures are highly simplified and do not reflect the real physical design. In order to establish a more realistic assessment of layout effects, we proposed a new layout model which accurately and efficiently accounts for the effects of wiring and floorplanning on the area and performance layout of RT level designs. Benchmarking has shown that our model is quite accurate. References [1] M. McFarland, "Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral specifications," in Proc. 23rd Design Automation Conf., pp. 474-480, IEEE/ACM, 1986. [2] M. Pedram and B. Preas, "Interconnection length estimation for optimized standard cell layouts," in Proc. ICCAD-89, pp. 390-393, IEEE/ACM, 1989. [3] G. Zimmermann, "A new area and shape function estimation technique for VLSI layouts," in Proc. 25th Design Automation Conf, pp. 60-65, IEEE/ACM, 1988. [4] F. J. Kurdahi and C. Ramachandran, "LAST: A layout area and shape function estimator for high level applications," in Proc. Second European Con. on Design Automation, Feb. 1991. [5] A. C.-H. Wu, V. Chaiyakul, and D. D. Gajski, "Layout-area models for high-level synthesis," in Proc. ICCAD91, pp. 34-37, Sept. 1991. [6] V. Chaiyakul, A. Wu, and D. Gajski, "Timing models for high-level synthesis," in Proc. EuroDAC-92, 1992. [7] D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992. [8] S. Narayan, F. Vahid, and D. Gajski, "System specification and synthesis with the specChart language," in Proc. ICCAD-91, pp. 266-269, 1991. [9] W. K. Luk and A. A. Dean, "Multi-stack optimization for data-path chip (microprocessor) layout," in Proc. 26th DAC, pp.110-115, 1989. [10] F. J. Kurdahi and A. C. Parker, "Techniques for area estimation of VLSI layouts," IEEE Trans. CAD, vol. 8, no. l, pp. 81-92,1989. [11] R. Brayton et al., "Mis: A multiple level logic optimization system," IEEE Trans. CAD, vol. CAD6, pp.10621081, Nov. 1987. [12] S. Devadas et. al, "MUSTANG: State assignment for finite state machines for multi-level logic implementations," in Proc. ICCAD-87, pp. 16-19, 1987. [13] M. Buric and T. Matheson, "Silicon compilation environments," in Proc. IEEE CICC,1985. [14] C. Ramachandran et. al., "RT level layout models for high level synthesis," tech. rep., ECE Department, UC Irvine, 1992. [15] P. Penfield Jr and J. Rubenstein, "Signal delay in RC tree networks," in Proc.18th DAC,1981. [16] P. C. McGeer, On the Interaction of Functional and Timing Behavior of Combinational Logic Circuits. PhD thesis, Dept. of EECS, Univ. of California, Berkeley, 1989. [17] C. Ramachandran and F. J. Kurdahi, "A combined topological and functionality based delay estimation using a layout-driven approach for high level applications," in Proc. Euro-DAC 92, Sept. 1992. (to appear). [18] K. A. Sakallah, T. N. Mudge, and O. A. Olukotun, "Analysis and design of latch-controlled synchronous digital circuits," in Proc. 27th Design Automation Conf, pp. 111- 117, June 1990. [19] S.-Y. Kung, H. J. Whitehouse, and T. Kailath, VLSI and Modern Signal Processing. Prentice Hall, 1985. [20] "Amd 2900 series databook." Advanced Micro Devices.

[21] B. Rouzeyre and G. Sagnes, "Memory area minimization by hierarchical clustering in high-level synthesis," in Fifth International Workshop on High-Level Synthesis, Mar. 1991. [22] R. Jain et. al., "Experience with the ADAM synthesis system," in Proc. 26th DAC, pp. 56-61,1989.


Ravel: Assigned-Delay Compiled-Code Logic Simulation Emily J. Shriver Digital Equipment Corporation Karem A. Sakallah University of Michigan Abstract Ravel is a long-and short path delay-accurate comp led-code logic gate simulator suitable for both the functional and timing verification of multiphase synchronous circuits. It is based on a waveform model of synchronous operation and an associated algebra for combining such waveforms both logically and temporally. This algebra extends the range of compiled-code simulation, which has been limited in the past to static functional verification, so that dynamic signal propagation effects can be captured accurately. For synchronous circuits exhibiting significant event activity per clock cycle, Ravel simulation can be faster than traditional eventdriven simulation with no sacrifice in the delay modeling accuracy. Initial experiments with Ravel on a subset of the ISCAS 89 sequential benchmarks confirm its viability as an alternative to event-driven simulation. References [1] M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990. [2] E. Ulrich, "Exclusive Simulation of Activity in Digital Networks," in Comm. of the ACM, Vol. 13, February 1969, pp. 102-110. [3] M. Chiang and R. Palkovic, "LCC Simulators Speed Development of Synchronous Hardware," in Computer Design, March 1986, pp. 87-92. [4] L. Wang, N. Hoover, E. Porter, and J. Zasio, "SSIM: A Software Levelized Compiled-Code Simulator," in Proc. of the 24th DAC,1987, pp. 2-8. [5] E. Ulrich, M. Kearney, J. Tellier, and S. Demba, "Design Verification for Very Large Digital Networks Based on Concurrent Simulation and Clock Suppression," in Proc. of ICCAD, November 1983, pp. 277-280. [6] R. Razdan, G. Bischoff, and E. Ulrich, "Exploitation of Periodicity in Logic Simulation of Synchronous Circuits," in Proc. of ICCAD, November 1990, pp. 62-65. [7] K. Sakallah, T. Mudge and 0. Olukotun, "checkTc and minTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits," in Proc. of ICCAD, November 1990, pp. 552-555. [8] F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits", ISCAS89 Proceedings, 1989. [9] T. Burks, K. Sakallah, and T. Mudge, "Multiphase Retiming Using minTc," in Proc. of TAU92, Princeton University, March 1992. [10] Verilog User's Manual, Cadence Design Systems.


Parallel Logic and Fault Simulation Algorithms for Shared Memory Vector Machines Abdulla Bataineh Cray Research Inc. Eagan, MN 55121 Fusun Özgüner Dept. of Electrical Eng. The Ohio State University Columbus, OH 43210 Imre Szauter AT&T Bell Laboratories Columbus, OH 43213 Abstract In this paper, we present algorithms for logic and fault simulation, developed and implemented on the Cray Y-MP supercomputer, a general purpose shared-memory parallel machine with vector processors. The parallel-and-vector version of the event-driven logic simulation algorithm achieves a speedup of 52 on the Cray Y-MP with 8 processors, with a maximum performance of about 2 million events per second. These results are comparable to the performance of hardware simulation engines and can be implemented on other parallel machines without major modifications. The second algorithm is a parallel and vector version of the parallel fault simulation algorithm. Experimental results on benchmark circuits [1] show that very high evaluation rates (20 to 32x 109 evaluations/s.) can be achieved. Speedup factors of 45 to 69 are observed between the scalar and the parallel-and-vector execution of the fault simulator. References [1] F. Brglez, and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proceedings of IEEE Int. Symp. Circuits Syst.; Special Session on ATPG and Fault Simulation , Jun. 1985. [2] R. Daoud, and F. Ozguner, "Highly vectorizable fault simulation on the Cray X-MP supercomputer," IEEE Trans. on Computer-Aided Design, Vol. 8, pp. 1362-1365, Dec. 1989. [3] M. Denneau, "The Yorktown simulation engine," Proceedings of the 19th DAC, pp. 58-51, Jun. 1982. [4] D. L. Greer, "The quick simulator benchmark ," VLSI Systems Design , pp. 2-7, Nov. 1987. [5] N. Ishiura, H. Yasuura, and S. Yajima, "Highspeed logic simulation on vector processors ," IEEE Trans. on Computer-Aided Design, Vol. Cad-6, pp. 305-320, May. 1987. [6] Y. Levendel, and P. R. Menon, "Fault simulation," Fault-Tolerant Computing: Theory and Techniques (D. K. Pradhan, ed.), pp. 184-264, Prentice-Hall, 1986. [7] F. Özgüner, C.Aykanat, and O. Khalid, "Logic fault simulation on a vector hypercube multiprocessor," Proceedings of The Third Conference on Hypercube Concurrent Computers and Applications, pp. 1108-1116, Jan. 1988. [8] S. Takasaki, F. Hirose, and A. Yamada, "Logic simulation engines in Japan," IEEE Design and Test of Computers , Vol. 6, pp. 40-49, Oct. 1989.


Reconfigurable Machine and Its Application to Logic Diagnosis Naoaki Suganuma*, Yukihiro Murata**, Satoru Nagata**, Shinichi Nagata* *, Masahiro Tomita*, and Kotaro Hirano* *The Graduate School of Science and Technology, Kobe University **Faculty of Engineering, Kobe University 1-1, Rokkodai, Nada, Kobe 657, Japan Abstract In this paper, we present a Reconfigurable Machine (RM). Its highly flexible architecture combining FPGA's with RAM's supports a wide range of applications. Since its "gate-level programmability" allows us to implement various kinds of parallel processing techniques, RM provides a performance comparable to existing "special-purpose" engines. A Reconfigurable Machine Prototype (RMP) has been built as the first prototype incorporating five FPGA's and four SRAM memory banks. RMP has been applied to logic diagnosis and logic simulator. The concept of RM may be the best solution to the trade-offs between general-purpose machines and special-purpose ones. RM will be a hardware platform accelerating a wide range of applications, also offering an interesting problem in high- level synthesis. References [1] P. Agrawal, W. J. Dally, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar, and R. Tutundjian, "MARS: A Multiprocessor-Based Programmable Accelerator," IEEE Design and Test of Computers, vol.4, no.5. pp.29-36,1987. [2] T. Blank, "A Survey of Hardware Accelerators Used in Computer-Aided Design," IEEE Design and Test of Computers, vol. 1, no. 3. pp.21-39,1984. [3] M. Sato, K. Kubota, and T. Ohtsuki, "A Hardware Implementation of Gridless Routing Based on Content Addressable Memory," Proc. 27th ACM/IEEE Design Automation Conference, pp. 646-649, 1990. [4] K. Subramanian and M. R. Zargham, "Distributed and Parallel Demand Driven Logic Simulation," Proc. 27th ACM/IEEE Design Automation Conference, pp.485-490, 1990. [5] K. Y. Tham, "Parallel Processing for CAD Applications," IEEE Design and Test of Computers, vol.4, no.5. pp.13-17, 1987. [6] "Programmable Gate Array User's Guide," Xilinx Inc., 1989. [7] R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Logic Synthesis for Programmable Gate Arrays," Proc. 27th ACM/ IEEE Design Automation Conference, pp.620-625, 1990. [8] "MARS II -- A Second-Generation Logic Emulation System for Validating VLSI Designs in the End Product," PiE Design Systems, Inc., 1991. [9] M. Tomita, H. Jiang, T. Yamamoto, Y. Hayashi "An Algorithm for Locating Logic Design Errors," ICCAD-90, pp.468- 471, 1990. [10] F. Brglez, H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translation in FORTRAN," Special Session on ATPG and Fault Simulation, Proc. ISCAS'85, 1985. [11] N. Suganuma, M. Tomita, K. Hirano, "A Compact Simulation Engine with Flexible Logic Model Expansion," IEEE International Conf. on Systems Engineering, 1992. [12] "The XC4000 Data Book," Xilinx, Inc., 1991.


A Logic Simulation Engine Based on a Modified Data Flow Architecture A.Mahmood*, W.I. Baker*, J. Herath** and A. Jayasumana*** *Washington State University at Tri-Cities, Richland, WA 99352 * * Drexel University, Philadelphia, PA 19104 *** Colorado State University, Fort Collins, CO 80523 ABSTRACT: Logic simulation contains a high degree of dynamic parallelism which can be exploited by a data flow architecture. This paper first develops an optimum application-specific data flow architecture for accelerating the standard event driven logic simulation. In the second part, a new conservative distributed simulation algorithm is developed which minimizes the use of NULL messages. A pseudo-dynamic data flow architecture is then developed to implement this distributed algorithm efficiently. Finally, a comparison of the standard event driven algorithm based data flow accelerator is made to the distributed simulation algorithm based accelerator on several benchmark circuits. It is shown that the distributed simulation algorithm on the specialized data flow accelerator outperforms the standard event driven algorithm based data flow accelerator by a factor of three in most cases. References [1] Hwang, K., and F. A. Briggs, "Computer Architecture and Parallel Processing," McGraw-Hill, 1984, pp. 732763. [2] Siegel, S., and M. E. Kaszynski, "The Design of a Logic Simulation Accelerator," VLSI Systems Design, Oct. 1985, pp. 76-80. [3] Catlin, G. and B. Paseman, "Hardware Acceleration of Logic Simulation Using a Data Flow Architecture," Proc. of the ICCD," 1985. [4] Denneau, M., "The Yorktown Simulation Engine," Proc. of the 19th DAC, 1982. [5] Takasaki, S., et al., "HAL H: A Mixed Level Hardware Logic Simulation System," Proc. of the 23rd ACM/IEEE DAC, 1986, pp. 581-587. [6] Saitoh, M., "Logic Simulation System Using Simulation Processor (SP)," Proc. of the 25th ACM/IEEE DAC, 1988, pp. 225-230. [7] Agrawal, P., "Architecture and Design of the MARS Hardware Accelerator," Proc. of the 24th ACM/IEEE DAC," 1987, pp. 101-107. [8] Blank, T., "A Survey of Hardware Accelerators Used in CAD," IEEE Design and Test, Aug. 1984. [9] Goering, R., "Simulation Accelerators Address Throughput Issues," Computer Design, March 15, 1988. [10] Chandy, K. M., and J. Misra, "Distributed Simulation: A Case Study in Design and Verification of Distributed Programs," IEEE Transactions on Software Engineering, vol. SE-5, no. 5, September, 1979, pp. 440-452. [11] Jefferson, D. R., "Virtual Time," ACM Transactions on Programming Languages and Systems," vol. 7, no. 3, July 1985, pp. 404-425.


Maze Router Without A Grid Map Jiri Soukup Code Farms Inc., Richmond, Ont., KOA 2ZO, Canada Abstract Maze routers provide powerful and flexible routing algorithms, but require storage of information for every routing grid and layer. With the advance of manufacturing technology, the number of these grids is often so large that routing programs either run out of memory or become very slow due to excessive paging. This paper presents a new data organization which, with certain modifications to the algorithm, reduces and possibly eliminates the entire grid map. The router has been coded with a special data structure library. References [1] Lee C.Y.: An algorithm for path connections..., IRE Trans. Electron.Comput., pp.346-365, Sept. 1961. [2] Rubin F.: The Lee..., 1974 IEEE T.Com., C-23, pp.907-914. [3] Soukup J.: Circuit Layout, Proc.of IEEE, Vol.69, No.10. [4] Soukup J.: Organized C, A unified method...., 27-th ACM/IEEE Design Automation Conference, pp.425-430, 1990. [5] Royle et al: Geometrical compaction..., 1987 DAC, pp. 140-4. [6] Hightower D.: A solution..., 1969 DA Workshop.


Detailed Layer Assignment for MCM Routing M. Sriram and S.M. Kang Beckman Institute and Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign Abstract A new routing environment model, called the k-MCM model, is developed to take into account the unique features of a multilayer MCM, such as the availability of "segmented vias", and the presence of two "active" or terminal-bearing layers. A detailed layer assignment problem is formulated on the k-MCM model. A fast heuristic algorithm for the layer assignment problem is proposed. and experimental results on twelve test examples with net counts up to 842 are presented. References [1] A. Aggarwal, M. Klawe and P. Shor, "Multilayer grid embeddings for VLSI," Algorithmica, 6(1), pp. 129-151, 1991. [2] J.M. Ho, M. Sarrafzadeh, G. Vijayan and C.K. Wong, "Layer assignment for multichip modules," IEEE Trans. CAD, CAD-9(12), pp. 1272-1277, Dec. 1990. [3] M. Sriram and S.M. Kang, "A new layer assignment approach for MCMs," Beckman Institute Technical Report UIUC-BI-VLSI-92-O1, University of Illinois, Urbana, March 1992.


A Wire-Length Minimization Algorithm For Single-Layer Layouts De-Sheng Chen and Majid Sarrafzadeh Department of EECS, Northwestern University Evanston IL 60208 Abstract Consider a Steiner tree S interconnecting a set N of terminals. Minimizing length of S can be shown to be equivalent to the traditional (NP-hard) Steiner tree problem. We present an exact polynomial-time algorithm for minimizing length of S when types of operations on S is limited we call these operations topology preserving transformations (TPT). Based on the notion of TPT, an exact algorithm for minimizing the total length of a single-layer layout involving a set of multi-terminal nets and a collection of obstacles is proposed. The proposed algorithm has been used to: • Find a minimum length single-layer layout. The algorithm has been applied to multi-chip modules (MCMs). Within each layer, on the average 10.9% saving in length has been obtained. • Find a Steiner tree interconnecting a net N of terminals. The idea is to find a minimum spanning tree T of N. Then, generate K Steiner trees by randomly flipping edges of T to both its upper- and lower-L-shaped configurations. Then, topology preserving transformation is applied to each Steiner tree. The best of them is selected as the final Steiner tree. On the average, 9.4% improvement over the MST length has been reported. References [CRS] J. P. Cohoon, D. S. Richards and J. S. Salowe, "An Optimal Steiner Tree Algorithm for a Net Whose Terminals lies on the Perimeter of a Rectangle", IEEE Transactions on Computer-Aided Design, Vol. 9, CAD9, No. 4, April 1990, pp. 398-407. [GJ] M. R. Garey and D. S. Johnson, "The Rectilinear Steiner Tree Problem is NP-Complete", SIAM Journal of Applied Mathematics, Vol. 32, No. 4, 1977, pp. 177-182. [H2] F. K. Hwang, "On Steiner minimal trees with rectilinear distance", SIAM J. Appl. Math., vol. 30, no. 1, pp. 104114, 1976. [HSS] J. M. Ho, M. Sarrafzadeh and A. Suzuki, "An Exact Algorithm For Single-Layer Wire-Length Minimization", Proceedings of IEEE International Conference of Computer Aided Design, 1990, pp. 424427. [HVW] N. Hasan, G. Vijayan, and C. K. Wong, "A Neighborhood Improvement Algorithm for Rectilinear Steiner Trees," Proceedings of ISCAS, 1990, pp. 2869-2872. [KR] A. Kahng and G. Robins, "A New Class of Iterative Steiner Tree Heuristics with Good Performance", IEEE transactions on Computer-Aided Design, Vol. 11, No. 7, July 1992, pp. 893-902. [LS] K. F. Liao and M. Sarrafzadeh, "Boundary Single-Layer Routing with Movable Terminals", IEEE transactions on Computer-Aided Design, No. 10, November 1991, pp.1382-1391. [MT] M. Marek-Sadowska and T. T.-K. Tarng, "Single-layer Routing for VLSI : Analysis and Algorithms", IEEE Transactions on Computer-Aided Design, Vol. 2, CAD2, No. 4, October 1983, pp. 246-259. [R1] D. Richards, "Complexity of Single-Layer Routing", IEEE Transactions on Computers, Vol. C-33, No. 3, March 1984, pp. 286-288. [SL*] M. Schlag, F. Luccio, P. Maestrini, D. T. Lee and C. K. Wong, "A Visibility Problem in VLSI Layout Compaction", (F. P. Preparata editor), In Advance in Computing Research (VLSI Theory), 1984, Vol. 2, pp. 259282.


System-level Routing of Mixed-Signal ASICs in WREN Sujoy Mitra, Sudip K. Nag, Rob A. Rutenbar and L. Richard Carley Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania 15213 Abstract This paper presents new techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal ASIC. We combine a comparatively simple geometric model of the problem with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. Experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets. References [1] H. H. Chen & E. Kuh, "Glitter: A Gridless Variable Width Channel Router," IEEE Trans. CAD, vol. CAD-5, no. 4, pp. 459-465, Oct. 1986. [2] U. Chowdhury & A. Sangiovanni-Vincentelli, "Constraint Generation for Routing Analog Circuits," Proc. DAC. pp. 561-566, June 1990. [3] U. Chowdhury and A. Sangiovanni-Vincentelli, "Constraint Based Channel Routing for Analog and Analog/Digital Circuits" Proc. IEEE ICCAD, pp. 198-201, Nov 1990. [4] J. M. Cohn, et al., "KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing," IEEE JSSC, vol. 26, no. 3, March, 1991. [5] P. Groeneveld, "Wire Ordering for Detailed Routing," IEEE Design & Test of Computers, pp. 6-17, Dec. 1989. [6] R. S. Gyurcsik and J. C. Jeen, "A Generalized Approach to Routing Mixed Analog and Digital Signal Nets in a Channel," IEEE JSSC, vol. CAD-24, no. 2, pp. 436-442, April 1989. [7] C. D. Kimble, et al., "Analog Autorouted VLSI," Proc. IEEE CICC., June, 1985. [8] H. Kimura, et al., "An Automatic Routing Scheme for General Cell LSI," IEEE Trans. CAD, vol. 2, pp. 285292, Oct. 1983. [9] E. S. Ochotta, et al, "Equation-Free Synthesis of High Performance Linear Analog Circuits," Proc. 1992 Brown/MPT Conference on Advanced VLSI, The MIT Press. [10] J. Rijmenants, et al, "ILAC: An Automated Layout tool for Analog CMOS Circuits," IEEE JSSC, pp. 417-425, vol. 24, no. 2, April 1989. [11] I. Harada, H. Kitazawa, and T. Kaneko, "A Routing System for Mixed A/D Standard Cell LSI's," Proc. IEEE ICCAD, pp.378-381,1990. [12] J. M Cohn, D. J. Garrod, R. A. Rutenbar and L. R. Carley, "Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM H, " Proc. IEEE ICCAD, pp.394-397,1991. [13] C. Sechen, "Placement and Global Routing of Macro/Custom Cell Integrated Circuits using Simulated Annealing", Proc. 25th ACM/IEEE DAC, pp. 73-80, June 1988. [14] T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout, Wiley-Taubner,1990. [15] E. Lawler, Combinatorial Optimization: Networks and Matroids, Holt, Rinehart, and Winston,1976. [16] D. Chen and C. Sechen, "Mickey: A Macro Cell Global Router," Proc. SRC TECHCON '90, pp. 241244,1990. [17] H. W. Leong, D. F. Wong and C. L. Liu, "A Simulated Annealing Channel Router," Proc. IEEE ICCAD,1985, pp. 226-228. [18] M. P Vecchi and S. Kirkpatrick, "Global Wiring by Simulated Annealing," IEEE Trans. Computer-Aided Design, vol CAD-2, No. 4, pp. 215-222, Oct 1983.


On Average Power Dissipation, and Random Pattern Testability of CMOS Combinational Logic Networks Amelia Shen*, Abhijit Ghosh**, Srinivas Devadas*, Kurt Keutzer*** *Massachusetts Institute of Technology, Cambridge, MA **Mitsubishi Electric Research Laboratories, Sunnyvale, CA ***Synopsis, Mountain View, CA

Abstract We explore the implications of the observation that the probability of the occurrence of a transition on a wire of a circuit affects both the average power dissipation and the random pattern testability of a circuit. We show that restructuring a logic circuit can significantly affect its average power dissipation. We present various methods for the synthesis of combinational logic networks, and show the effect of different algorithms on the power dissipation of the circuit. We also focus on the dual problem of improving the random pattern testability of logic circuits. We show that modifying the signal probabilities can significantly affect the random pattern testability of a circuit. References [1] P. H. Bardell, W. H. McAnney, and J. Savir. Built-In Test for VLSI. Pseudorandom Techniques. John Wiley and Sons, New York, New York, 1987. [2] K. Bartlett, R. Brayton, G. Hachtel, R. Jacoby, C. Morrison, R. Rudell, A. SangiovanniVincentelli, and A. Wang. Multi-level Logic Minimization Using Implicit Don't Cares. In IEEE Transactions on Computer-Aided Design, pages 723-740, June 1988. [3] R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984. [4] R. K. Brayton, R. L. Rudell, A. SangiovanniVincentelli, and A. Wang. MIS: A Multiple-Level Logic Optimization System. In IEEE Transactions on Computer-Aided Design, pages 1062-1081, Nov. 1987. [5] A. Chandrakasan, T. Sheng, and R. W. Brodersen. Low Power CMOS Digital Design. In Journal of Solid State Circuits, pages 473-484, Apr. 1992. [6] O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Using Boolean Functional Vectors. In IMEC-IFIP Int'l Workshop on Applied Formal Methods for Correct VLSI Design, pages 111-128, Nov. 1989. [7] S. Devadas and K. Keutzer. A Unified Approach to the Synthesis of Fully Testable Sequential Machines. In IEEE Transactions on Computer-Aided Design, pages 39-50, Jan. 1991. [8] D. Bostick et. al. The Boulder Optimal Logic Design System. In Proceedings of the Int'l Conference on Computer-Aided Design, pages 62-65, Nov. 1987. [9] A. Ghosh, S. Devadas, K. Keutzer, and J. White. Estimation of Average Switching Activity in Combinational and Sequential Circuits. In Proceedings o f the 29th Design Automation Conference, June 1992. [10] L. Glasser and D. Dobberpuhl. The Design and Analysis o f VLSI Circuits. Addison-Wesley, 1985. [11] J. Hayes and A. Friedman. Test point placement to simplify fault detection. In Proceedings of the Fault Tolerant Symposium, pages 73-78, 1974. [12] V. S. Iyengar and D. Brand. Synthesis of PseudoRandom Pattern Testable Designs. In Proceedings of the International Test Conference, pages 501-508, Sept. 1989. [13] F. Najm. Transition Density, A Stochastic Measure of Activity in Digital Circuits. In Proceedings of the 28 th Design Automation Conference, pages 644-649, June 1991. Extended version submitted to IEEE Transactions on CAD. [14] H. Savoj and R. Brayton. Observability relations and observability don't-cares. In Proceedings of the International Conference on Computer-Aided Design, pages 518-521, Nov. 1991. [15] H. Savoj, R. Brayton, and H. Touati. Extracting local don't-cares for network optimization. In Proceedings of the International Conference on Computer-Aided Design, pages 514-517, Nov. 1991.

[16] K. J. Singh, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Timing Optimization of Combinational Logic. In Proceedings of the International Conference on Computer-Aided Design, pages 282-285, Nov. 1988. [17] T. W. Williams, W. Underwood, and M. R. Mercer. The Interdependence Between DelayOptimization of Synthesized Networks and Testing. In Proceedings of 28th Design Automation Conference, pages 87-92, June 1991.


Efficient Boolean Function Matching Jerry R. Burch, David E. Long School of Computer Science, Carnegie Mellon University Abstract We propose efficient new algorithms for performing the matching step in technology mapping. Our main result is an algorithm for matching under input negations that takes time polynomial in the size of the BDDs representing the functions to be matched. This algorithm is the basis for efficient methods for matching under permutations, bridging and constant inputs. We implemented a simple mapper based on our algorithms, and tested it on a suite of combinational circuits. Using the Actel type 1 mother cell, our mapper required an average of 8.5% fewer cells than mispga. When integrated into a more sophisticated technology mapper, we believe our matching algorithms could provide even better performance. References [1] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proc. 27th DAC, 1990. [2] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput., C-35(8), 1986. [3] E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Technology mapping in MIS. In Proc. ICCAD, 1987. [4] S. Ercolani and G. De Micheh. Technology mapping for electrically programmable gate arrays. In Proc. 28th DAC, 1991. [5] K. Keutzer. DAGON: Technology binding and local optimization by DAG matching. In Proc. 24th DAC, 1987. [6] F. Mailhot and G. De Micheli. Technology mapping using boolean matching and don't care sets. In Proc. European Design Automation Conf., 1990. [7] R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. Logic synthesis for programmable gate arrays. In Proc. 27th DAC, 1990. [8] S. Muroga. Threshold Logic and its Applications. Wiley-Interscience, 1971. [9] H. Savoj, H.-Y. Wang, and R. K. Brayton. Improved scripts in MIS-II for logic minimization of combinational circuits. In Proc. Int. Workshop on Logic Synthesis, 1991.


ProperSYN: A Portable Parallel Algorithm for Logic Synthesis Kaushik De1, Balkrishna Ramkumar2 , Prithviraj Banerjee1 1 Center for Reliable & High-Perf. Computing, Coordinated Science Laboratory, University of Illinois, Urbana, IL 61801 2 Dept. of Electrical & Computer Engg, University of Iowa, Iowa City, IA 52242 Abstract Parallel processing is fast becoming an attractive solution to reduce the computation time of CAD applications. Much of the work in parallel algorithms for CAD reported to date, however, suffers from a major limitation. The parallel algorithms proposed for the CAD applications are designed with a specific underlying parallel architecture in mind. We have developed a portable parallel algorithm based on the Transduction method [1], called ProperSYN. The same algorithm runs on a variety of parallel machines. Experimental results on various parallel machines are presented. References [1] X. Xiang, Multilevel Logic Network Synthesis Systems, SYLON-XTRANS. PhD thesis, Univ. of Illinois, 1990. [2] R. Brayton, R. Ruddel, A. Sangiovanni-Vincentelli, and A. Wang, "MIS: A Multiple-level Logic Optimization System," IEEE Transactions on Computer-Aided Design, pp. 1062-1081, November 1987. [3] R. Galivanche and S. M. Reddy, "A Parallel PLA Minimization Program," Design Automation Conference, pp. 600-607,1987. [4] H. T. Ma, S. Devadas, and A. S. Vincentelli, "Logic Verification Algorithms and their Parallel Implementations," 24th DAC 1987. [5] C.-F. Lim, "Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method," Master's thesis, Univ. of Illinois, 1991. [6] L. V. Kale, "The Chare Kernel Parallel Programming System," International Conference on Parallel Processing, August 1990. [7] B. Ramkumar and P. Banerjee, "ProperCAD: A Portable Object-oriented Parallel Environment for VLSI CAD," To appear in International Conference in Computer Design, 1992. [8] K. De, B. Ramkumar, and P. Banerjee, "A Portable Parallel Algorithm for Logic Synthesis using Transduction," submitted to IEEE Transactions of CAD, 1992. [9] H. Savoj, H.-Y. Wang, and R. K. Brayton, "Improved Scripts in MIS-II for Logic Minimization of Combinational Circuits," International Workshop on Logic Synthesis, 1991.


A New Algorithm for the Binate Covering Problem and its Application to the Minimization of Boolean Relations Seh-Woong Jeong, Fabio Somenzi Department of Electrical and Computer Engineering, University of Colorado at Boulder Abstract The Binate Covering Problem (BCP) is the problem of finding a minimum cost assignment to variables that is a solution of a boolean equation f = 1. It is a generalization of the set covering (or unate covering) problem, where f is positive unate, and is generally given as a table with rows corresponding to the set elements and the columns corresponding to the subsets. Previous methods have considered the case when f is given as a product-of-sum formula or as a binary decision diagram (BDD). In this paper we present a new branch-and-bound algorithm for the BCP, that assumes f is expressed as the conjunction of multiple BDD's. The BCP solver we have implemented can be applied to several problems, including exact minimization of boolean relations, for which we present results. We have been able to solve large, difficult problems (up to 4692 variables) which could not be solved by the product of sum-based method. References [1] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of the 87th Design Automation Conference, pages 40-45, June 1990. [2] R. K. Brayton and F. Somenzi. An exact minimizer for boolean relations. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 316-319, Santa Clara, CA, November 1989. [3] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C35(8):677-691, August 1986. [4] O. Coudert, C. Berthet, and J. C. Madre. Verification of sequential machines based on symbolic execution. In J. Sifakis, editor, Automatic Verification Methods for Finite State Systems, Lecture Notes in Computer Science 407, pages 365-373. Springer-Verlag,1989. [5] A. Grasselli and F. Luccio. A method for minimizing the number of internal states in incompletely specified sequential networks. IEEE Transactions on Electronic Computers, EC14:350-359, June 1965. [6] G. D. Hachtel, J.-K. Rho, F. Somenzi, and R. Jacoby. Exact and heuristic algorithms for the minimization of incompletely specified state machines. In Proceedings of the European Design Automation Conference, pages 184191, Amsterdam, The Netherlands, February 1991. [7] R. W. House, L. D. Nelson, and T. Rado. Computer studies of a certain class of linear integer problems. In A. Lavi and T. P. Vogl, editors, Recent Advances in Optimisation Techniques, pages 241-280. Wiley, New York, 1966. [8] S.-W. Jeong, B. Plessier, G. D. Hachtel, and F. Somensi. Variable ordering and selection for FSM traversal. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 476-479, Santa Clara, CA, November 1991. [9] S.-W. Jeong, B. F. Plessier, G. D. Hachtel, and F. Somenzi. Variable ordering for binary decision diagrams. In Proceedings of the European Design Automation Conference, Brussels, March 1992. [10] B. Lin and F. Somensi. Minimization of symbolic relations. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 88-91, Santa Clara, CA, November 1990. [11] H. J. Mathony. Universal logic design algorithm and its application to the synthesis of two-level switching functions. IEE Proceedings, Vol. 136, Pt. E, No. 3, May 1989. [12] E. J. McCluskey, Jr. Minimization of boolean functions. Bell Syst. Technical Journal, 35:1417-1444, November 1956. [13] M. Pipponzi and F. Somenzi. An iterative approach to the binate covering problem. In Proceedings of the European Design Automation Conference, pages 208-211, Glasgow, UK, March 1990. [14] R., Rudell and A. Sangiovanni-Vincentelli. Multiple-valued minimization for PLA optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-6(5):727-750, September 1987.


A New Approach to Effective Circuit Clustering Lars Hagen and Andrew B. Kahng UCLA CS Dept., Los Angeles CA 90024-1596 Abstract The complexity of next-generation VLSI systems will exceed the capabilities of top-down layout synthesis algorithms, particularly in netlist partitioning and module placement. Bottom-up clustering is needed to "condense" the netlist so that the problem size becomes tractable to existing optimization methods. In this paper, we establish the DS quality measure, the first general metric for evaluation of clustering algorithms. The DS metric in turn motivates our RWST algorithm, a new self-tuning clustering method based on random walks in the circuit netlist. RW-ST efficiently captures a globally good circuit clustering. When incorporated within a twophase iterative Fiduccia-Mattheyses partitioning strategy, the RW-ST clustering method improves bisection width by an average of 17% over previous matching-based methods. References [1] T. N. Bui, S. Chaudhuri, F. T. Leighton and M. Sipser, "Graph Bisection Algorithms with Good Average Case Behavior", Combinatorica 7(2) (1987), pp. 171-191. [2] T. N. Bui, "Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms", Proc. ACM/IEEE Design Automation Conf., 1989, pp. 775-778. [3] C. K. Cheng and E. S. Kuh, "Module Placement Based on Resistive Network Optimization", IEEE Trans. on CAD 3(1984), pp. 218-225. [4] J. Cong, L. Hagen and A. B. Kahng, "Random Walks for Circuit Clustering", Proc. IEEE Intl. Conf. on ASIC, June 1991, pp. 14.2.1- 14.2.4. [5] D. Coppersmith, P. Tetali and P. Winkler, "Collisions Among Random Walks on a Graph", to appear in SIAM J. Discrete Math.. [6] W.E. Donath, "Logic Partitioning", in Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti, eds., Benjamin/Cummings, 1988, pp. 65-86. [7] J. Garbers, H. J. Promel and A. Steger, "Finding Clusters in VLSI Circuits", (preliminary version of paper in) Proc. IEEE Intl. Conf. on Computer-Aided Design, 1990, pp. 520-523. Also personal communication, A. Steger, April 1992. [8] L. Hagen and A. B. Kahng, "Fast Spectral Methods for Ratio Cut Partitioning and Clustering", Proc. IEEE Intl. Conf. on Computer-Aided Design, 1991, pp. 10-13. [9] L. Hagen and A. B. Kahng, "A New Approach to Effective Circuit Clustering", technical report UCLA CSD TR920041, 1992. [10] J. D. Kahn, N. Linial, N. Nisan and M. E. Saks, "On the Cover Time of Random Walks on Graphs", J. of Theoretical Probability 2(1) (1989), pp. 121-128. [11] B. W. Kernighan and S. Lin, "An efficient heuristic for partitioning graphs", Bell Syst. Tech. J. 49(2) (1970), pp.291307. [12] C. Sechen and K. W. Lee, "An Improved Simulated Annealing Algorithm for Row-Based Placement", Proc. IEEE Intl. Conf. on Computer-Aided Design, 1987, pp. 478-481. [13] R. S. Tsay and E. S. Kuh, "A unified approach to partitioning and placement" in Proc. Princeton Conf. on Inf. and Comp., 1986. [14] Y. C. Wei and C. K. Cheng, "Towards efficient hierarchical designs by ratio cut partitioning", in Proc. IEEE Intl. Conf. on Computer-Aided Design, 1989, pp. 298-301. [15] Y.C. Wei and C.K. Cheng, "A Two-Level Two-Way Partitioning Algorithm", Proc. IEEE Intl. Conf. on Computer-Aided Design, 1990, pp. 516-519.


A Probabilistic Multicommodity-Flow Solution to Circuit Clustering Problems Ching-Wei Yeh, Chung-Kuan Cheng and Ting-Ting Y. Lin University of California, San Diego La Jolla, CA 93093 Abstract Circuit clustering plays a fundamental role in hierarchical designs. Identifying strongly connected components in the circuits can significantly reduce the complexity of the design and improve the performance of the design process. However, there has not been a clear objective function for circuit clustering. In this paper, we present a new clustering metric based on the random graph model and the ratio cut [Wei89] concept. A probabilistic, multi-commodity flow based algorithm is proposed and tested under the new clustering metric. Experimental results show that this algorithm generates promising results with respect to the proposed metric. Extensions and directions for future work are also proposed. References [Bol85] B. Bollobas, Random Graphs, Academic Press Inc., 1985, pp. 11-12 and pp.31-53. [Gar90] Jorn Garbers, "Finding Clusters in VLSI Circuits," Proc. Int. Conf. Computer-Aided Design, 1990, pp.520-523. [Hal70] K.M. Hall, "An r-dimensional Quadratic Placement Algorithm," Management Science, vol. 17, no. 3, Nov. 1970, pp. 219-229. [Iri67] M. Iri, "On an Extension of the Maximum Flow Minimum Cut Theorem to Multicommodity Flows," Journal of Operations Research Society of Japan, 5(4), Dec. 1967, pp.697-703. [Kan83] Sungho Kang, "Linear Ordering and Application to Placement," Proc. 20th Design Automation Conf., 1983, pp. 457-464. [Ker70] B.W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Technical Journal, Vol. 49, No. 2, Feb. 1970, pp. 291-307. [Ona71] K. Onaga and O. Kakusho, "On Feasibility Conditions of Multicommodity Flows in Networks," IEEE Trans. Circuit Theory, 18(4) 1971, pp. 425-429. [Rus71] R.L. Russo, P.H. Oden and P.K. Wolff, Sr., "A heuristic procedure for the partitioning and mapping of computer logic graphs," IEEE Trans. on Computers, vol. C-20, Dec. 1971, pp. 1455-1462. [San89] L.A. Sanchis, "Multi-Way Network Partitioning," IEEE Trans. on Computers, Vol.38, No. l, Jan., 1989, pp.62-81. [Sch72] D. M. Schuler and E. G. Ulrich, "Clustering and Linear Placement," Proc. 9th Design Automation Workshop," 1972, pp.50-56. [Sha90] F. Shahrokhi and D.W. Matula, "The Maximum Concurrent Flow Problem," Journal of the ACM, Vol. 37, No.2, April 1990, pp.318-334. [Wei89] Yen-Chuen Wei and Cheng-Kuan Cheng, "Toward Efficient Hierarchical Designs by Ratio Cut Partitioning," Proc. IEEE Int. Conf. on Computer-Aided Design, 1989, pp.298-301. [Wei90] Yen-Chuen Wei and Cheng-Kuan Cheng, "Two-way Two-level Partitioning Algorithm," Proc. IEEE Int. Conf. on Computer Aided Design, 1990, pp. 516-519. [Yeh91] Cheng-Wei Yeh, Cheng-Kuan Cheng and Ting-Ting Y. Lin, "A General Purpose Multiple-Way Partitioning Algorithm," Proc 28th ACM/IEEE Design Automation Conf., June 1991, pp.421-425.


Optimal Replication for Min-Cut Partitioning James Hwang, Abbas El Gamal Information Systems Laboratory, Stanford University, Stanford, CA 94305 Abstract Heuristics for replicating logic have been shown to reduce pin count and wiring density in partitioned logic networks. We present an efficient algorithm for determining an optimal min-cut replication set for a k-partitioned graph in O(knm log(n2/m)) time. For the NP-hard case with limited size partition components, we propose a new replication heuristic which reduces the worst-case running time by a factor of O(k2) over previous methods. Experimental results are presented. References [1] I. Dobbelaere, A. El Gamal, D. How, and B. Kleveland, "Field Programmable MCM Systems--Design of an Interconnection Frame," FPGA Workshop, 1992. [2] A. El Gamal, et al., Architectures, Circuits, and Computer-Aided Design for Electrically Programmable VLSI, Semi-Annual Technical Report, Defense Advanced Research Projects Agency, March 1991. [3] C. M. Fiduccia and R. M. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions," Proceedings of the 19th Design Automation Conference, 1982, pp. 175-181. [4] L. R. Ford, Jr. and D. R. Fulkerson, "Maximal Flow Through a Network," Canadian Journal of Mathematics, Vol. 8, 1956, pp. 399-404. [5] A. V. Goldberg and R. E. Tarjan, "A New Approach to the Maximum Flow Problem," Proceedings of the 18th ACM Symposium on Theory of Computing, 1986, pp. 136-146. [6] B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," The Bell System Technical Journal, Vol. 49, 1970, pp. 291-307. [7] C. Kring and A. R. Newton, "A Cell-Replicating Approach to Mincut-Based Circuit Partitioning," Digest of Technical Papers, ICCAD-91, Nov. 1991, pp. 2-5. [8] R. L. Russo, P. H. Oden, and P. K. Wolff, Sr., "A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs," IEEE Trans. on Computers, vol. C-20, no. 12, December 1971, pp. 1455-1462.


Efficient Techniques for Inductance Extraction of Complex 3-D Geometries M. Kamon*, M. J. Tsuk**, C. Smithhisler*, J. White* *Massachusetts Inst. of Technology Cambridge, MA 02139 **Digital Equipment Corporation Tewksbury, MA 01876 Abstract In this paper we describe combining a mesh analysis equation formulation technique with a preconditioned GMRES matrix solution algorithm to accelerate the determination of inductances of complex three-dimensional structures. Results from FASTHENRY, our 3-D inductance extraction program, demonstrate that the method is more than an order of magnitude faster than the standard solution techniques for large problems. References [1] W. T. Weeks, L. L. Wu, M. F. McAllister, and A. Singh, "Resistive and inductive skin effect in rectangular conductors," IBM Journal of Res. and Develop., vol. 23, pp. 652-660, November 1979. [2] A. E. Ruehli, "Survey of computer-aided electrical analysis of integrated circuit interconnections," IBM Journal of Research and Development, vol. 23, pp. 626-639, November 1979. [3] P. A. Brennan, N. Raver, and A. Ruehli, "Three dimensional inductance computations with partial element equivalent circuits," IBM Journal of Res. and Develop., vol. 23, pp. 661-668, November 1979. [4] C. A. Desoer and E. S. Kuh, Basic Circuit Theory. New York: McGraw-Hill, 1969. [5] A. E. Ruehli and P. A. Brennan, "Efficient capacitance calculations for three-dimensional multiconductor systems," IEEE Transactions on Microwave Theory and Techniques, vol. 21, pp. 76-82, February 1973. [6] S. M. Rao, T. K. Sarkar, and R. F. Harrington, "The electrostatic field of conducting bodies in multiple dielectric media," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-32, pp. 1441-1448, November 1984. [7] Y. Saad and M. H. Schultz, "GMRES: A generalized minimal residual algorithm for solving nonsymmetric linear systems," SIAM Journal on Scientific and Statistical Computing, vol. 7, pp. 856-869, July 1986. [8] M. J. Tsuk, "Propagation and Interference in Lossy Microelectronic Integrated Circuits," PhD Thesis, Massachusetts Institute of Technology, June 1990. [9] L. Greengard and V. Rokhlin, "A fast algorithm for particle simulations," Journal of Computational Physics, vol. 73, pp. 325-348, December 1987.


An Analytical Method for Finding the Maximum Crosstalk in Lossless-Coupled Transmission Lines Ali El-Zein and Salim Chowdhury Department of Electrical and Computer Engineering, University of Iowa Abstract This paper formulates the crosstalk in a system containing n (n≥2) lossless microstrip transmission lines as a linear function in time. The maximum crosstalk is computed by evaluating the crosstalk at certain breakpoints in time. The technique presented also provides the pattern (rising or falling) of input voltages and their relative delays for which the maximum crosstalk occurs. This pattern is usually determined by the system parameters. Since the maximum crosstalk determines the faulty vs fault free operation, the pattern found could be used for testing integrated logic circuits during the design stage. References [1] S. Chowdhury and J.S. Barkatullah, "An efficient method for computing transient response of integrated circuits with lossy transmission lines," Proceedings of the European Conference on Design Automation, pp. 219-223, March 1992. [2] F.Y. Chang, "Transient analysis of lossless coupled transmission lines in a nonhomogeneous dielectric medium," IEEE Trans. Microwave Theory Tech., vol MTT-18, pp. 616-626, September 1970. [3] I. Catt, "Crosstalk (Noise) in Digital Systems," IEEE Trans. Electronic Computers, vol EC-16, no. 6, pp. 743-763, December 1967. [4] R.A. Horn and C.A. Johnson, Matrix Analysis, Cambridge University Press, 1985. [5] H. B. Bakaglu, Interconnections, and Packaging for VLSI Circuits, Addison-Wesley Publishing Company, Massachusetts, 1990. [6] H. Amemyia, "Time domain analysis of multiple parallel transmission lines," RCA Rev, vol. 28, no. 2, pp. 241-276, June 1967. [7] C. P. Yuan, Modeling and extraction of interconnect parameters in very-large-scale integrated circuits, Ph.D. dissertation, Univ. of Illinois at Urbana-Champaign, August 1983. [8] J. Chilo and T. Arnaud, "Coupling effects in the time domain for an interconnecting bus in high-speed GaAs logic circuits," IEEE Trans. Electron Devices, vol. ED31, pp. 347-352, March 1984.


Time Domain Analysis of Nonuniform Frequency Dependent High-Speed Interconnects Sanjay L. Manney, Michel S. Nakhla and Qi-jun Zhang Department of Electronics, Carleton University Ottawa, Ontario, Canada. K1S 5B6. ABSTRACT A new method based on numerical inversion of the Laplace transform is described for the transient analysis of nonuniform high-speed interconnects in LSI/VLSI circuits. The interconnects are treated as lossy multiconductor nonuniform frequency dependent transmission lines. A new algorithm is proposed for overcoming the inherent initial value instability encountered while numerically integrating transmission line equations. Examples and comparisons with published results are presented. REFERENCES [1] Y. C. Yang, J. A. Kong, and Q. Gu, "Timedomain perturbational analysis of nonuniform coupled transmission lines," IEEE Trans. Microwave Theory Tech., vol. MTT 33, pp. 1120-1130, Nov. 1985. [2] O. A. Palusinsky and A. Lee, "Analysis of transients in nonuniform and uniform multiconductor transmission lines," IEEE Trans. Microwave Theory Tech., vol. MTT-37, pp. 127-138, Jan. 1989. [3] M. A. Mehalic and Raj Mittra, "Investigation of tapered multiple microstrip lines for VLSI circuits," IEEE Trans. Microwave Theory Tech., vol. 38, pp. 1559-1567, Nov. 1990 [4] F.Y. Chang, "Waveform relaxation analysis of nonuniform lossy transmission lines characterized with frequencydependent parameters," IEEE Trans. Circuits Syst., vol. 38, pp. 1484-1500, Dec. 1991. [5] N. Orhanovic and V. K. Tripathi, "Time-domain simulation of uniform and nonuniform multiconductor lossy lines by the method of characteristics," IEEE MTT-S International Microwave Symposium, pp. 1191-1194, 1990. [6] M. S. Nakhla, "Analysis of pulse propagation on high-speed VLSI chips," IEEE Solid-State Circuits, vol. SC-25, pp. 490-494, Apr. 1990. [7] R. Griffith and M. S. Nakhla, "Mixed frequency/ time domain analysis of nonlinear circuits," IEEE Trans. ComputerAided Design, August 1992. [8] S. Lum, M. S. Nakhla and Q. J. Zhang, "Sensitivity analysis of lossy coupled transmission lines," IEEE Trans. Microwave Theory Tech., vol. 39, pp. 2089-2099, Dec. 1991. [9] K. Singhal and J. Vlach, "Computation of time domain response by numerical inversion of the Laplace transform," J. Franklin Inst., vol. 299, pp. 109-126, Feb. 1975. [10] K. Singhal, J. Vlach and M. Nakhla, "Absolutely stable, high order method for time domain solution of networks," Archiv fur Electronik and Uebertragungstechnik, vol. 30, pp. 157-166, 1976. [11] R. Griffith and M. Nakhla, "Time-domain analysis of lossy coupled transmission lines," IEEE Trans. Microwave Theory Tech., vol. 38, pp. 1480-1487, Oct. 1990. [12] M. Nakhla and L. Lu, "Time domain analysis of distributed networks," Proceedings of The IEEE International Symposium on Circuits and Systems (ISCAS), pp. 888-891, June 1991. [13] L. Lu, M. Nakhla and Q. J. Zhang, "A stepping algorithm for transient analysis of distributed networks," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1957-1960, June 1992 [14] A. A. Bykov, "A stable numerical method for constructing a fundamental matrix for a system of ordinary differential equations," Soviet Math. Dokl., vol. 29, pp. 1-4, Jan. 1984. [15] A. van der Sluis, "Estimating the solutions of slowly varying recursions," SIAM J. Math. Anal., vol. 7, pp. 662695,1976. [16] R. M. M. Mattheij, "Characterizations of dominant and dominated solutions of linear recursions," Numer. Math., vol. 35, pp. 421-442,1980. [17] U. M. Ascher, R. M. M. Mattheij and R. D. Russell, Numerical solution of boundary value problems for ordinary differential equations, New Jersey: Prentice Hall, 1988. [18] S. Manney, M. Nakhla and Q. J. Zhang, "Analysis of nonuniform frequency dependent high-speed interconnects," (submitted for publication). [19] R. Griffith, E. Chiprout, Q. J. Zhang and M. Nakhla, "A CAD framework for simulation and optimization of highspeed interconnects," IEEE Trans. Circuits Syst., (submitted for publication).

ICCAD92, Page 456

ENGINEERING EDUCATION: TRENDS AND NEEDS The explosive growth of knowledge in the many diverse fields comprising electrical engineering has resulted in an undergraduate curriculum that is overflowing in specialized courses, increasingly hard to complete in four years, showing a decrease in social and humanistic courses, and providing fewer electives courses. At the same time the enrollment and retention in electrical engineering departments is decreasing nationwide, with a significant difficulty in recruiting and retaining under-represented students (women and minorities). These two major areas combine with increasing complaints on the part of industry that today's students are not prepared, cannot write and speak clearly, and cannot think through problems in a fundamental way. Furthermore, the increasing global nature of the electronics industry requires greater awareness of history, cultures and languages. This is a description of a field in crisis. The result of the crisis has been the radical rethinking of the undergraduate electrical and computer engineering curriculum at several universities. In this session we will hear the solutions chosen at two prominent universities, and the suggestions and comments of one of the leading electronics companies. The presentations will allow sufficient time for audience interaction as well as interchanges among the speakers. Speakers: Professor S.W. Director, Carnegie Mellon University, Pittsburgh, PA Professor J. Allen, MIT, Cambridge, MA Dr. J. Duley, Hewlett-Packard Corporation,Palo Alto, CA


A Zero-Skew Clock Routing Scheme for VLSI Circuits Ying-Meng Li and Marwan A. Jabri Electrical Engineering Department, The University of Sydney, N.S.W. 2006 Australia Abstract A new clock routing scheme that guarantees zero-skew routing result is proposed. It is shown that the time complexity for the algorithm can be reduced to O(n2logn) by using the modified Voronoi diagram to structure the algorithm. L-shaped pairing and H-flipping operations are introduced to further reduce the clock wire length. Extensions are made to the algorithm for use in Building-block Layout and zero skew is also achieved. Significant reduction in total clock wire lengths is observed. References [1] H. Bakoglu, J. T. Walker, and J. D. Meindl. A symmetric clock distribution tree and optimized high-speed interconnections for reduced clock skew in ULSI and WSI circuits. In Proceedings of International Conference on Computer Design, pages 118-122, october 1986. [2] L. P. Chew and R. L. Drysdale III. Voronoi diagrams based on convex distance functions. In Proc. 1st ACM Symposium on Computational Geometry, pages 235-244,1985. [3] J. Cong, A. Kahng, and G. Robins. Matching based methods for high-performance clock routing. In manuscript submitted to IEEE Trans. on CAD-IC, 1992. [4] W.-M. Dai, T. Asano, and E. S. Kuh. Routing region definition and ordering scheme for building-block layout. IEEE Transactions on Computer-Aided Design, CAD-4(3):189197,1985. [5] M. Jackson, A. Srinivasan, and E. S. Kuh. Clock routing for high-performance ics. In Proceedings of 27th ACM/IEEE Design Automation Conference, pages 573-579,1990. [6] A. Kahng, J. Cong, and G. Robins. High-performance clock routing based on recursive geometric matching. In Proceedings of 28th ACM/IEEE Design Automation Conference, pages 322-327, 1991. [7] D. T. Lee. Two dimensional Voronoi diagram in the lp metric. In J. ACM, pages 604-618, 1980. [8] F. P. Preparata and M. I. Shamos. Computational geometry, an introduction. Springer-Verlag, 1990. [9] P. Ramanathan and K. G. Shin. A clock distribution scheme for non symmetry VLSI circuits. In Proceedings of International Conference on Computer-Aided Design, pages 398-401, November 1989. [10] R. Sedgewick. Algorithms. Addison-Wesley, 1988. [11] R. S. Tsay. Exact zero skew. In Proc. IEEE Intl. Conf, on Computer-Aided Design, Santa Clara, November 1991.


Zero Skew Clock Routing in Multiple-Clock Synchronous Systems Wasim Khan, Moazzem Hossain, Naveed Sherwani Department of Computer Science, Western Michigan University, Kalamazoo, MI 49008 Abstract: Clock routing problem for single-phase clock has been extensively studied in recent years. However, in many microprocessor designs, multi-phase clocks are used for improved system design. The problem of routing multiple-clock is more complicated than a singleclock because in multiple-clock systems, we need to minimize not only the skew within a clock (intra-clock skew) but also minimize skew between different clocks (inter-clock skew). In this paper, we present an algorithm to minimize both intra-clock skew and interclock skew. The algorithm has been implemented on SPARC 1+ in C and have been tested it on several industrial benchmarks as well as on randomly generated examples. In particular, we tested our result for a 267 synchronous component circuit at clock rates of 100MHz. The significance of this paper lies in the fact that this is the first ever result which deals with multiple clock routing with zero skew. References [1] H. B. Bakoglu. "Circuits. Interconnections, and Packaging for VLSI."' Addison-Wesley Publishing Company, reading. [2] S. Dhar. M. A. Franklin and D. F. Wann. "Reduction of Clock Delays in VLSI Structures"'. IEEE International Conference on Computer Design: VLSI in Computers (ICCD-84). 1984, pp.778-783. [3] T. M. Lin and C. A. Mead. "Signal Delay in General RC Networks."' IEEE Transactions on Computer-Aided Design. Vol. CAD-3. No.4. October 1984. pp.331-349. [4] A. Kahng. J. Cong. and G. Robins. "HighPerformance Clock Routing Based on Recursive Geometric Matching." IEEE Design Automation Conference(DAC-91). June 1991. pp.322-327. [5] W. Khan. M. Hossain, and N. Sherwani. "Minimum Skew Multiple Clock Routing in Synchronous ASIC Systems". to appear in The Fifth International ASIC Conference and Exhibit. Rochester. New York. Sept. 2125. 1992. [6] W . Khan. M. Hossain, and N. Sherwani. "Zero Skew Clock Routing in Multiple-Clock Synchronous Systems". Tech. Rep. no TR/92-16. Department of Computer Science. Western Michigan University. 1992. [7] Naveed A. Sherwani and Bo Wu. "Clock Layout For High-Performance ASIC Based On Weighted Center Algorithm". IEEE International ASIC Conference and Exhibit. September 1991. pp 155.1 - 15-5.4 . [8] R . S . T s a y . "Exact Zero Skew." Proceedings of ICCAD `91. pp. 336-339. Nov. 1991.


HERO: Hierarchical EMC-Constrained Routing D. Theune, R. Thiele, T. Lengauer, A. Feldmann Cadlab - Joint Venture, University of Paderborn/Siemens Nixdorf Informationssysteme AG, Paderborn, Germany Abstract Due to the increasing significance of fast component technologies and the increasing complexity of printed circuit boards, electromagnetic phenomena, e.g. reflections and crosstalk, gain more and more importance and may even disturb the function of a printed circuit board. In the future, it will be indispensable to consider phenomena of electromagnetic compatibility (EMC) already during layout synthesis. In this paper robust methods are presented which, for the first time, make it possible to incorporate complex EMC-constraints and EMC-cost criteria into printed circuit board routing. The results achieved so far are reported. References [1] H.B. Bakoglu. Circuits, interconnections and packaging for VLSI. Addison Wesley Publ. Comp., 1990. [2] M. Burstein, R. Pelavin. Hierarchical wire routing. IEEE Trans. on CAD of IC's and Systems, 671-680, 1983. [3] U. Choudhury, A. Sangiovanni-Vincentelli. Constraint generation for routing analog circuits. 27th ACM/IEEE Design Automation Conf., 561-566, 1990. [4] D.J. Garrod, R.A. Rutenbar, L.R. Carley. Automatic layout of custom analog cells in ANAGRAM. IEEE ICCAD, 544-547,1988. [5] W. John. Remarks to the solution of EMC-problems on printed circuit boards. 7th Int. Conf. on EMC, Univ. of York, UK, 1990. [6] W. John. An EMC-analysis workbench for component design based on a framework approach. Microsystem Technologies 91, 7. Int. Kongreß and Fachmesse für Mikrosystemtechnik, Berlin, 1991. [7] W. John, D. Theune, R. Thiele. A concept for EMC-appropriate routing of printed circuit boards (in German). Kleinheubacher Tagong 1991, 363-376, 1991. [8] S. Kiefl. A new hierarchical concept for the physical design of PCBs. Int. Workshop on Placement and Routing, Research Triangle Park, North Carolina, 1988. [9] J. Kessenich, G. Jackoway. Global forced hierarchical router. 23rd ACM/IEEE Design Automation Conf., 798802, 1986. [10] U. Lauther. Top down hierarchical global routing for channelless gate arrays based on linear assignment. Proceedings of VLSI'87, 141-151. Elsevier Science Publ. B.V., Amsterdam, 1987. [11] T. Lengauer. Combinatorial algorithms for integrated circuit layout. Teubner Wiley Series in Computer Science. 1990. [12] W. K. Luk, P. Sipila, M. Tamminen, D. Tang, L. S. Woo, C. K. Wong. A hierarchical global wiring algorithm for custom chip design. IEEE Trans. on CAD of IC's and Systems, 518-533, 1987. [13] T. Lengauer, D. Theune. Efficient algorithms for path problems with general cost criteria. 18th Int. Symposium on Automata, Languages and Programming, 314-326. Springer Lecture Notes in Computer Science, No. 510, 1991. [14] T. Lengauer, D. Theune. Unstructured path problems and the making of semirings. 2nd Workshop on Algorithms and Data Structures, Ottawa, Canada, 189-200. Springer Lecture Notes in Computer Science, No. 519, 1991. [15] E. Malavasi, M. Chilanti, R. Guerrieri. A general router for analog layout. COMPEURO '89, Hamburg, 549551, 1989. [16] E. Malavasi, U. Choudhury, A. Sangiovanni-Vincentelli. A routing method for analog integrated circuits. IEEE ICCAD, 202-205, 1990. [17] T. Lengauer, R. Muller. A robust framework for hierarchical floorplanning with integrated global wiring. IEEE ICCAD, 148-151, 1990. [18] A. P.-C. Ng, P. Raghavan, C. D. Thompson. Experimental results for a linear program global router. Computers and Artificial Intelligence, 6(3):229-242, 1987.

[19] P. Raghavan, C. D. Thompson. Randomized rounding: A technique for provably good algorithms and algorithmic proofs. Combinatorica, 7(4):365-374, 1987. [20] D. Theune, R. Thiele, A. Feldmann. Robust methods for EMC-constrained routing of printed circuit boards (in German). GME/ITG-Diskussionssitzung 'Entwicklung von Analogschaltungen und CAE-Methoden’, Universität GH Paderborn, 1991. [21] J.S. Turner. Allmost all k-colorable graphs are easy to color. Journal of Algorithms, 9:63-82, 1988. [22] K. Wawryn. Layout including parasitics for printed circuit boards. Int. J. Circuit Theory Appl. (UK), 6(2):10728, April 1988.


Perfect-balance Planar Clock Routing with Minimal Path-length Qing Zhu, Wayne Wei-Ming Dai Computer Engineering Board of Studies University of California, Santa Cruz, Santa Cruz, CA 95064 Abstract The design of high speed digital VLSI circuits prefers that the clock net is routed on the metal layer with the smallest RC delay. This strategy not only avoids the difficulties of having different electrical parameters on different layers, but also eliminates the delay and attenuation of the clock signal through vias. The clock phase-delay is also decreased. In this paper, we present a novel algorithm, based on max-min optimization, to construct a planar clock tree which can be embedded on a single metal layer. The clock tree achieves equal path length-the length of the path from the clock source to each clock terminal is exactly the same. In addition, the path length from the source to clock terminals is minimized. Some examples including industrial benchmarks have been tested and the results are promising. References [1] H. Bakoglu, J. T. Walker, and J. D. Meindl. A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ulsi and wsi circuits. In Proc. IEEE Intl. C o n f . on Computer Design, pages 118-122, 1986. [2] D. Dobberpuhl and R. Witek. A 200mhz 64b dual issue cmos microprocessor. In Proc. IEEE Intl. Solid-State Circuits C o n f . , pages 106-107, 1992. [3] M. A. B. Jackson, A. Srinivasan, and E. S. Kuh. Clock routing for high-performance ics. In Proc. of 27th Design Automation Conf., pages 573-579, 1990. [4] A. Kahng, J. Cong, and G. Robins. High-performance clock routing based on recursive geometric matching. In Proc. of 28th Design Automation Conf., pages 322-327, 1991. [5] R.-S. Tsay. Exact zero skew. In Digest of Tech. Papers of IEEE Intl. Conf. on Computer Aided Design, pages 336-339, 1991. [6] Qing Zhu and Wayne Wei-Ming Dai. Perfect-balance planar clock routing with minimal path-length. Technical Report, Computer Engineering Board of Studies, U. C. Santa Cruz, UCSC-CRL-92-12, April 1992.


Design of System Interface Modules Jane S. Sun, Robert W. Brodersen EECS Department, University of California at Berkeley Abstract Complex digital systems are designed with hardware modules which interact by transferring information and synchronizing their inputs and outputs. The modules can be constructed from a variety of single IC components to subsystems, and typically they have incompatible I/O and communication protocols. A large portion of the integration time is thus devoted to designing the interfaces (also a module) between interacting modules. This paper presents a design methodology and high-level synthesis techniques for integrating hardware modules into a system. The interface between modules, which can obey arbitrary protocols, is generated from a high-level specification developed especially for describing inter-module communication. Central to the design methodology are libraries which contain system-level module generators and a strategy to capture the protocol and timing information necessary for interface synthesis. The main impact of this work is raising the interface design abstraction and reducing the effort required from a designer to produce a system using various IC technologies. References [1] J.A. Nestor, D.E. Thomas. Behavioral Synthesis with Interfaces. Proc. of ICCAD, 1986. [2] S. Hayati, A.C. Parker. Automatic Production of Controller Specificationsfrom Control and Timing Behavioral Descriptions. Proc. of 26th DAC, 1989. [3] M.C. McFarland, A.C Parker, R. Camposano. The High-level Synthesis of Digital Systems. Proc. of the IEEE, Vol. 78, No. 2, Feb. 1990. [4]T.A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. Proc. of ICCD, Oct. 1987. [5] T.H.Y Meng, R.W. Brodersen, D.G. Messerschmitt. Automatic Synthesis of Asynchronous Circuits from High-Level Specifications. IEEE Trans. on CAD, Vol. 8, No. 11, Nov. 1989. [6] G. Borriello and R.H. Katz. Synthesis and Optimization of Interface Transducer Logic. Proc. of ICCAD, Nov. 1988. [7] M.B. Srivastava, et. al. Rapid-Prototyping of Hardware and Software in a Unified Framework. Proc. of ICCAD, Nov 1991. [8] J.S. Sun, et. al. SIERA: A CAD Environment for Real-Time Systems. 3rd Physical Design Workshop, May 1991. [9] B. Richards. SDL Language Syntax. LAGER Man., U.C. Berkeley. [10] D. Doukas, A.S. LaPaugh. CLOVER: A Timing Constraints Verification System. Proc. of 28th DAC, June 1991. [11] J. Rabaey, et. al. HYPER Flowgraph Policy. U.C. Berkeley, 1990. [12]T. Amon, et. al. OEsim: A Simulator for Timing Behavior. Proc. of 28th DAC, June 1991. [13] G.V Bochman, et. a1. Structured Specification of Communicating Systems. IEEE Trans. on Computers, Vol. C-32, No. 2, Feb. 1983. [14] OCTTOOLS Reference Manuals. EECS Dept., U.C. Berkeley, 1991. [15] R.K. Yu. PLDS: Prototyping in Lager Using Decomposition and Synthesis. Mem. No. UCB/ERL M91/53, U.C. Berkeley, May 1991.


A Partitioning Algorithm For System-Level Synthesis G. Menez, M. Auguin, F. Boéri, C. Carrière Laboratoire d'Informatique Signaux et Systemes, CNRS / Universite de Nice Sophia - Antipolis 41 Bd Napoleon III - 06041 Nice Cedex - FRANCE Abstract The major purpose of this paper is to present the partitioning / scheduling / allocation algorithm developed for the CAPSYS method. The aim of this project is to define a tool able to automatically design dedicated and embedded VLIW architectures for large and complex applications. It inherits a sizeable knowledge-pool from the wider field of parallel processors, VLIW compiler design and high-level synthesis (HLS). We focus here on constraints of such a system synthesis approach and more especially on the particularity of the partitioning step. The solution proposed implements a software / hardware approach based on the list-scheduling heuristic. References [1] G.Menez, Thesis, Sept. 1991, University of Nice Sophia-Antipolis. [2] C.Carrière,Thesis, Sept. 1992, University of Nice Sophia-Antipolis. [3] J.A Fisher, J.R. Ellis, J.C. Ruttenberg and A. Nicolau," Parallel Processing : A Smart Compiler and a Dumb Machine", SIGPLAN Notices, Vol. 19, N. 6, June 1984, pp. 34-47. [4] M.C. McFarland, A.C.Parker, R. Camposano, "The high level synthesis of digital systems", Proceedings of IEEE, vol. 78, n. 2, pp 301- 318, feb. 1990. [5] A.V. Aho, R.Sethy., J.D. Ullman,"Compilers, principles, techniques and tools", Addison-Wesley (1986). [6] J.R. Ellis, "Bulldog: A compiler for VLIW Architectures", The MIT Press, 1985. [7] M. Auguin, F. Boeri, Parallel memory management in a SIMD computer, IFIP 10.3 Working Conference on Highly Parallel Computers, Sophia-Antipolis, France, 24-26 March, 1986. [8] J.A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction", IEEE Trans. on Comp., vol. 30, n. 7, pp. 478-490, july 1981. [9] C.J. Tseng, D.P. Siewiorek, "Facet: A Procedure for Automated Synthesis of Digital Systems Proceedings of the 20th Design Automation Conf. , pp 490-496, 1983. [10] P.G. Paulin, J.P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's". IEEE Trans. on CAD, vol. 8, N. 6, June 1989. [11] A. C. Parker, J. Pizarro and M. Mlinar, "MAHA : A program for Datapath Synthesis", 23rd Design Automation Conf., pp. 461-466, june 1986. [12] D. Landskov. and all, "Local microcode compaction techniques, Computing Survey", vol. 12, n. 3(1980). [13] P.M. Kogge , "The architecture of pipelined computers", McGraw-Hill (1981). [14] C. Eisenbeis , "Optimization of horizontal microcode eneration for loop structures", International Conf. on Supercomputing, Saint Malo, FRANCE, july 1988.


Synthesis of the Hardware/Software Interface in Micro controller-Based Systems Pai Chou, Ross Ortega, Gaetano Borriello Department of Computer Science and Engineering, University of Washington, Seattle, WA Abstract MicrocontroIler-based systems require the design of a hardware/software interface that enables software running on the microcontroller to control external devices. This interface consists of the sequential logic that physically connects the devices to the microcontroller and the software drivers that allow code to access the device functions. This paper presents a method for automatically synthesizing this hardware/software interface using a recursive algorithm. Practical examples are used to demonstrate the utility of the method and results indicate that the synthesized circuit and driver code are comparable to that generated by human designers. This new tool will be used by higher-level synthesis tools to evaluate partitionings of a system between hardware and software components. References [1] Intel. 8-Bit Embedded Controller Handbook, Intel Corporation, 1990. [2] AT Martin. Programming in VLSI: From Communicating Processes To Delay-Insensitive Circuits, Department of Computer Science, California Institute of Technology, Caltech-CS-TR 89-1, 1989. [3] C.A.R. Hoare. Communicating Sequential Processes, Prentice/Hall International, Englewood Cliffs, NJ, 1985. [4] M. Srivastava, R. Brodersen. "Rapid Prototyping of Hardware and Software in a Unified Framework", Proc. of the International Conference on Computer-Aided Design, 1991. [5] J. Sun, R.W. Brodersen, "Design of System Interface Modules", Submitted to ICCAD-92. [6] F. Vahid, D. Gajski, "Specification Partitioning for System Design", 29th ACM/IEEE Design Automation Conference, June 1992. [7] Shelley & Associates. SLM21602 LCD Data Book, 1990.


Assignment of Global Memory Elements for Multi-Process VHDL Specifications H. Krämer, J. Müller Automation of Circuit Design (Prof. D. Schmid), Forschungszentrum Informatik, Karlsruhe, Germany Abstract This paper describes a method for the synthesis of the global memory structure for a behavioural VHDL specification which consists of several concurrent processes. The global memory cells may be implemented as separate registers or RAMs. Emphasis was laid on the minimization of both the area demand and timing demand due to access conflicts. The VHDL description is modelled as Petri net. The cases of this Petri net are regarded as possible states of the system. The conflicts are then estimated on the basis of the probabilities that the system is in a certain state. Finally the global signals are combined to larger memory structures by a clustering algorithm which is guided by both a decrease in area cost and possible conflicts. References [1] L.P.M. Benders, M.P.J. Stevens, Task level Behavioural Hardware Description, Proc. of Euromicro, 1991 [2] L. Claesen, F. Catthor, D. Lanneer, G. Goossens, S. Note, J. van Meerbergen, H. De Man, Automatic Synthesis of Signal Processing Benchmark using the CATHEDRAL Silicon Compilers, Proc. IEEE CICC, 1988 [3] A. Delaruelle, O. McArdle,J. van Meerbergen, C. Niessen, Synthesis of Delay Functions in DSP Compilers, Proc. 1st European Design Automation Conference, Glasgow, 1990 [4] C. S. Georg Lee, P. R. Chang, A Maximum Pipelined CORDIC Architecture For Inverse Kinematic Position Computation, IEEE Journal. of Robotics and Automation, Vol. 3, No 5, 1987 [5] R. K. Gupta, G. De Micheli, System-Level-Synthesis Using Re-programmable Components, Proc. of 3rd European Design Automation Conference, 1992 [6] S. Prakash, A. C. Parker, Synthesis of ApplicationSpecific Multiprocessor Architecture, Proc. of 28th Design Automation Conference, 1991 [7] W. Reisig, Petrinetze, eine Einfuhrung, Springer-Verlag, 2nd Edition, 1990 [8] J Rabaey, H. De Man, J. Vanhoof, G. Goossens, F. Catthoor, CATHEDRAL II: A Synthesis System for MultiProcessor DSP Systems, in "Silicon Compilation", D. Gajski (Ed), Addison-Wesly, 1988 [9] I. Verbauwhede, F. Catthoor, J. Vanderwalle, H. De Man, Background Memory Synthesis for Algebraic Algorithms on Multi-Processor DSP Chips, Proc. of VLSI 89, 1989 [10] R. Walker, R. Camposano, A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, 1991, [11] H. J. Zander, Logischer Entwurf binärer Systeme, VEB Verlag Technik, Berlin 1989


Performance Optimization of Sequential Circuits by Eliminating Retiming Bottlenecks Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler C&C Research Labs, NEC USA Princeton, NJ 08540 Abstract Retiming is an effective technique to optimize the performance of synchronous sequential circuits. This paper proposes a method to improve the effectiveness of retiming by transforming the sequential circuit. Bottlenecks which prevent retiming to achieve a desired clock period are identified. Conditions to eliminate the retiming bottlenecks are derived. These conditions are satisfied by a process of identifying sub-circuits and satisfying a set of timing constraints on the sub-circuits. The transformed circuit, which satisfies the timing constraints, can be retimed to achieve the desired clock period. If the original circuit has its initial state specified, our method always generates the final circuit with an equivalent initial state. Experimental results on a variety of sequential benchmark circuits demonstrate significant performance improvement. References [1] K.J. Singh, A.R. Wang, R.K. Brayton, and A. Sangiovanni-Vincentelli. Timing Optimization of Combinational Logic. In Proc. IEEE International Conference on Computer-Aided Design, pages 282 - 285, November 1988. [2] P.C. McGeer, R.K. Brayton, A.Sangiovanni-Vincentelli, and S.K. Sahni. Performance Enhancement through the Generalized Bypass Transform. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 184 - 187, November 1991. [3] H. Touati, H. Savoj, and R.K. Brayton. Delay Optimization of Combinational Logic Circuits by Clustering and Partial Collapsing. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 188-191,November 1991. [4] D. Hathaway, L.H. Trevillyan, C.L. Berman, and A.S. LaPaugh. Efficient Techniques for Timing Correction. In Proc. ISCAS, pages 391-394, June 1985. [5] C.E. Leiserson and J.B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6:5 -35,1991. [6] G. De Micheli. Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization. IEEE Transactions on Computer Aided Design, 10(1):63 - 73, January 1991. [7] K. Bartlett, G. Borriello, and S. Raju. Timing Optimization of Multiphase Sequential Logic. IEEE Transactions on Computer Aided Design,10(1):51- 62, January 1991. [8] S. Malik, K.J. Singh, R.K. Brayton, and A. Sangiovanni-Vincentelli. Performance Optimization of Pipelined Circuits. In Proc. IEEE International Conference on Computer-Aided Design, pages 410 -413, November 1990. [9] N. Shenoy and R.K. Brayton. Retiming of Circuits with Single Phase Transparent Latches. In Proceedings of the International Conference on Computer Design, October 1991. [l0] A.T. Ishii, C.E. Leiserson, and M.C. Papaefthymiou. Optimizing two-phase, levelclocked circuitry. In Advanced Research in VLSI and Parallel Systems: Proc. of the 1992 Brown/MIT Conference, pages 245 - 264, March 1992. [11] S. Dey, M. Potkonjak, and S.G. Rothweiler. Performance Optimization of Sequential Circuits by Eliminating Retiming Bottlenecks. Technical Report 92-0013-45016-2, C&C Research Labs, NEC USA, May 1992. [12] S. Dey, F Brglez, and G. Kedem. Circuit Partitioning for Logic Synthesis. IEEE Journal of Solid-State Circuits, 26(3):350- 363, March 1991. [13] E.M. Sentovich,K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A. SangiovanniVincentelli. Sequential Circuit Design using Synthesis and Optimization. In Proceedings of the International Conference on Computer Design, October 1992. [14] Saeyang Yang. Logic Synthesis and Optimization Benchmarks, User Guide Version 3.0. In International Workshop on Logic Synthesis, MCNC, Research Triangle Park, NC, May 1991.


Exploiting Mufti-Cycle False Paths in the Performance Optimization of Sequential Circuits Pranav Ashar, Sujit Dey C&C Research Labs, NEC USA Princeton, NJ Sharad Malik Dept. of EE, Princeton Univ. Princeton, NJ Abstract This paper addresses the performance optimization problem for sequential circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clockcycles. Multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. A preliminary implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a very modest area overhead. References [1] F. Brglez, D. Bryan, and K. Kozminski. Combinational Profiles of Sequential Benchmark Circuits. In Proceedings of the International Symposium on Circuits and Systems, Portland, Oregon, May 1989. [2] H. C. Chen and D. H. Du. Path sensitization in critical path problem. In ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990. [3] K-C Chen and M. Fujita. Network resynthesis for delay minimization. In The Proceedings of the Design Automation Conference, pages 443-448, June 1992. [4] G. DeMicheli. Synchronous logic synthesis: Algorithms for cycle-time minimization. IEEE Transactions on Computer-aided design, CAD- 10(l): 63-7 3, January 1991. [5] S. Devadas, K. Keutzer, and S. Malik. Delay Computation in Combinational Circuits: Theory and Algorithms. In Proceedings of the International Conference on Computer-Aided Design, November 1991. [6] J. P. Fishburn and A. E. Dunlop. TILOS: A posinomial programming approach to transistor sizing. In Proceedings of the International Conference on Computer-Aided Design, pages 326-328, November 1985. [7] A. Ghosh, S. Devadas, and A. R. Newton. Test Generation for Highly Sequential Circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 362-365, November 1989. [8] K. Keutzer, S. Malik, and A. Saldanha. Is redundancy necessary to reduce delay? IEEE Transactions on Computer-aided design, 10(4):427-435, April 1991. [9] Charles E. Leiserson and James B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6(1):5-36,1991. [10] R. Lisanke, editor. FSM Benchmark Suite. Microelectronics Center of North Carolina, Research Triangle Park, North Carolina, 1987. [11] S. Malik, E. Sentovich, R. K. Brayton, and A. Sangiovanni Vincentelli. Retiming and resynthesis: Optimizing sequential networks with combinational techniques. IEEE Transactions on Computer-aided design, CAD10(1):7484, January 1991. [12] S. Malik, K. J. Singh, R. K. Brayton, and A. Sangiovanni-Vincentelli. Performance optimization of pipelined circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 410-413, November 1990. To appear, IEEE Transactions on CAD. [13] P. C. McGeer and R. K. Brayton. Integrating functional and temporal domains in logic design. Kluwer Academic Publishers, 1991. [14] A. Saldanha, R. K. Brayton, and A. SangiovanniVincentelli. Circuit structure relations to redundancy and delay: The KMS algorithm revisited. In The Proceedings of the Design Automation Conference, pages 245-252, June 1992.

[15] E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli. Sequential circuit design using synthesis and optimization. In Proceedings of the International Conference on Computer Design, 1992. [16] K. J. Singh, A. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Timing optimization of Combnational logic. In Proceedings of the International Conference on Computer-Aided Design, pages 282-285, November 1988. [17] H. Touati and R. K. Brayton. Computing initial states of retimed circuits. To appear, IEEE Transactions on CAD. [18] H. Touati, C. Moon, R. K. Brayton, and A. Wang. Performance-oriented technology mapping. In Proceedings of the sixth MIT VLSI Conference, pages 79-97, April 1990. [19] H. Touati, H. Savoj, B. Lin R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDDs. In Proceedings of the International Conference on Computer-Aided Design, pages 130133, November 1990.


Valid Clocking in Wavepipelined Circuits William K.C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Department of EECS, University of California, Berkeley, CA 94720 Abstract In this paper, we consider the problem of clocking wavepipelined circuits. Wavepipelined circuits can operate at a much higher clock rate than conventional pipelined circuits, because its maximum rate is limited only by the path delay difference instead of the maximum path delay, [Cot69]. Current research in this area has focused on minimizing the path delay difference, hence maximizing the achievable clock frequency. In this paper, we present an analysis of valid clock rates in wavepipelined circuits using a technique called Timed Boolean Functions. We show that the valid intervals for the clack period can be disconnected. Thus, it is insufficient to only know the minimum valid clock period in guaranteeing proper operation of pipelined circuits. We provide analytic expressions for the valid clock intervals in terms of both topological delay as well as 2-vector longest and shortest delays. Also uncertainties arising from manufacturing are taken into account. We also illustrate some potential difficulties in computing the exact valid clock intervals by demonstrating discontinuity and non-monotonicity of the harmonic number H(τ) (the number of valid simultaneous data waves allowed) as a function of the clock period τ . References [Cot69] L. Cotten. Maximum rate pipelined systems. 1969 AFIPS Proceedings of Spring Joint Computer Conference, 1969. [DKM92] S. Devadas, K. Keutzer, and S. Malik. Certified timing verification and transition delay of a logic circuit. Proc. of the 29th Design Automation Conference, June, 1992. [Fis90] J. Fishburn. Clock skew optimization. IEEE Transactions on Computers, Vol. 39, No. 7, July 1990. [JC91] D. Joy and M. Ciesielski. Placement for clock period minimization with multiple wave propagation. Proceedings of 28th Design Automation Conference, 1991. [Kog81] P Kogge. The Architecture of Pipelined Computers. Prentice-Hall, Englewood Cliffs, N.J., 1981. [LB92] W. Lien and W. Burleson. Wave-domino logic: Timing analysis and applications. 1992 ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1992. [LBSV92a] W. Lam, R. Brayton, and A. SangiovanniVincentelli. Valid clocking in wavepipelined circuits. UC Berkeley ERL memorandum: UCBIERL, 1992. [LBSV92b] W. Lam, R. Brayton, and A. SangiovanniVincentelli. Exact delay computation with timed boolean function. UC Berkeley ERL memorandum: UCBIERL M92157, May 1992. [LBSV92c] W. Lam, R. Brayton, and A. SangiovanniVincentelli. Minimum cycle time of synchronous circuit with bounded delays. UC Berkeley ERL memorandum: UCBIERL M92156, May 1992. [MB89] P. McGeer and R. Brayton. Provably correct critical paths. The Proceedings of the Decennial Caltech VLSI Conference, 1989. [Ung69] Stephen H. Unger. Asynchronous Sequential Switching Circuits. John Wiley and Sons, Inc., 1969. [WDF89] D. Wong, D. DeMicheli, and G. Flynn. Inserting active delay elements to achieve wave pipelining. Proceedings of the ICCAD, 1989.


Precise Timing Verification of Logic Circuits under Combined Delay Model Shinji KIMURA, Shigemi KASHIMA and Hiromasa HANEDA Dept. of Electronics Engineering, Kobe University, 1-1 Rokkodai, Nada, Kobe, 657 JAPAN Abstract The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so. References [1] A. V. Aho, J. E. Hopcroft, and J. D. Ullman. The Design and Analysis of Computer Algorithms. AddisonWesley, 1974. [2] J. Burch. Combining CTL, trace theory and timing models. In LNCS 407, Automatic Verification Methods for Finite State Systems, J.Sifakis (Ed.), pages 334-348, June 1989. [3] D. L. Dill and E. M. Clarke. Automatic verification of asyncronous circuits using temporal logic. IEE Proceedings, Part E(5):276-282, Sept. 1986. [4] F. K. Hanna and N. Daeche. Specification and verification using higher-order predicate logic. IEE Proc. E, 13:3(5):242-251, Sept. 1986. [5] T. Instruments. The Bipolar Digital Integrated Circuits Data Book. for Design, Engineers. Texas Instruments, 1976. [6] N. Ishiura, Y. Deguchi, and S. Yajima. Coded time-symbolic simulation using shared binary decision diagram. In Proc. of 27-th DA Conf., pages 130-135, 1990. [7] S. Kimura and H. Haneda.. The least-fixed-point of feedbackloops of logic circuit for a set of input strings. Trans of the IEICE Japan, E 72(12):1344-1349, Dec. 1989. [8] S. Kimura and S. Yajima. The description and verification of input constraints and input-output specifications of logic systems using a new extended regular expression. In Proc. of VLSI'87, pages 81-90, Aug 1.987. [9] Z. Kohavi. Switching and Finite Automata Theory (2nd Ed.) Chapter 13. TATA McGraw-Hill Publishing Co., 1987. [10] D. L. D. M. C. Browne, E. M. Clarke and B. Mishra. Autornatic verification of sequential circuits using temporal logic. IEEE Trans. on Comput., C-35(12):1035-1044, Dec. 1986. [11] H.-K. T. M. S. Devadas and A. R. Newton. On the verification of sequential machines at differing levels of abstraction. IEEE Trans. on CAD, CAD-35(8):713-722, June 1988. [12] C.-.I. H. Segar. Models and algorithms for race analysis in asynchronous circuits. In Ph.D. Theis, Waterloo University, 1988.


DECOR - Tightly Integrated Design Control and Observation Elisabeth Kupitz, Jürgen Tacken Cadlab Cooperation of Paderborn University and Siemens Nixdorf Informationssysteme AG, Paderborn, Germany Abstract This paper presents DECOR, a configurable design flow management component for online monitoring and control of concurrent design processes. In addition, DECOR allows automatic activation of design actions. Since DECOR is tightly integrated into a framework like a usual design tool, its approach is also applicable for other frameworks. DECOR allows to control encapsulated tools as well as tools that are tightly integrated into the framework. Manipulations of data objects with arbitrary granularity from files or directories down to single structures can be considered. DECOR relies on a formal model for the specification of design process behaviour. This is especially important for environment openness, since the effect of changes to an existing design process model due to environment extensions can only be assessed if the semantics of the specified design process is clearly defined. References [1] W. Allen, D. Rosenthal, K. Fiduk, "The MCC CAD Framework Methodology Management System", Proceedings of the 28th ACM/IEEE Design Automation Conference, 1991. [2] K.O. ten Bosch, P. Bingley, P. van der Wolf, "Design Flow Management in the NELSIS CAD Framework", Proceedings of the 28th ACM/IEEE Design Automation Conference, 1991. [3] A. Bretschneider, C. Kopf, H. Lagger, A. Hsu, E. Wei, "Knowledge Based Design Flow Management", IEEE International Conference on Computer-Aided Design, 1990. [4] A. Casotto, A.R. Newton, A. SangiovanniVincentelli, "Design Management based on Design Traces", Proceedings of the 27th ACM/IEEE Design Automation Conference, 1990. [5] L.A. Cherkasova, V.E. Kotov, "Structured Nets", Lecture Notes of Computer Science 118, Springer, 1981. [6] A. Di Janni, "A Monitor for complex CAD systems", Proceedings of the 23rd ACM/IEEE Design Automation Conference, 1986. [7] H. J. Genrich, K. Lautenbach, "System Modelling with High-Level Petri Nets" Theoretical Computer Science (13), North Holland, 1981. [8] P. van den Hamer, M.A. Treffers, "A Data Flow Based Architecture for CAD Frameworks", IEEE International Conference on ComputerAided Design, 1990. [9] B. Kleinjohann, E. Kupitz, "Tool Communication in an Integrated Synthesis Environment", Proceedings of the 2nd European Design Automation Conference, 1991. [10] A. Meckenstock, et al., "Concept and Architecture of a Distributed Object-Oriented Datebase Kernel", Cadlab Report 1392, Cadlab, Paderborn, 1992: [11] C.A. Petri, "Kommunikation mit Automaten" (in German), Schriften des IIM Nr. 2, Institut fur Instrumentelle Mathematik, Bonn, 1962. [12] B. Steinmuller, "The JESSI-COMMON-FRAME Project - A Project Overview", in M. Newman and T. Rhyne (editors), Proceedings of the 3rd International Workshop on Electronic Design Automation Frameworks, 1992.


Incorporating Design Flow Management in a Framework based CAD System Peter Bingley, Olav ten Bosch and Pieter van der Wolf Delft University of Technology, Department of Electrical Engineering, Mekelweg 4, 2628 CD Delft, The Netherlands Abstract This paper describes how design flow management can be incorporated in a framework based CAD system. Based on powerful concepts for design flow management and the architecture of a CAD system we have aimed to realize an integrated design environment with a maximum of functionality and an absolute minimum impact on existing design tools. Addressed are the interface between the design tools and the framework, the architecture of the framework including the inter-relations between the different components, and the internal operation of the flow management components. These issues are combined to arrive at an overall solution that yields a running design flow management system implemented in the NELSIS CAD Framework. The net result is a CAD system that makes the graphical representation of the design tasks the basis for all design actions. The system provides generic mechanisms applicable to many application domains, thus new tools can be easily incorporated. References 1. R.H. Katz, et al., "Design Version Management," IEEE Design & Test Magazine, pp. 12-22 (Feb 1987). 2. P. van der Wolf and T.G.R. van Leuken, "Object Type Oriented Data Modeling for VLSI Data Management," Proc. 25th ACM/IEEE DAC, pp. 351-356 (1988). 3. P. van den Hamer and M.A. Treffers, "A Data Flow Based Architecture for CAD Frameworks," Proc. ICCAD - 90, pp. 482-485 (1990). 4. A. Casotto, A.R. Newton, and A. Sangiovanni-Vincentelli, "Design Management based on Design Traces," Proc. 27th ACM/IEEE DAC, pp. 136-141 (1990). 5. M. Bushnell and S.W. Director, "Automated Design Tool Execution in the Ulysses Design Environment," IEEE Trans. on Computer-Aided Design 8(3)(March 1989). 6. J.B. Brockman and S.W. Director, "The Hercules CAD Task Management System," Proc. International Conference on CAD, pp. 254-257 (1991). 7. D.C. Liebisch and A. Jain, "Jessi Common Framework Design Management - The Means to Configuration and Execution of the Design Process," Proc. 1st European Design Automation Conference, (September 1992). 8. J.H. ter Bekke, "Database Design (in Dutch)," Stenfert Kroese, (1988). English version: "Semantic Data Modelling", Prentice Hall, ISBN 0-13-80605 0-9. 9. K.O. ten Bosch, P. Bingley, and P. van der Wolf, "Design Flow Management in the NELSIS CAD Framework," Proc. 28th ACM/IEEE DAC, pp. 711-716 (1991). 10. CFI Architecture Tiger Team, "Framework Architecture Reference (Draft Proposal)," Document 91, Version 0.88, (January 20, 1992). 11. Digital Equipment Corporation, PowerFrame Handbook. 1991. 12. P. Bingley and P. van der Wolf, "A Design Platform for the NELSIS CAD Framework," Proc. 27th ACM/IEEE Design Automation Conference, pp. 146-149 (1990).


DAMOCLES: An Observer-Based Approach to Design Tracking Venu Vasudevan, Yves Mathys, Jim Tolar Semiconductor Systems Design Technologies Laboratory, Motorola Inc. Abstract This paper describes the DAMOCLES design tracking system (DTS). Design tracking systems provide the notion of a project-wide design state, and facilities to query the design state. Most current DTS control the designer's environment. DAMOCLES adopts an observer architecture which leads to easy deployment and requires little modification of the design groups mode of operation. References [Cas90] Casotto, A. et al., Design Management based on Design Traces, in 27th Design Automation Conference, pp.136-141, 1990. [CFI91] CFI Tool Execution Log Standards, 1991. [Katz85] Katz,R.H., Information Management for Engineering Design, Springer-Verlag, 1985. [Liu90] Liu,L.C, et al, Design Data Management in a CAD Framework Environment, in the 27th Design Automation Conference, pp.156-161, 1990. [Mg91] The Mentor Graphics 8.0 Design Manager Reference Manual, Mentor Graphics Corporation, 1991. [Vand90] Meta Data Management in the NELSIS framework, in 27th Design Automation Conference, pp. 142146,1990. [Ma92] Yves Mathys, A Graph Browser for Large Directed Graphs, Proceedings of the 1992 ACM/SIGAPP symposium on Applied Computing, pp. 476-481, 1992.


TEST GENERATION FOR DELAY FAULTS IN NON-SCAN AND PARTIAL SCAN SEQUENTIAL CIRCUITS Kwang-Tang Cheng AT&T Bell Laboratories, Murray Hill, NJ 07974 Abstract We address the problem of generating tests for delay faults in non-scan and partial scan synchronous sequential circuits. A recently proposed transition fault model for sequential circuits [1] is considered. In this fault model, a transition fault is characterized by the fault site, the fault type and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. It was observed that neither a comprehensive functional verification sequence nor a sequence with a high stuck-at fault coverage gives a high transition fault coverage for sequential circuits. Deterministic test generation for delay faults is required to raise the coverage to a reasonable level. In this paper, we present a test generation algorithm for this fault model. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck-at fault test generation algorithm with some modifications. The new test generator DATEST (Delay fault Automatic TEST generator for sequential circuits) has been integrated with our sequential circuit delay fault simulator, TFSIM. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. For partial scan circuits, we first describe a test application scheme for detecting transition faults. Modifications on test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle-breaking technique [2]. REFERENCES 1. K.-T. Cheng, "Transition Fault Simulation For Sequential Circuits," submitted to Int'l Test Conf. (Sept. 1992). 2. K. -T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. Computers 39-4, pp. 544-548 (April 1990). 3. G. L. Smith, "Model for Delay Faults Based upon Paths," Proc. IEEE Int'l Test Conf., pp. 342-349 (Nov. 1985). 4. C. J. Lin and S. M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. on Computer-Aided Design, pp. 694-703 (Sept. 1987). 5. J. A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, "Transition Fault Simulation," IEEE Design and Test, pp. 32-38 (April 1987). 6. E. S. Park and M. R. Mercer, "Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit," Proc. IEEE Int'l Test Conf., pp. 1027-1034 (Sept. 1987). 7. V. Iyengar, B. Rosen, and J. A. Waicukauski, "On Computing the Sizes of Detected Delay Faults," IEEE Trans. on Computer-Aided Design, pp. 299-312 (March 1990). 8. K.-T. Cheng, S. Dev adas, and K. Keutzer, "Robust DelayFault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology," Proc. 28th Design Automation Con., pp. 80-86 (June 1991). 9. Y. K. Malaiya and R. Narayanswamy, "Testing for Timing Failures in Synchronous Sequential Integrated Circuits," Proc. of Int'l Test Conf., pp. 560-571 (Oct. 1983). 10. S. Devadas, "Delay Test Generation for Synchronous Sequential Circuits," Proc. Int. Test Con., pp. 144-152 (Sept. 1987). 11. P. Agrawal, V. D. Agrawal, and S. C. Seth, "A New Method For Generating Tests For Delay Faults In NonScan Circuits," Proc. VLSI Design (Jan. 1992).

12. W. T. Cheng, "The BACK Algorithm for Sequential Test Generation," Proc. Int. Conf. Computer Design (ICCD88), Rye Brook, NY, pp. 66-69 (October 1988). 13. O. Bula et al, "Gross Delay Defect Evaluation for a CMOS Logic Design System Product," IBM Journal of Research and Development 34, pp. 325-338 (March/May 1990). 14. R.. Marlett, "EBT: a comprehensive test generation technique for highly sequential circuits," Proc. 15th Design Automation Conf., pp. 332-339 (June 1978). 15. L. H. Goldstein and E. L. Thigpen, "SCOAP: Sandia Controllability/Observability Analysis Program," Proc. 16th Design Automation Conf., pp. 190-196 (June 1980). 16. A. Bhawmik, C. J. Lin, K.-T. Cheng, and V. D. Agrawal„ "Pascant: A Partial Scan and Test Generation System," Proc.1991 Custom Integrated Circuits Conf. (May 1991).


An Efficient Non-Enumerative Method to Estimate Path Delay Fault Coverage Irith Pomeranz and Sudhakar M. Reddy Electrical and Computer Engineering, Department University of Iowa, Iowa City, IA 52242 Abstract A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths. References [1] S. M. Reddy, M. K. Reddy and V. D. Agrawal, "Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits", in Proc. Int. Symp. on Fault-Tolerant Computing, Florida, pp. 44-49, June 1984. [2] G. L. Smith, "Model for delay faults based upon paths," in Proc. Int. Test Conf., pp. 342-349, Nov. 1985. [3] C. J. Lin and S. M. Reddy, "On delay fault testing in logic circuits," IEEE Trans. CAD, pp. 694-703, Sept. 1987. [4] E. S. Park and M. R. Mercer, "Robust and nonrobust tests for path delay faults in a combinational logic," in Proc. Int. Test Conf., pp. 1027-1034, Sept. 1987. [5] M. H. Schultz, F. Fink and K. Fuchs, "Parallel Pattern Fault Simulation of Path Delay Faults", in Proc. Design Autom. Conf., pp. 357-363, June 1989. [6] M. H. Schultz, K. Fuchs and F. Fink, "Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults", in Proc. Int. Symp. on Fault-Tolerant Computing, pp. 44-51, June 1989. [7] T. W. Williams, B. Underwood and M. R. Mercer, "The Interdependence between Delay-Optimization of Synthesized Networks and Testing", in Proc. 28th Design Automation Conf, June 1991, pp. 87-92. [8] S. Even, Graph Algorithms, Computer Science Press, 1979. [9] I. Pomeranz and S. M. Reddy, "An Efficient NonEnumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits", technical report No. 10-1-1991 Revised 7-11-1992, Electrical & Computer Eng. Dept., U. of Iowa. [10] I. Pomeranz, L. N. Reddy and S. M. Reddy, "SPADES: A Simulator for Path Delay Faults in Sequential Circuits", to appear in EURO-DAC '92, Sept. 1992.


COMPACTEST-II: A Method to Generate Compact Two-Pattern Test Sets for Combinational Logic Circuits Lakshmi N. Reddy IBM Corporation, Poughkeepsie, NY -12602 Irith Pomeranz and Sudhakar M. Reddy Dept. of Electrical & Computer Engg., The University of Iowa, Iowa City, IA - 52242 Abstract In this paper, we consider the problem of generating small (compact) test sets for single transition and CMOS stuck-open faults in combinational logic circuits. In addition, we propose that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. Specifically, we address the problem of generating small and comprehensive test sets by considering the CMOS stuck-open and the single transition fault models together. We propose a dynamic test compaction technique for two-pattern tests, which exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. We present experimental results for ISCAS-85 combinational circuits and fully scanned versions of ISCAS-89 sequential circuits to illustrate the efficacy of the proposed test compaction technique. References [1] J. P. Roth, "Diagnosis of Automata Failures: A Calculus and a Method," IBM J. Res. Develop., vol. 10, pp. 278291, July 1966. [2] P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. on Comp., vol. C-30, pp. 215-222, Mar. 1981. [3] H. Fujiwara, and T. Shimono, "On the Acceleration of Test Generation Algorithms," IEEE Trans. on Comp., vol. C-32, pp. 1137-1144, Dec. 1983. [4] T. Kirkland, and M. R. Mercer, "A Topological Search Algorithm for ATPG," Proc. of the 24th ACM/IEEE Design Automation Conference, pp. 502-508, June 1987. [5] M. Schulz, E. Trischler, and T. Sarfert, "SOCRATES: A Highly Efficient Automatic Test Pattern Generation System," IEEE Trans. on CAD., pp. 126-137, Jan. 1988. [6] M. Schulz and E. Auth, "Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques," FTCS-18, pp. 30-35, June 1988. [7] J. Waicukauski, P. Shupe, D. Giramma, and A. Matin, "ATPG for Ultra-Large Structured Designs," 1990 International Test Conference, pp. 44-51. [8] Y. Levendel and P. R. Menon, "Transition Faults in Combinational Circuits: Input Transition Test Generation and Fault Simulation," FTCS-17, June 1987, pp. 278-283. [9] H. Cox and J. Rajski, "Stuck-Open and Transition Fault Testing in CMOS Complex Gates," 1988 International Test Conference, pp. 688-694, Sept. 1988. [10] H. K. Lee and D. S. Ha, "SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits," 1990 Design Automation Conf., pp. 660-666. [11] E.B. Eichelberger and T.W. Williams, "A Logic Design Structure for LSI Testability", Proc.14th Design Automation Conf.,1977, pp. 462-468. [12] I. Pomeranz, L. N. Reddy and S. M. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," 1991 International Test Conf., pp. 194-203. [13] G. Tromp, "Minimal Test Sets for Combinational Circuits," 1991 International Test Conference, pp. 204-209. [14] L. N. Reddy, I. Pomeranz, and S. M. Reddy, "ROTCO: A Reverse Order Test Compaction Technique," to appear in 1992 IEEE EURO-ASIC Conference. [15] R. L. Wadsack, "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits," Bell Sys. Tech. Journal, vol. 57, No. 5, pp. 1449-1474, May-June 1978.

[16] Z. Barzilai and B. Rosen, "Comparison of AC SelfTesting Procedures," 1983 International Test Conference, pp. 89-94. [17] E. Park, B. Underwood, T. Williams and M. Mercer, "Delay Testing Quality in Timing-Optimized Designs," 1991 International Test Conference, pp. 897-905. [18] F. Brglez, D. Bryan and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," International Symposium on Circuits and Systems, pp. 1929-1934, May 1989. [19] J. Gallant, D. Maier, and J. A. Storer, "On Finding Minimal Length Superstring," Journal of Computer and System Sciences, vol. 20, No. l, pp. 50-58, Feb. 1980. [20] J. Waicukauski, E. Lindbloom, B. Rosen and V. Iyengar, "Transition Fault Simulation," IEEE Design & Test, April 1987, pp. 32-38. [21] F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Designs and a Special Translator in Fortran," International Symposium on Circuits and Systems, June 1985. [22] H. K. Lee, D. S. Ha, and K. Kim, "Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits," 26th Design Automation Conference, 1989, pp. 345-350.


Automatic Synthesis of 3D Asynchronous State Machines Kenneth Y Yun, David L. Dill Computer Systems Laboratory, Stanford University, Stanford, CA 94305 Abstract We describe a new automatic synthesis tool (3D) for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation. We present an algorithm for constructing a three-dimensional next-state table, a heuristic for encoding states, and a procedure for generating necessary constraints for exact logic minimization. We demonstrate the effectiveness of the 3D implementation and the synthesis procedure on numerous designs including a large realistic example (Asynchronous Data Transfer Protocol of the SCSI Bus Controller). We estimate the latency (input to output delay) and the cycle time (time required for the circuit to stabilize after the excitation) for all benchmark designs using a 0.8 µm CMOS standard cell library. References [1] Jon G. Bredeson. On multiple input change hazard-free combinational switching circuits without feedback. In 14th Annual Symposium on Switching Theory, Iowa City, Iowa, October 1973. [2] Jon G. Bredeson and Paul T. Hulina. Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits. Information and Control, 20:114-224, 1972. [3] T.-A. Chu. Synthesis of self-timed VLSI circuits from graphtheoretic specifications. Technical Report MITLCS-TR-393, 1987. [4] A. D. Friedman, R. L. Graham, and J. D. Ullman. Universal single transition time asynchronous state assignments. IEEE TOC, C-18(6):541-547,1969. [5] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous circuits. In DAC-91. [6] J. Maneatis and D. Ramsey,1992. Private communication. [7] T. H. Meng. Synchronization Design for Digital Systems. Kluwer Academic, 1990. [8] C. E. Molnar, T.-P. Fang, and F. U. Rosenberger. Synthesis of delay-insensitive modules. In Henry Fuchs, editor, 1985 Chapel Hill Conference on Very Large Scale Integration, pages 67-86. CSP, Inc., 1985. [9] C.W. Moon, P.R. Stephan, and R.K. Brayton. Specification, synthesis, and verification of hazard-free asynchronous circuits. In ICCAD-91. [10] S. M. Nowick and D. L. Dill. Synthesis of asynchronous state machines using a local clock. In ICCD-91. [11] S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In ICCAD92. [12] S. M. Nowick, K. Y. Yun and D. L. Dill. Practical asynchronous controller design. In ICCD-92. [13] Gabriele Saucier. Encoding of asynchronous sequential networks. IEEE TEC, EC-16(6):365-369,1967. [14] S. H. Unger. Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience,1969. [15] P. Vanbekbergen, F. Catthoor, G. Goossens and H. De Man. Optimized synthesis of asynchronous control circuits from graph-theoretic specifications. In ICCAD-90. [16] K. Y. Yun, D. L. Dill and S. M. Nowick. Synthesis of 3D asynchronous state machines. In ICCD-92.


Automatic Gate-Level Synthesis of Speed-Independent Circuits Peter A. Beerel and Teresa H.-Y. Meng Computer Systems Laboratory Stanford University Stanford, CA 94305 Abstract In this paper, we present a CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates. The synthesized circuits are speed-independent; that is, they work correctly regardless of individual gate delays. We present synthesis results for a variety of specifications taken from industry and previously published examples. We compare our speed-independent circuits with those non-speed-independent circuits synthesized using the algorithms described in [1], in which delay elements are added to remove circuit hazards. These synthesis results show that, our circuits are on average approximately 25% faster with an area penalty of only 15%. This work demonstrates that direct synthesis of gate-level speedindependent circuits is not only feasible, but also produces robust and relatively efficient circuits compared to those synthesized with timing constraints. References [1] L. Lavagno, K. Keutzers, and A. Sangiovanni-Vincentelli. "Algorithms for Synthesis of Hazard-Free Asynchronous Circuits". In Proceedings of the 28th ACM/IEEE Design Automation Conference, 1991. [2] Tam-Anh Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, Massachusetts Institute of Technology, 1987. [3] Alain J. Martin. "Programming in VLSI: From Communicating Processes to Delay-Insensitive VLSI Circuits". In C.A.R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming. Addison-Wesley, 1990. [4] D. L. Dill. "Trace Theory for Automatic Hierarchial Verification of Speed-Independent Circuits". ACM Distinguished Dissertations, 1989. [5] David E. Muller and W. S. Bartky. "A Theory of Asynchronous Circuits". In Proceedings of an International Symposium of the Theory of Switching, pages 204-243, 1959. [6] Peter A. Beerel and Teresa H.-Y. Meng. "Semi-Modularity and Testability of Speed-Independent Circuits". Accepted for publication in INTEGRATION, The VLSI Journal. [7] V. I. Varshavky, editor. Self-Timed Control of Concurrent Processes. Kluwer Academic Publishers, Dordrecht, The Netherlands, 1990. [8] Peter A. Beerel and Teresa H.-Y. Meng. "Gate-Level Sythesis of Speed-Independent Asynchronous Control Circuits", 1992. In collection of papers of the ACM International Workshop on Timing Issues in the Specification of and Synthesis of Digital Systems. [9] S.H. Unger. Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience, 1969. [10] Chris Myers and Teresa H.-Y. Meng. "Synthesis of Timed Asynchronous Circuits". To appear in International Conference on Computer Design, ICCD-1992.


SHILPA: A High-level Synthesis System for Self-Timed Circuits Venkatesh Akella Department of Computer Science University of Utah Salt Lake City, UT 84112 Ganesh Gopalakrishnan Department of Computer Science University of Utah Salt Lake City, UT 84112 Abstract SHILPA is system for the high-level synthesis of self-timed circuits. It takes behavioral descriptions in a process+functional language called hopCP and produces a netlist for the Actel FPGA, supported by the VIEWIogic tools. hopCP descriptions are initially translated into an intermediate-form based on hypergraphs called HFG. SHILPA then applies action refinement, which is a technique for transforming HFGs into asynchronous hardware by a series of graphbased transformation rules. Action refinement is characterized by incremental resource allocation and control decomposition. The major contributions of the proposed work are: (i) the source language hopCP which is equipped with shared variables, broadcast channels, and barrier synchronization, that are constructs well suited for system-level hardware specification; (ii) use of flow analysis techniques to optimize resource allocation, to implement guarded commands efficiently, and ensure that shared variables are used "safely" (potentially concurrent reads and writes are detected); (iii) a self timed macromodule library for Actel FPGA implementation. References [Ake92] Venkatesh Akella. An Integrated Framework for the Automatic Synthesis of Efficient Self-timed Circuits from Behavioral Specifications. PhD thesis, Department of Computer Science, University of Utah, 1992. [Bru91] Erik Brunvand. Translating Concurrent Communicating Programs into Asynchronous Circuits. PhD thesis, Carnegie Mellon University, November 1991. [Mar89] Alain J. Martin. Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits. Technical Report Caltech-CS-TR-89-1, Department of Computer Science, California Institute of Technology, 1989. [Sut89] Ivan Sutherland. Micropipelines. Communications of the ACM, June 1989. The 1988 ACM Turing Award Lecture. [vB92] Kees van Berkel. Handshake circuits: an intermediary between communicating processes and VLSI. PhD thesis, Philips Research Laboratories, Eindhoven, The Netherlands, 1992.

ICAD92, Pages 594-598

Accurate Net Models for Placement Improvement by Network Flow Methods KONRAD DOLL, FRANK M. JOHANNES, AND GEORG SIGL Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, 8000 Munich 2, Germany Abstract An efficient iterative improvement procedure for row based cell placement is described with special emphasis on the objective function used to model net lengths. We prove that minimizing net length estimated with our new net model also minimizes the half perimeter of a rectangle enclosing all pins of a net. Contrary to the half perimeter the new objective function allows to compute costs for assigning cells to locations independently for all cells to be placed simultaneously. This offers our algorithm an important advantage compared to other iterative improvement techniques: Many cells can be placed simultaneously by formulating placement as a network flow problem. Our algorithm is superior to TimberWolfSC 5.4, which minimizes the half perimeter. This is shown on benchmark circuits with up to 14% smaller area computed in one order of magnitude less cpu-time. References [1] B. Preas and M. Lorenzetti, Physical Design Automation of VLSI Systems. Benjamin/ Cummings, 1988. [2] T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. John Wiley & Sons, 1990. [3] K. Doll, F. Johannes, and G. Sigl, "Domino: Deterministic placement improvement with hill-climbing capabilities," Proc. VLSI, pp. 3b.1.1-3b.1.10, 1991. [4] L. Steinberg, "The backboard wiring problem: A placement algorithm," SIAM Review, pp. 37-50, 1961. [5] S. B. Akers, "On the use of the linear assignment algorithm in module placement," Proc. 18th DAC, pp. 137-144, 1981. [6] R. Kling and P. Banerjee, "ESP: Placement by simulated evolution," IEEE Trans. on CAD, pp. 245-256, 1989. [7] A. Srinivasan, K. Chaudhary, and E. S. Kuh, "Ritual: A performance driven placement algorithm for small cell ICs," Proc. ICCAD, pp. 48-51, 1991. [8] C. Sechen and K. W. Lee, "An improved simulated annealing algorithm," Proc. ICCAD, pp. 478-481, 1987. [9] P. Suaris and G. Kedem, "An algorithm for quadrisection and its application to standard cell placement," IEEE Trans. on CAS, pp. 294-303, 1988. [10] J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich, "Gordian: VLSI placement by quadratic programming and slicing optimization," IEEE Trans. on CAD, pp. 356-365, 1991. [11] G. Sigl, K. Doll, and F. Johannes, "Analytical placement: A linear or a quadratic objective function?," Proc. 28th DAC, pp. 427-432, 1991. [12] K. Doll, F. Johannes, and G. Sigl, "Placement improvement by network flow methods," Proc. International Workshop on Layout Synthesis, pp. 179-188, 1992. [13] K. Kozminski, "Benchmarks for layout synthesis," Proc. 28th DAC, pp. 265-270, 1991. [14] K. Kozminski, "TimberWolf Hunt Results," International Workshop on Layout Synthesis MCNC, 1992. [15] "VPNR users guide," MCNC Technical Report, Microelectronics Center of North Carolina, 1988.


Three-Phase Chip Planning - An Improved Top-Down Chip Planning Strategy Bernd Schürmann, Joachim Altmeyer, Gerhard Zimmermann University of Kaiserslautern D-6750 Kaiserslautern, Germany Abstract The most important precondition for top-down chip planning is a good area estimation. However, each estimation has tolerances which result in differences of the estimated shapes in the floorplan and the final layouts. This paper introduces an improved top-down chip planning method that reduces the effects of these deviations. In a fully recursive approach, each cell is planned several times with different presumptions. Bottom-up adjustment steps use refined shape functions instead of rigid dimensions. Although we perform such bottom-up adjustment steps, the general direction is top-down. The convergence of our procedure can be ensured. Within the paper, we describe our method in detail and provide some experimental results. Several real big test designs (the largest example has nearly 300.000 standard cells) have been performed with our PLAYOUT design system to compare the pure top-down approach with our new method. References [1] W.W. Dai, B. Eschermann, E.S. Kuh, M. Pedram, "Hierarchical Placement and Floorplanning in Bear", Trans. on CAD, 1989 [2] K. Glasmacher, A. Hess, G. Zimmermann, "A Genetic Algorithm for Global Improvement of Macrocell Layouts", Proc. Int. Conference on Computer Design, Cambridge, 1991 [3] K. Glasmacher, G. Zimmermann, "Chip Assembly in the PLAYOUT VLSI Design System", Proc. European Design Automation Conference, Hamburg, 1992 [4] A. Herrigel, "GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design", Proc. Int. Conference of Computer Aided Design, 1990 [5] F.J. Kurdahi, A.C. Parker, "Techniques for Area Estimation of VLSI Layouts", Trans. on CAD, 1989 [6] D. LaPotin, S. Director, "Mason A global floorplanning approach for VLSI design", Trans. on CAD, 1986 [7] T. Lengauer, R. Mueller, "A Robust Framework for Hierarchical Floorplanning with Integrated Global Wiring", Proc. Int. Conference of Computer Aided Design, 1990 [8] P. Marwedel, "A New Synthesis Algorithm for the MIMOLA Software System", Proc. 23rd Design Automation Conference, 1986 [9] C. Masson, R. Escassut, D. Barbier, et. al., "Object-Oriented Lisp Implementation of the CHEOPS VLSI Floorplanning and Routing System", Proc. 28th Design Automation Conference, 1991 [10] R. Otten, "Efficient Floorplan Optimization", Proc. Int. Conf. on Computer Design, Port Chester, 499-503,1983 [11] M. Pedram, B. Preas, "A Hierarchical Floorplanning Approach", Proc. Int. Conference on Computer Design, Cambridge, 1990 [12] C. Sechen, K. Lee, "A Improved Simulated Annealing Algorithm for Row-Based Placement", Proc. Int. Conference of Computer Aided Design, 1987 [13] E. Siepmann, "A Data Management Interface as Part of the Framework of an Integrated VLSI-Design System", Proc. Int. Conference on Computer-Aided Design, 1989 [14] B. Schuermann, "A 280.00 Standard Cells Test Design - First Experiences with the PLAYOUT Top-Down Design System", Proc. Int. Workshop on Layout Synthesis, Research Triangle Park, NC, 1992 [15] B. Schuermann, J. Altmeyer, G. Zimmermann, "Three-Phase Chip Planning", technical report, University of Kaiserslautern,1992 [16] B. Schuermann, G. Zimmermann, "Estimation of Wiring Area for Hierarchical Design", Proc. Int. Workshop on Layout Synthesis, Research Triangle Park, NC, 1992

[17] W. Swartz, C. Sechen, "New Algorithms for the Placement and Routing of Macro Cells", Proc. Int. Conference of Computer Aided Design, 1990 [18] T.-C. Wang, D.F. Wong, "An Optimal Algorithm for Floorplan Area Estimation", Proc. 27th Design Automation Conference, 1990 [19] C.-S: Ying, J.S.-L. Wong, "An Analytical Approach to Floorplanning for Hierarchical Building Blocks", Trans. on CAD, 1989 [20] G. Zimmermann, "A New Area Shape Function Estimation Technique for VLSI Layouts", Proc. 25th Design Automation Conference, 1988 [21] G. Zimmermann, "PLAYOUT - A Hierarchical Design System", Information Processing 89, G.X. Ritter (ed.), Elsevier Science Publishers BX (North Holland), IFIP, 1989


Area Minimization for General Floorplans Peichen Pan and C. L. Liu Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL Abstract Two methods for the area minimization problem in floorplanning are presented. These methods can be viewed as generalizations of Stockmeyer's algorithm [7] in the sense that they reduce to Stockmeyer's algorithm for floorplans that are slicing. Our methods can also be applied to general floorplans. Compared with the branch-and-bound algorithm [9] which is enumerative in nature and does not have any non-trivial performance bound for general floorplans, our methods are provably better than exhaustive methods for all the floorplans we experimented with. References [1] Chong, K. and S. Sahni, Optimal Realizations of Floorplans. TR 90-20, CS Dept, University of Minnesota, 1990. [2] Lengauer, T., Combinatorial Algorithms for Integrated Circuit Layout: John Wiley & Sons, New York, 1990. [3] Liu, C. L., Introduction to Combinatorial Mathematics. McGraw-Hill Book Company, New York, 1968. [4] Otten, R.H.J.M., Graphs in Floorplan Design. Intl. Journal of Circuit Theory and Appl., Vol 16, 391-410,1988. [5] Pan, Peichen and C. L. Liu, Unpublished notes. 1991. [6] Pan, Peichen and C. L. Liu, Manuscript. 1992. [7] Stockmeyer, L., Optimal Orientations of Cells in Slicing Floorplan Designs. Info. and Control, Vol 59, 91-101,1983. [8] Wang, T. and D.F. Wong, An Optimal Algorithm for Floorplan Area Optimization. Proc. 27th DAC, 180186,1990. [9] Wimer, S., I. Koren, and I. Cederbaum, Optimal Aspect Ratios of Building Blocks in VLSI. IEEE Trans. on CAD, V618, No 2,139-145,1989. [10] Wong, D.F. and P.S. Sakhamuri, Efficient Floorplan Area Optimization. Proc. 26th DAC, 586-589,1989.


Behavioral Synthesis for Testability Chung-Hsing Chen, Daniel G. Saab Center for Reliable and High-performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801 Abstract In this paper, a synthesis for testability approach is presented. In this approach we select test points or flip-flops to be used in Test Point Insertion or Partial Scan to enhance circuit testability. The selection is based on circuit behavioral information rather than low level structural description. This allows Test Point Insertion or Partial Scan usage on circuits described as interconnection of high level modules. In this paper, we also propose Test Statement Insertion as an alternative to Test Point Insertion and to Partial Scan. The major advantage of using Test Statement Insertion is less pin count and lower test application time overhead than Test Point Insertion and Partial Scan. Our tool has been implemented in a computer program. References [1] William, T.W. and Parker, K.P., "Design for Testability - A Survey," Proc. o f IEEE, Vol. 71, No. 1, pp. 311325,1983. [2] Abadir, M.S., "Testability Insertion Guidance Expert System (TIGER)," Proc. ICCAD, pp. 562-565, 1989. [3] Breuer, M.A., Gupta, R. and Gupta, R., "AI Aspects of TEST : A System for Designing Testable VLSI Chips," IFIP Workshop on Knowledge-Based Systems for Test and Diagnosis, pp. 28- 75 1988. [4] Hayes, J.P., "On Modifying Logic Networks to Improve their Diagnosability," IEEE Trans. Comput., Vol. C-23 pp.56-62 1974. [5] Trischler, E., "Incomplete Scan Path with an Automatic Test Generation Methodology," Proc. ITC, pp.153162,1980. [6] Williams, M.J.Y., and Angel, J.B., "Enhancing Tstability of Large Scale Integrated Circuits via Test Points and Additional Logic"' IEEE Trans. Comput., Vol. C-22 No. 1, pp 46 –60, 1073. [7] Krishnamurthy, B., "A Dynamic Programming Approach to the Test Point Insertion Problem" Proc. 24th Design Automation Conf., pp. 695-705, 1987. [8] Pomeranz, I. and Kohavi, Z., "Polynomial Complixity. Algorithms for Increasing the Testability of Digital Circuist by Testing-Module Insertion,' IEEE Trans. Comput, vol. 40 No. 11, pp. 1198-1212 Nov. 1991. [9] Chickermane, V. and Patel, J.H., "An Optimization Based Approach to the Partial Scan Design Problem," Proc. ITC, pp. 377-386, 1990. [10] Agrawal, V.D., Chang, K.D., Johnson, D.D. and Lin T., "A Complete Solution to the Partial Scan Problem," Proc. ITC, pp. 44-51,1987. [11] Ma, H.-K. T., Devadas, S., Newton, A.R. and Sangiovanni-Vincentelli, A., "An Incomplete Scan Design Approach to Test Generation for Sequential ,Machines," Proc. ITC, pp. 730-734 1988. [12] Cheng, K.T. and Agrawal, V.D., "An Economical Scan Design for Sequential Logic Test Generation, Proc. 19th Int l. Symp. on Fault-Tolerant Compt., pp. 28-35, 1989. [13] L.Goldstein and E. Thigpen, "SCOAP:Sandia Controllability/ Observability Analysis Program," Proc. of DAC, pp. 190-196, June 1980. [14] Chen, C.-H., Wu, C. and Saab, D., "BETA: BEhavioral Testability Analysis," Proc. ICCAD, pp. 202205,1991.


Behavioral Synthesis for Easy Testability in Data Path Scheduling Tien-Chien Lee, Wayne H. Wolf, and Niraj K. Jha Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 Abstract This paper presents a data path scheduling algorithm to improve testability without a priori assuming any particular test strategy. We introduce a scheduling heuristic for easy testability, based on our previous work [15] on data path allocation for testability. We then develop a mobility path scheduling algorithm to implement this heuristic while also minimizing area. Experimental results on benchmark and example circuits show high fault coverage, short test generation time, and little or no area overhead. References [1] P. G. Paulin, J. P. Knight, E. F. Girczyc, "HAL: A multi-paradigm approach to automatic data path synthesis," in Proc. DAC, pp. 263-270,1986. [2] A. C. Parker, J. T. Pizarro, M. Milnar, "MAHA: A program for datapath synthesis," in Proc. DAC, pp. 461-466, 1986. [3] B. M. Pangrle and D. D. Gajski, "Slicer: A state synthesizer for intelligent silicon compilation," in Proc. ICCAD, pp. 536-541, 1987. [4] C. A. Papachristou, "Rescheduling transformations for high-level synthesis," in Proc. ISCAS, pp. 766-769, 1989. [5] A. Ghosh, S. Devadas, A. R. Newton, "Test generation for highly sequential circuits," in Proc. ICCAD, pp. 362365, 1989. [6] M. C. McFarland, A. C. Parker, R. Camposano, "The high-level synthesis of digital systems," Proc. IEEE, vol. 78, pp. 301-318, Feb. 1990. [7] K.-T. Cheng and V. D. Agrawal, "Synthesis of testable finite state machine," in Proc. ISCAS, pp. 31143115,1990. [8] L. Avra and E. J. McCluskey, "Behavioral synthesis of testable systems with VHDL," in Proc. COMPCON Spring'90, pp. 410-415,1990. [9] L. Avra, "Allocation and assignment in high-level synthesis for self-testable data paths," in Proc. ITC, pp. 463472,1991. [10] R. Camposano and W. H. Wolf, High-Level VLSI Synthesis, Kluwer Academic Publishers, 1991. [11] C. A. Papachristou, S. Chiu, H. Harmanani, "A data path synthesis method for self-testability designs," in Proc. DAC, pp. 378-384, 1991. [12] E. M. Sentovich et al., "Sequential circuit design using synthesis and optimization," to be presented at ICCD; 1992. [13] G. Krishnamoorthy and J. A. Nestor, "Data path allocation using an extended binding model," in Proc. DAC, pp. 279-284, 1992. [14] A. Mujumdar, K. Saluja, R. Jain, "Incorporating testability considerations in high-level synthesis," in Proc. FTCS, pp. 272-279, 1992. [15] T.-C. Lee, W. H. Wolf, N. K. Jha, J. M. Acken, "Behavioral synthesis for easy testability in data path allocation," to be presented at ICCD, 1992.


A Comparative Study of Design for Testability Methods Using High-Level and Gate-Level Descriptions Vivek Chickermane, Jaushin Lee, and Janak H. Patel Center for Reliable and High-Performance Computing, University of Illinois at Urbana-Champaign, Urbana, IL Abstract In this paper, we first present a comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits. Based on the examination of the results we propose DFT techniques that use high-level circuit information. The results obtained after partial scan selection by a high-level DFT tool are compared with results obtained by a gate-level partial scan tool. This detailed comparative study demonstrates that a DFT tool can make a more effective selection of partial scan flip flops by exploiting the high-level circuit information, and by accurately predicting the hard-to-test areas of a circuit. References [1] B. T. Murray and J. P. Hayes, "Hierarchical test generation using precomputed tests for modules," Proc. Int. Test Conference, pp. 221-229, September 1988. [2] K. Roy and J. A. Abraham, "High-level test generation using data flow descriptions," Proc. European Design Automation Conference, pp. 480-484, March 1990. [3] J. Lee and J. H. Patel, "An Instruction Sequence Assembling Methodology for Testing Microprocessors," Proc. Int. Test Conference, October 1992. [4] T. M. Niermann and J. H. Patel, "HITEC: a test generation package for sequential circuits," Proc. European Conference on Design Automation, pp. 214-218, February 1991. [5] V. Chickermane, J. Lee, and J. H. Patel, "Design for testability using architectural descriptions," Proc. Int. Test Conference, September 1992. [6] R. Lipsett, C. Schaefer, and C. Ussery, VHDL: Hardware Description and Design. Kluwer Academic Press: Norwell, MA, 1989. [7] M. Abadir and M. A. Breuer, "A knowledge-based system for designing testable VLSI chips," IEEE Design and Test, pp. 56-68, August 1985. [8] R. Gupta, Advanced Serial Scan Design for Testability. Ph.d Thesis, Dept of Electrical Engineering, University of Southern California: Los Angeles, CA, 1991. [9] J. Lee and J. H. Patel, "Hierarchical test generation under intensive global functional constraints," Proc. Design Automation Conference, pp. 261-166, June 1992. [10] V. Chickermane and J. H. Patel, "A fault-oriented partial scan design approach," Proc. Int. Conference on Computer-Aided Design, pp. 400-403, November 1991.


Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes Steven M. Nowick, David L. Dill Computer Systems Laboratory, Stanford University Stanford, CA 94305 Abstract This paper describes a new method for exact hazard free logic minimization of Boolean functions. Given an incompletelyspecified Boolean function, the method produces a minimal sumof-products implementation which is hazard -free for a given set of multiple-input changes, if such a solution exists. The method is a constrained version of the Quine-McCluskey algorithm. It has been automated and applied to a number of examples. Results are compared with results of a comparable non-hazard-free method (espresso-exact). Overhead due to hazard-elimination is shown to be negligible. References [1] V Akella and G. Gopalakrishnan. Shilpa: a high-level synthesis system for self-timed circuits. In ICCAD-1992. [2] P.A. Beerel and T. Meng. Automatic gate-level synthesis of speed-independent circuits. In ICCAD-1992. [3] J. Beister. A unified approach to combinational hazards. IEEE Transactions on Computers, C-23(6),1974: [4] J.G. Bredeson. Synthesis of multiple input-change hazard-free combinational switching circuits without feedback. Int. J. Electronics, 39(6):615-624,1975. [5] J.G. Bredeson and P.T. Hulina. Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits. Information and Control, 20:114-224,1972. [6] E. Brunvand and R. F Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD-1989. [7] T. A. Chu. Synthesis of self-timed vlsi circuits from graph-theoretic specifications. Technical Report MTT-LCSTR-393,1987. [8] E.B. Eichelberger. Hazard detection in combinational and sequential switching circuits. IBM J. Res. Develop., 9(2):90-199,1965. [9] R.K. Brayton et al. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic, 1984. [l0] J. Frackowiak. Methoden der analyse and synthese von hasardarmen schaltnetzen mit minimalen kosten i. Elektronische Informanonsverarbeitung und Kybernetik, 10(2/3):149-187,1974. [11] D.S. Rung. Hazard-non-increasing gate-level optimization algorithms. In ICCAD-1992. [12] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous circuits. In DAC-91. [13] Alain J. Martin. Compiling communicating processes into delay-insensitive vlsi circuits. Distributed Computing, 1:226-234,1986. [14] EJ. McCuskey. Introduction to the Theory of Switching Circuits. McGrawHill, 1965. [15] EJ. McCluskey. Logic Design Principles. Prentice--Hall, 1986. [16] P.C. McGeer and R.K. Brayton. Hazard prevention in combinational circuits. In Hawaii Int. Conf. on System Sciences 1990. [17] R.B. McGhee. Some aids to the detection of hazards in combinational switching circuits. IEEE TOC (Short Notes), C-18:561565, 1969. [18] Teresa H. -Y. Meng, Robert W. Brodersen, and David G. Messerschmitt. Automatic synthesis of asynchronous circuits from high-level specifications. IEEE Transactions on CAD, 8(11):1185-1205, November 1989. [19] C.W. Moon, P.R. Stephan, and R.K. Brayton. Synthesis of hazard-free asynchronous circuits from graphical specifications. In ICCAD-1991. [20] C. Myers and T. Meng. Synthesis of timed asynchronous circuits. In ICCD1992. [21] S. M. Nowick and D. L. Dill. Synthesis of asynchronous state machines using a local clock. In ICCD-1991. [22] S.M. Nowick and D.L. Dill. Automatic synthesis of locally-clocked asynchronous state machines. In ICCAD1991. [23] Richard Rudell. Logic synthesis for vlsi design. Technical Report UCB/ERL M89/49, Berkeley, 1989. [24] S.H. Unger. Asynchronous Sequential Switching Circuits. New York: WileyInterscienee, 1969.

[25] M.L. Yu and P.A. Subrahmanyam. A path-oriented approach for reducing hazards in asynchronous designs. In DAC-1992. [26] Kenneth Yun, David Dill, and Steven M. Nowick. Synthesis of 3d asynchronous state machines. In ICCD1992.


Hazard-non-increasing gate-level optimization algorithms David S. Kung IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 Abstract This paper presents hazard-non-increasing optimization algorithms. These are optimizations on gatelevel logic without introduction of any further static nor dynamic hazards. Proofs are given for general theoretical results on hazard-non-increasing transformations which serve as the basis for these algorithms. The algorithms in this paper substantially augment the set of proven hazardnon-increasing optimization techniques in the literature. These algorithms are useful for hazard free implementations of asynchronous designs. References [1] S. M. Nowick and D. L. Dill, "Automatic synthesis of locally-clocked asynchronous state machines," in Proceedings of the ICCAD, pp. 318-321, 1991. [2] T. A. Chu, "Synthesis of self-timed control circuits from graphs: An example," in Proceedings of the ICCD, pp. 565-571, 1986. [3] S. H. Unger, Asynchronous Sequential Switching Circuits. Wiley Interscience, 1969. [4] L. Lavagno, K. Keutzer, and A. SangiovanniVincentelli, "Synthesis of verifiably hazard-free asynchronous control circuits," in Advanced research in VLSI 1991: U C Santa Cruz, pp. 87-102, 1991. [5] G. Fantauzzi, "An algebraic model for the analysis of logic circuits," IEEE transactions on Computers, vol. C23, pp. 576-581, 1974. [6] L. Berman and R. F. Damiano, "Dual global flow," in Proceedings of the International Workshop on Logic Synthesis, 1991. [7] C. L. Berman and L. H. Trevillyan, "Global flow optimization in automatic logic design," IEEE transactions on Computer Aided Design, vol. 10, pp. 557-564, 1991. [8] D. S. Kung, "On hazard-non-increasing transformations," Tech. Rep. RC 18153, IBM Research Division, March 1992. To be submitted to the IEEE transactions in CAD. [9] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "MIS: A multiple-level logic optimization system," IEEE Transactions on Computer-Aided Design, vol. CAD-6, November 1987.

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