components. Meanwhile, the avionics industry has endorsed a new approach for systems design, namely the. Integrated Modular Avionics (IMA) [1,2]. The IMA.
MINIATURIZED GENERAL-PURPOSE ARCHITECTURE FOR I/O SIGNALS' HANDLING IN AEROSPACE APPLICATIONS Mohamed F. Younis, Honeywell Advanced Systems Technology Group Columbia, MD James W. Ernst, Thomson multimedia, Indianapolis, IN Abstract Typically handling of input and output (I/O) is one of the most complex and costly parts of an electronic control system. As signal characteristics vary significantly among applications, the handling of the signals becomes unique to the application. In aerospace applications the I/O design tends not to be portable among different aircraft, or even among the different control units on the same aircraft. With the need for a new I/O design for each control unit, the handling of I/O becomes a major cost factor. This paper presents a novel general-purpose architecture that enables the reuse of I/O designs across multiple applications and facilitates the handling of a wide variety of signal characteristics. The architecture unifies the interface to both signals and data bus so that the same design can fit different applications. Many of the architectural building blocks are integrated into a miniaturized implementation in order to reduce the cost, weight and volume for the aircraft system. The design of a novel chip for re-configurable signal conditioning and conversion is also discussed.
1. Introduction Currently the handling of input and output signals is a major cost for aerospace products. Since signal characteristics vary among various aircraft, product-specific design is usually prepared to handle I/O. Such diverse designs do not allow reuse and impose additional costs to develop a new I/O design for each aircraft and even each subsystem on the same aircraft. Moreover, many types of chipsets and components are being used which impose significant technical risk and development delays while designers gain expertise with these components. Meanwhile, the avionics industry has endorsed a new approach for systems design, namely the Integrated Modular Avionics (IMA) [1,2]. The IMA approach encourages the use of general-purpose
basic components as a means of standardizing hardware building blocks in order to achieve high levels of reusability. In addition, functional integration is at the core of the IMA concept. Integration can reduce the size and weight of avionics and thus enhances the efficiency of aircraft operation. Following the IMA guidelines, the cost of both development and maintenance is expected to decrease because of mass production of the building blocks, lower levels of spares, and reduced certification costs. While application software and system interconnect received significant attention [3], very little progress has been on the I/O side. This paper addresses portability of the I/O design in aerospace applications. The paper describes a novel configurable general-purpose I/O architecture (GPIO) that enables the reuse of I/O hardware across multiple applications. The architecture integrates many generic capabilities for signal conditioning, conversion and processing to accommodate the various applications' requirements. The architecture unifies the interface to both signals and data bus so that the same design can fit different applications. The signal interface is configurable to handle combinations of analog and discrete signals both input and output for most aircraft subsystems. A two-layer bus interface is used to limit the impact of a change in bus specifications on the I/O design. Many of the architectural building blocks are integrated to allow for a miniaturized implementation. A novel chip is developed which facilitates reconfiguration and the handling of a wide variety of signal characteristics. Interface ports can be configured to allow signals to be processed independently from each other with support for both single-ended and differential input signals. The chip performs a wide variety of signal conditioning, coupled with analog-to-digital and digital-to-analog conversion. Such an integrated approach reduces chip count, board space and connections and thus increases design reliability. 1
2. GPIO Conceptual Architecture The main features of the architecture are to be both configurable and miniaturized. Flexibility in configuration is being addressed at the core of the design. For an I/O design to be general-purpose it has to handle a variety of signal voltage ranges and signal types whether they are discrete or analog, input or output, single-ended or differential. In addition the design has to be capable of interfacing with multiple bus types. Miniaturization, as discussed later in the paper, is achieved by combining multiple functional blocks into one device during the detailed design and by using microelectronics in the implementation. A high-level functional block diagram for the GPIO architecture is shown in Figure 1. Some of the blocks do not exist in traditional I/O design and are included to allow reconfiguration of the GPIO to suit a wide variety of applications. The architecture can be partitioned into three main parts, signal conditioning, signal processing and bus interfacing. The signal conditioning part configures the signal interface for either input or output, differential or single-ended. It scales the input and
Signal Conditioning
Bus Interface
DSP Controller
DAC
Bus Dependent Interface Unit
Bus Independent Interface Logic
ADC Memory
. . .
Programmable Signal Conditioning and Signal Control
. . .
Signal Processing
Control Signal Specific Conditioning
. . .
High Current and/or Voltage Signals
The chip can standardize the I/O hardware for aircraft and thus significantly reduce the cost, size and weight for aircraft electronic control systems. There have been few sporadic attempts to tackle the problem of re-configurable signal interface from the technological rather than the functional point-of-view [4,5,6]. Such work focuses on mixed (analog and digital) signal microelectronic design methodology but not on the aspect of system level functionality and configuration. On the other hand, there has been some progress made towards standardizing (IEEE 1451) the interface between the signal/application processor and the signal conditioning and conversion logic [7,8]. That and similar work are steps in the right direction, although they are focused only on the smart sensor domain. We are not aware of other work that comprehensively addresses portability of I/O design from end-to-end, compared to the approach presented in this paper. The next section describes the features of the GPIO architecture and its building blocks. Section 3 discusses the miniaturization approach for a GPIObased design. Prototyping efforts are summarized in section 4. Section 5 concludes the paper.
Figure 1: GPIO Conceptual Design output signals to the full range of the analog-todigital and digital-to-analog converters respectively. It is also responsible for shaping output signals to satisfy the requirements of the external environment. The signal processing circuit includes converters between digital and analog format and the digital processing logic that performs frequency filtering, transformation etc. The bus interface logic handles communication between the mission computer and the GPIO. The following subsections explain the various blocks.
2.1 Signal Conditioning Signal characteristics such as the voltage range vary from one input signal to another and the same also for output signals. Therefore, signals have to be conditioned to fit a unified set of characteristics that the signal conversion logic is designed to handle. In addition, differential input signals will be adjusted to a local reference to be dealt with as single-ended signal in the signal processing stage. Thus signal conditioning is responsible for shaping input signals to a format suitable for handling by the analog-todigital converter and shaping output signals to satisfy the requirements of the external environment. As depicted in Figure 1, signal conditioning is broken down into two blocks. The first is the "High Current and/or Voltage Signals and Signal Specific Conditioning" block, which pre-conditions the large signals to within a tolerable range and creates the correct matching characteristic of special-type signals. Signals that require this type of conditioning are not common especially when high voltage electronics are used. Therefore, this block is 2
included as optional. The techniques applied for this type of conditioning varies too widely and is outside the scope of this paper. At this point, all the high voltage signals have been scaled to within a reasonable bound, but the small signals (some perhaps in the milllivolts range) are still not to the full range of the ADC or DAC. Also, there is no control over the DAC driving a potential input. The "Programmable Signal Conditioning and Signal Control" block addresses both issues. This block allows programmable gain amplification to scale differential or single-ended input signals to the full range of analog-to-digital converter. Such scaling step produces the maximum resolution for a number of signal ranges using a single range converter. Similarly output signals will be scaled to the full range of the digital-to-analog converter and fulfill expected signal characteristics. In addition, this block controls port configuration. It enables or disables the output driver of a signal and configures the interface with other functional blocks such as the conversion logic. It is worth noting that this block interfaces with a mix of analog and discrete, single-ended and differential input and output signals that all need to be sorted out and dealt with accordingly. There is no predefined location for any such class of signal within this block, although the implementation of this block may impose a minor restriction on the placement of differential input signals and true differential output signals. This block will be discussed in details in section 3.1.
2.2 Signal Processing The most important aspect of signal handling is to process the data represented by the signal. Data encoded in an input signal has to be extracted from a carrier signal and sent to the mission computer that runs the application. Signal processing is mostly done digitally using quantized values of discrete signals and samples of analog signals. Therefore, conversion between analog and digital signal formats is essential to I/O handling. In Figure 1, the DAC, ADC, DSP Controller, Memory and Control blocks can be regarded as the core of the signal processing. The Digital to Analog Converter (DAC) and Analog to Digital Converter (ADC) are where digital meets analog and raw values are converted
from a digital representation to a voltage level and vice versa. The granularity must be very fine to acquire the precision outlined in the application requirements. All conversions must be fast in order to meet the timing goals and refresh rates also mandated by the performance goals. The implementation could be handled a number of ways. Usually multiple signals are multiplexed per each ADC or DAC. The number of ADC (DAC) depends on the number of input (output) signals and the multiplexing ratio. The Digital Signal Processing (DSP) Controller block is shown as being optional. This section is where all digital filtering and manipulation take place. Having a DSP controller on board enables the manipulation of time critical information efficiently and reduces traffic over the system bus. However, if desirable, raw data of signal samples can be sent via the bus to the mission computer for processing. Most of the recent I/O designs include a DSP. In the balance of the paper, a DSP Controller is assumed to be a part of the GPIO. The overall role of Memory and Control blocks is simply to facilitate the exchange of data between the converters and the DSP Controller and/or the Bus-independent Interface Logic by mapping of the internal registers of ADC, DAC and Signal Conditioning and Control blocks into appropriate memory addresses. The mapping allows reconfiguration and access to I/O data registers from the mission computer. The Memory and Control functional block could be merged with either the Bus-independent Interface Logic or the DSP Controller. The control block also serves as a placeholder for any support logic needed to keep the DSP Controller performing optimally, e.g. a sequencer to upload the data from the ADC to memory.
2.3 Bus Interface Logic Since design portability is the main goal of the GPIO, the capability of interfacing with multiple types of buses is essential. To limit the impact of the bus selection on the design, interfacing with the bus is to be divided into two layers. The first layer is the Bus-dependent Unit, a controller that handles the bus-specific signals and communication protocol. The second layer is the Bus-independent Interface Logic that creates a bound around the
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3. Miniaturized GPIO Design There are a few blocks in Figure 1 that seem to lend themselves to being merged with other functional blocks. This section outlines an approach that includes two mergers. One implies a chip for signal conditioning and conversion and another simply accounts for logical control. Such integration is depicted in Figure 2. Comparing Figure 2 with Figure 1, the "Programmable Signal Conditioning and Signal Control" block has been integrated with the ADC and DAC, along with some of the functionality of the "Memory Control" block. The integration creates a new block for Signal Conditioning and Conversion. In addition, the Bus-independent Interface Logic and the rest of the Memory Control have been merged with the DSP Controller, forming the DSP, Configuration and Bus Controller block. This is the logical migration path since the
Bus Dependent Interface Unit
DSP, Configuration and Bus Controller
. . .
. . .
Signal Conditioning and Conversion
. . .
High Current and/or Voltage Signals and Signal Specific Conditioning
GPIO functionality and provides a defined port to be bridged to a targeted bus. The concept is similar to a daughter board interface (e.g. a PCI bridge for a PMC interface [9]). The Bus-independent logic is an abstract layer, which may be implemented as a programmable device or in software. In this layer all data transfers from/to the DSP are wrapped into one singular communication protocol, regardless the bus selection. The Bus-independent logic will be programmed with bus-specific data format and protocol to interface with Bus-dependent Interface Unit and will be responsible for data reformatting and protocol mapping in order to be compatible with the DSP interface. In this way, regardless of what system bus is being interfaced to, the information will be transferred to the DSP processor in the same format. Thus, this layer hides the bus-specific interface details from the other components so that they do not have to be modified as a result of a bus type change. Miniaturization is one of the fundamental goals of the GPIO approach. Increasing the number of signals handled by an I/O unit will have large impact on the cost, weight and volume of aircraft. Such impact will be even more significant for future airspace vehicles given the large increase in advanced sensors, navigation, and safety equipment these vehicles are expected to have onboard [10,11,12].
Figure 2: A miniaturized GPIO configuration control and logic can be easily merged with the DSP Controller instead of making it a separate entity. The implementation of the combined DSP, Configuration and Bus Controller is previously addressed in the literature, e.g. [13] and will not be further discussed in this paper. A miniaturized implementation of the Signal Conditioning and Conversion block can be realized as an ASIC (Application Specific Integrated Circuit) using mixed-signal design microelectronics. A high-level functional block diagram for the Signal Conditioning and Conversion chip is shown in Figure 3. The main features of the chip are to be both highly configurable and capable of performing conditioning and type-conversion for a wide range of signal characteristics. The chip design handles any combination of signals configured as input or output, discrete or analog. Signals can be configured and processed independently from each other. Input signals can be single-ended or differential. Each port has a two-wire interface to accommodate differential signals. The chip interfaces with other components on the I/O handler via a digital local bus. The following is a brief explanation for the various blocks: •
Signal Conditioning’s Cells: Each cell interfaces with a signal and performs signal conditioning according to the type of the signal. Each cell can be configured to fit the type and characteristics of a particular signal, e.g. input or output. The cell includes a programmable gain operational amplifier to scale the signal to
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S ig n a l c o n d itio n in g C e ll
A n a lo g M u lt ip le x e r
S a m p le & H o ld L o g ic
ADC
D ig ita l D ecoder
S y s te m A D C r e g is te r file
#1
2
S ig n a l c o n d itio n in g C e ll
In p u t r e g is te r f ile
#2
2
Address Bus
2
(N x P )
S equencer & C o n tr o l
S ig n a l c o n d itio n in g C e ll
U s e r D e fin e d C o n tr o l
Data Bus
#3
O u tp u t r e g is te r f ile (N x P )
S a m p le & H o ld L o g ic
2
A n a lo g D eco der
DAC
D ig it a l M u lip le x e r
S y s te m D A C r e g is te r f ile
User C o n fig u r a t io n R e g is te r file (N x P )
S ig n a l c o n d itio n in g C e ll # N
Figure 3: Block diagram for the signal conditioning and conversion chip
•
• • • • •
the full range supported by the ADC or DAC while maintaining signal integrity and accuracy. In addition, the cell has filtering and testing capabilities. The cell is explained in detail in section 3.1. ADC and DAC: There can be a number of converters; each multiplexed to a subset of signals with an overall sampling or refresh rate for each signal. The number of required converters depends on the system clock, number of signals and the refresh rate. Analog Decoder: It is used to route a separate analog signal and capture it into a designated "Sample and Hold" device. Analog Multiplexer: It is used to select separate analog signals and pass them on an analog bus to the "Sample and Hold" circuit. Sample and Hold: It samples analog signals and keeps the value stable for the ADC or for the output amplifier in the signal-conditioning cell. Digital Decoder: It is used to route a separate digital value and capture it into a designated register in an internal ADC system register file. Digital Multiplexer: It ensures that the output values, stored in the DAC system register file,
•
•
are routed one at a time to the DAC for conversion. Sequencer and Control: This functional block organizes the interaction among internal modules and handles the mapping of the internal registers of ADC, DAC and Signal Conditioning and Control blocks into an appropriate memory map. The mapping allows reconfiguration and access to I/O data registers. The sequencer ensures the correct order of internal operations and the synchronization of input and output data streams to and out of the DAC and ADC. Register files: They represent the interface to the chip from the board (I/O handler). Three groups of registers are included for input data, output data and configuration. The number of registers per file depends of the number of signals (N) the chip is designed to handle. The size of the register depends on the accuracy of the conversion logic (P). Output registers are continually monitored and generate output signals. The configuration registers are used to set up the gain and type of conditioning for each cell consistent with the signal attached. One register will be needed for each signal.
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Among the different functional blocks, the signal conditioning’s cell is very unique and conceptually new. The other modules have been extensively covered in the literature; see for example [14]. However, we are not aware of any previous work that integrates such modules in one programmable general-purpose configuration.
3.1 Signal-Conditioning Cell Programmability is a key design factor for the signal-conditioning cell. Each cell is empowered with generic capabilities to interface with a singleended or differential input signal, voltage- or current-based output signal. Signals can be either analog or discrete. Each cell has two connection pins per signal interface that are used to handle differential input, with one of them grounded in case of single-ended signals. The cell has a programmable gain operational amplifier to scale input signals to the full range of the ADC and output signals to the required range, while maintaining signal integrity and accuracy. Configuring a cell to a particular signal type and setting the gain are handled through internal control signals derived from the configuration registers. In addition to the adaptability to the type of signal being processed, the signal-conditioning cell has filtering and testing capabilities. It may be desirable to filter the input before it is sampled for anti-aliasing. This is true for most analog signals, and may be a desirable feature for discrete signals experiencing high doses of noise. In addition, a signal may need to be checked for a short or an open circuit or to check the DC offset on a particularly precise signal. A wrap around test and
Current OUT
I+
TO ADC
Optional Filter
Volt IN
IO +
I-
I-
T+
I+
T-
I-
Volt OUT
FROM DAC
Figure 4: Cell's internal design
a configuration to a known good voltage will supply the tests needed to investigate these scenarios. A simplified description of the design the conditioning cell is shown in Figure 4. The following describes how the cell handles the different signal characteristics. Analog and Discrete Signals: The approach for handling the different analog and discrete signals is not to sort them out, but to handle the discrete input as a single-ended analog input. Treating them differently would be redundant and consume more chip area and thus would increase the chip cost. In addition, handling the signals similarly has many benefits for the discrete signal, such as programmable hysteresis and programmable debounce [14]. Single-Ended and Differential Signals: Since discrete signals have been classified as single-ended analog signals, there are really only two classes of signals, the single-ended and the differential signals. These need to be handled so that the differential signal keeps its integrity and the singleended signal has a reference to its local ground. The approach, as shown in Figure 4, is to make the input voltage differential. If the signal is actually single-ended, the input pin “I-“ should be connected to local ground. This gives the input amplifier a good ground reference. As for the output, the signal is single-ended. If needed, a local ground can be included for a reference. If a fully differential output is needed, one channel would carry the true signal while another channel would carry the negative signal. This case would cause two channels to be used for one signal. Signal Sizes: There are some signals that use the maximum upper bound as their limit, but there are other signals whose upper bound is much smaller than the maximum. Sampling these signals without amplifying them first would result in a loss of precision in the signal. To compensate, the input voltage amplifier has a system of programmable gains to scale up the signal. A more detailed view of the input amplifier is shown in Figure 5. The T-Gates (transmission gates) are typical analog switches used to turn a signal ‘on’ or ‘off’. When off, the signal becomes high impedance (Hi-Z). The common mode voltage
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is a typical reference mechanism used for singleended configurations. The ‘GAINS’ block is implemented by a system of resistors in parallel with a T-Gate to switch them in or out of the circuit and vary the feedback resistance used in Op Amp calculations for gains (Vout = (Rfeedback/Rinput) * Vin). GAINS IT-
Op Amp
I+ T+
Out
+
Common Mode Voltage
T-Gate under user control
Figure 5: Detailed Design of the Input Amplifier Input and Output: The last variable in conditioning the signals is to classify each signal as input or output. It can be programmed using output amplifiers with an ‘enable’ command bit that will put their respective output into high impedance (HiZ). Therefore, when a cell is to be configured as an input, the output devices can be disabled and not interfere with the input signal. Also, when a cell is set to be an output port, the input functionality is still activated and has no effect on the output signal. This provides a strong support for testability, as discussed next. Testability: Figure 5 shows the internal design of the input circuitry in the conditioning cell (Figure 4). The input amplifier allows a DC offset test to be performed. As seen in Figure 5, it is possible to disable both test (T-, T+) and input (I-, I+) signal pins. In this configuration, the input amplifier can be configured as a voltage follower and would report the value of the common mode voltage source. In addition, the overall circuitry of the signal interface allows for two methods of wrap around tests. The first wrap around mechanism is always active and tests the output. As seen in Figure 4, the input is always connected to the final output. As such, the input can be checked at any time to be certain that the output is functioning properly. This is true for both the voltage and current sources and
is also the procedure for monitoring the voltage built up across a resister when current is supplied. The second testing mechanism is enabled when the cell is configured as an input signal. In such configuration, the output must be disabled so as not to interfere with the incoming signal. In this case, a wrap around circuit cannot be created through the output of the output amplifier. As an alternative, the input can switch to the voltage supplied by the DAC, as detailed in Figure 5 (T+ and T-). This test creates confidence that the input amplifier is functioning for different smaller signal and is not “stuck” at a certain level. Current Sourcing Output: As seen in Figure 4, the output can also be a controlled current. The output DAC is disabled, and the Current Output control is turned on via the configuration register. The result of the voltage generated across the external load of the current source can then be measured by the DAC input. Filtering: Another feature of the signalconditioning cell is the user-selectable filter, as shown in Figure 4. By configuration, it is possible to switch in a filter individually for each signal. The filter can be used as an anti-aliasing low-pass or band-pass filter. The implementation of various types of filtering is constrained by limitations on the size of the chip imposed by the microelectronic technology. In the example implementation mentioned in section 4, a low-pass filter could be successfully included on the chip. The filter is implemented by a switched capacitor network and has an independent clock signal (one clock signal supplied to all filters). The filter block can also act as demodulator, given the appropriate reference signal. This demodulator then can use the reference signal for an LVDT or RVDT device and generate the appropriate voltage according to feedback for the position or angle, respectively.
4. Prototype Evaluation The concept of the chip has been implemented for aerospace applications. That implementation can support up to 16 signals. Every signal port is equipped with a selectable low pass filter to perform anti-aliasing and each port can act as a current source for up to 20mA. Signals can range
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from –10 to 28 Volts. Signal conditioning maintains signal integrity for up 12-bit accuracy. Analog-to-digital and digital-to-analog conversions sustain a precision of 12 bits, sampling each signal at a rate 40K sample/sec. The chip configuration is fully programmable and can be set up in a BITmode, in which signal ports either select a known voltage-level and convert it (for input) or wrap the output directly around input (for output) to a test line allowing for a board-level self-testing. The described chip implementation uses BiCDMOS (Bipolar, DMOS and CMOS) devices. It is being fabricated on 6 inches bulk CMOS wafers using 0.8 micron N-well and P substrate process. The chip should be operable in the range of –40C to 85C. Prototype chips are currently being evaluated. Production is expected to start by the end of 2001.
5. Conclusion We have described a novel general purpose I/O (GPIO) design that is configurable to different aircraft needs and miniaturized using state of the art in microelectronics. The approach unifies both the signal and the bus interfaces. Wide range of signal characteristics can be supported. A novel chip for programmable signal conditioning and conversion has been discussed. The chip is capable of handling a number of signals in any combination of discrete or analog as input (differential or single-ended) or output (voltage or current source). The GPIO approach can reduce the weight and volume of aircraft electronic systems and thus lower the cost of aircraft operation [1,2]. The highly configurable approach allows for I/O design to be reusable among different aerospace applications and thus achieves significant development cost.
References
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