(TLP) or human metal model (HMM) as sources of the current. However, real system-level ESD rarely shows this current waveform. Thus, this article emphasizes ...
System-Level Design for ESD Protection on Multiple IO Interfaces Pengyu Wei, Javad Meiguni, David Pommerenke Electromagnetic Compatibility Laboratory, Missouri University of Science and Technology Rolla, MO, 65401, USA +1 (573) 308 2019 Abstract—This paper introduces the application of systemefficient ESD design (SEED) to ESD-induced pulses that are typical for system-level ESD. Emphasis is given to USB connectors because it has been shown that discharges to the connector shell will not lead to damaging current levels; however, the current levels are sufficient to cause soft-failures and possibly lead to latch-up of the USB IC.
1) Quasi-static VI curve For the time after the turn-on phase, a TVS is often described by its static VI curve. The static VI curve illustrated in Fig. 1 shows the turn-on voltage and the dynamic resistance of the TVS. Dynamic resistance values are often less than 1 Ohm. TLP time domain data was used to obtain the static VI curve. An average window was set into the later part of the Index Terms—Electrostatic discharge (ESD), system-efficient waveform to obtain data in the quasi-static region of the time ESD design (SEED), transient voltage suppressor (TVS), SPICE domain waveform. modeling, snapback
I.
INTRODUCTION
IO damage due to ESD events is a common threat to electric devices. The on-chip ESD protection design has often limited the current handling ability of the I/O to reduce the chip area occupied by ESD protection. A variety of situations can lead to ESD stress on I/O; e.g., the insertion of a charged cable [2]-[3], discharges to the shell of a USB connector, or the discharge to a USB connected device. The latter case often leads to currents larger than 5 A if the USB cable is not shielded. Market sampling had shown that about 30% of the USB 2.0 cables had no shield. The system-efficient ESD design (SEED) methodology [1] is one approach for systematic and robust system-level ESD protection design. SEED combines source models, current path models, passive components, and the quasi-static VI behavior of the IO in order to predict the current that is injected into an IC. The advanced analysis uses complex models of the IC’s ESD protection and TVS diodes that include inductive and non-inductive overshoot and snapback delay. Such models can be combined with other nonlinear elements to predict the current injected into an IC for complex discharge situations. In many cases, SEED simulation uses transmission line pulser (TLP) or human metal model (HMM) as sources of the current. However, real system-level ESD rarely shows this current waveform. Thus, this article emphasizes more realistic discharge situations such as the discharge into the shell of a USB-connected device.
(a) Figure 1.
(b) (a) Quasi-static VI curve. (b) Voltage waveforms during TLP pulse.
2) Inductive overshoot The inductive overshoot in the voltage waveform is due to the time changing the current through the apparent inductance of the diode. Its value depends on the mounting of the diode. In typical PCB applications, the inductive overshoot is characterized by inductances of less than 1 nH. The voltage across the diode which is caused by the apparent inductance is proportional to the time derivative of the current.
3) Non-inductive overshoot The non-inductive overshoot is caused by the modulation of the conductivity of the TVS diode. At first, the charge carrier density is not large enough to create a very low resistance path. Within nanoseconds, the number of charge II. COMPONENT MODELS carriers increases until the final dynamic resistance value is A. TVS model and its transient behavior reached. Higher voltages across the diode lead to a reduction Transient voltage suppressor (TVS) diodes are used in ESD of the time until the final dynamic resistance value is reached. protection for multiple interfaces such as USB, LAN, HDMI, The time domain response and the quasi-static VI curve are etc. The transient response during the turn-on process of a shown in Fig. 2. typical TVS diode can be broken into the following contributions.
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Figure 2. Illustration of voltage waveforms of the non-inductive overshoot for different TLP charge voltage
4) Snapback delay Figure 5. Three terminal model of the Snapback delay behavior is a phenomenon due to the USB IC TX pin [4]. internal low resistance structure is triggered by high voltage stress. Fig. 3 shows the response of the snapback delay in the In general, characterizations are performed with respect to time domain and its related VI curve. VSS. However, because of the on-chip ESD protection diodes, current can also be diverted to VDD. The current will return to VSS via on-chip and off-chip capacitances. The three-terminal (IO pin, VDD, VSS) model [4] (Fig. 5) was used in the simulation. Fig. 6 presents the fitted quasistatic VI curve of the three terminal IO model. This USB IC can only handle current at about 1.5 A. Disregarding the effect of the pulse length, we assume that any current larger than 1.5 A may damage the IC.
(a) Figure 3.
(b) (a) Voltage waveform IV curve. (b) Snapback delay.
Fig. 4 shows the comparison between the simulation and measurement results for a typical TVS model (TDR-TLP method, 300 ps rise time, 6 ns pulse length) for two charge voltage levels. Figure 6. Quasi-static VI curve comparison between measurement and simulation.
(a)
(b)
Figure 4. Measurement and simulation results comparing transient behavior of a TVS: (a) 45 V TLP source voltage, (b) 1000V TLP source voltage.
B. Large signal IO pin model A good approximation to the large-signal behavior of the pin can be extracted in the form of a quasi-static IV curve that is measured by long (in this case 75 ns) TLP with a fast (1 ns) rise time. In this model, the transient behavior during the turn-on and turn-off of the ESD protection is neglected. For this specific IC, this is justified as its internal response is very fast.
C. Source model System-level ESD testing was performed using IEC 610004-2 [7] ESD generators. For component level validation, a TLP was used as it provides a clean waveform. In reality, ESD events can occur from a person touching a connector (human skin ESD), a person touching a connector having a metal part (e.g., key), from discharging a person to a USB connected device, inserting a charged LAN cable, etc. The ESD generator contact model [8] which was extracted from the ESD gun physical model is shown in Fig. 7.
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(LUSB-GND) is between the bottom of the USB shell and the large return path to model the inductance of an imperfect USB shell to enclosure connections. This inductor is shown in Fig. 9 (b).
Figure 7.
IEC61000-4-2 ESD generator contact mode model [8].
Figure 9. Simulation workspace to analyze different realizations of a flex circuit with transmission lines cable connection between a USB connector and a PCB: (top) Perspective view, (bottom) Side view.
Figure 8. Measured ESD discharge current into the USB IO pin for a discharge into a USB connected device if the USB cable has no shield (8kV contact mode) [4].
D. Passive model The implementation of a USB port often requires other components, such as flex circuits, and structural choices. Here, the connection of a USB connector shell to an enclosure helps divert ESD currents to the outside of the system. However, due to economic reasons, such connections may not be perfect, and flex cables may not have good field confinement (e.g., single layer). To investigate the coupling, a CST model was created. The CST simulation workspace for a given USB right-angle female connector attached to a PCB is sketched in Fig. 9. This model consists of a large grounded return path in the bottom (models the main ground of the DUT) and in the front of the structure as well as a bulk perfect electric conductor (PEC) attached to the large grounded return path. The signal from the USB connector is transmitted to the target (which would carry the USB IC) via a host PCB (FR4 substrate) and a flex circuit. Inductors are used to model imperfect connections between the flex circuit pins (e.g., parasitic inductance in a connector) and imperfect connection of a flex circuit ground. An inductor
In the investigations of the flex cable attached USB connector the following design variations were investigated. • Connection of the USB connector shell to the enclosure. This was investigated by varying the value of an inductor (LUSB-GND) between the USB connector shell and the “large grounded return path” as depicted in Fig. 9. Values of 5 nH and 10 nH model a moderate and bad connection, respectively, and “open” models, the case in which a plastic enclosure, were used; thus, the USB connector cannot be connected to an enclosure. • Having a USB cable inserted prior to the discharge vs. having an open USB connector. The main difference is that the cable terminates the D+ and D- pin by 50 Ohm (from the other USB connected device) and it practically shorts GND and VDD. In the CST model, passive components are inserted into the USB connector to approximate the effect of an attached cable. The current flow in D+ and D- is changed, as the traces are now connected on both sides: One side of the USB connector, on the other side of the IC. • Flex cable realization. The flex circuit may contain two layers, where the second layer is ground. Its connection to the PCB grounds may be imperfect, or even nonexistent. The second variant uses a single layer flex; however, the signaling structure is changed from VDD D+ D- GND to VDD D+ GND
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D- GND. Here, it is assumed that VDD is connected to GND via low inductance capacitors, thus VDD is modeled as GND. The single layer flex is designed as a CPW, achieving about 60 Ohm characteristic impedance for D+ and D-. • Parasitic inductances in the flex cable connection. The flex cable is often connected via a connector. In this case, parasitic inductances will inhibit the current flow. They are modeled as inductors at the connection points of the traces on the flex cable, and as inductors at the connection of the flex cable ground (in the two layer case) to the PCB grounds. The simulation model was excited by a current injection into the USB shell. The voltages at the IC input, port 2 and 3 are monitored. The simulation creates an S-parameter block. This S-parameter block is imported into the SPICE-like ADS (top) Simplified USB connector simulation environment. In the ADS simulation, nonlinear Figure 10. model with the passives connected internally between USB pins and USB models of ICs and TVS diodes can be included to determine shell. (bottom) The magnitude of the insertion parameter from source to the currents that are injected into the IC. target. Other passives on the flex traces and PCB traces = 0 ȍ, flex shield and PCB ground = 0 ȍ, flex shield and bulk ground = 0 ȍ, LUSB-GND = 5 nH. 1) Effect of parasitic inductances on the flex cable connector 2) Effect of the connection between the USB shell and the The (RPIN-USB) passives which connect the USB pins to the enclosure USB shell emulates the effect of having a USB cable inserted The imperfection of the USB shell to enclosure (large prior to the ESD. Fig. 10 (a) shows the USB connector where grounded return path) connection was modeled by the inductor the pins are connected to the USB shell internally with RPIN-USB = 0 ȍ, 50 ȍ, 50 ȍ, 0 ȍ, respectively. The USB shell is LUSB-GND. Values of 5 nH, 10 nH and “open,” were used. The connected to the large grounded return path using a LUSB-GND = open case showed the effect of not having a metallic enclosure. 5 nH. The magnitude of S21 as a function of frequency for the Fig. 11 shows the effect of LUSB-GND which connected the USB proposed structure is compared to those of the same structure shell to the large grounded return path. Around 500 MHz the without using passives and is shown in Fig. 10 (b). Thus, this coupling was increased by 15 dB if the enclosure was not compares the noise coupling to a USB connector for the two conductive. cases: No cable inserted vs. cable inserted prior to the ESD 3) Effect of the parasitic inductances in the flex cable injection. connectors Connectors used for the flex cable added parasitic If no cable was inserted, a strong resonance was observed around 1 GHz. This is formed by the inductances between the inductances. These are modeled as passive components at the shell and ground (LUSB_GND and flex cable inductance) and the end of the flex cables. Fig. 12 (a) compares two cases (LUSBcapacitance of the USB connector structure. If the D+ and D- GND = 5 nH). Adding 3 nH parasitic inductance increases the traces were connected by 50 Ohm, the resonance was strongly coupling by about 10 dB up to 800 MHz which indicates the attenuated. More than a 40 dB/dec slope was observed in the importance of selecting connectors with minimal parasitic magnitude of S21 for frequencies below 150 MHz if no cable inductance not only for signal integrity reasons, but also for was inserted, a consequence of only having a capacitive return reducing ESD noise coupling. path from the unconnected connector pins to the USB shell.
Figure 11. Magnitude of the coupling from the ESD injection to the IC pins for different values of LUSB-GND. Other passives on the flex traces and PCB traces = 0 ȍ, flex shield and PCB ground = 0 ȍ, flex shield and bulk ground = 0 ȍ, RPIN-USB = 0 ȍ, 50 ȍ, 50 ȍ, 0 ȍ.
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primary results show a few dB more coupling for this single layer structure, as shown in Fig. 13.
Figure 12. (top) Magnitude of S21 from the ESD source to the IC pins for different components on the flex traces. Flex shield to ground on both sides = 0 ȍ. (bottom) The magnitude of S21 for different components on the Flex shield to ground. flex traces on both sides = 0ȍ. Other passives: Flex traces and PCB traces = 0 ȍ. LUSB-GND = 5 nH., RPINUSB = 0 ȍ, 50 ȍ, 50 ȍ, 0 ȍ.
Another design choice related to the flex cable ground connection is the ideal of a connection along the complete width of the ground. However, in many connectors only the two outer pins are used to connect a flex ground, causing additional parasitic inductances. A more extreme case is the addition of a piece of CU tape to the flex cable, without connecting this metal part to ground. Such a design can often be found if not having any ground on the flex caused unacceptable signal integrity problems; however, the design was already so advanced that the connector could not be changed any more to provide a ground connection. Fig. 12 (b) illustrates the coupling as a function of different flex cable ground connections. If the ground was not connected on both sides, the coupling increased by about 16 dB. Again, there is an emphasis on the importance of good field confinement in flex cable connections. If the fields of the signaling conductors are not well confined, it will couple to the fields of noise currents that should only be carried by return planes and shields. 4) The effect of passives on the CPW-like flexible transmission line A single layer flex circuit can be used if a CPW like structure is created for meeting the characteristic impedance goal. As shown in Fig. 13 (a), the ground traces are located in between each signal traces with no ground underneath. The
Figure 13. (top) Simplified CPW-like single layer flex, S, and G are an abbreviation for signal and ground, respectively. (bottom) S21 from ESD source to IC pin. Other passives on the flex traces and PCB traces = 0 ȍ, flex shield and PCB ground = 0 ȍ, LUSB-GND = 5 nH, RPINUSB = 0 ȍ, 50 ȍ, 50 ȍ, 0 ȍ.
Investigating the worst case topology allows estimating the current injected into the IC. By not connecting the flex cable ground in this study, the realistic worst cases are reached while the flex shield to grounded return paths on both sides is kept floating. The existence of LUSB-GND = 5 nH between the USB shell and large grounded return path is unnecessary to avoid any sparking during the ESD stress because of the existing large conductive path from USB GND pin to the grounded bulk. The results, in this case, are prepared in Fig. 14 for both usual flex and CPW-like flex while LUSB-GND is “open”.
Figure 14. Magnitude of the S21 parameter in the worst cases. Passives on the flex traces and PCB traces = 0 ȍ, flex shield and PCB ground = open, LUSB-GND = infinite, RPIN-USB = 0 ȍ, 50 ȍ, 50 ȍ, 0 ȍ.
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III.
SYSTEM LEVEL SIMULATION MODEL AND RESULTS
A. Simulation I: TLP injection into D+ In general, the trigger voltage of a typical snapback TVS diode is higher than the turn-on threshold voltage of the onchip ESD protection diode. For example, the TVS diode in this simulation and measurement will be triggered only if the stress voltage is higher than 16 V, however, the turn-on threshold for the on-chip ESD protection diode is Vth=VDD (0 V or 3.3 V) + 0.7 V. Although the dynamic resistance and the clamping voltage of the TVS diode are much lower than the IO pin, it cannot guarantee the TVS diode will provide protection. In this simulation. The TLP model was used as the source, after the source a 100 nF AC capacitor was connected with a 70 mm microstrip line, and at the end, the IC model was placed with a 200 nF and a 200 pF decoupling capacitors between the VDD and VSS. VDD is 0 V, or 3.3 V with reference to VSS. A snapback TVS diode was applied to the source and the capacitor. The simulation and measurement set-up is shown in Fig. 15.
Figure 15.
Simulation model for an IC which is additionally protected by a TVS diode.
Figure 16. Simulation results of the TLP stress on the USB port, VDD=0 V. (top), (mid) Voltage waveform. (bottom) Current waveform.
Fig. 16 shows the simulation results compared to the measurement results. In this simulation, the VDD is 0 V. In Fig. 15 (b), the ringing at the beginning of the waveform is due to the reflection between the TVS diode and the IO pin. From the current waveform we can see that even with the TVS diode, there is still a significant amount of current injected into the IO pin; potentially, this type of TVS diode cannot protect the IO when the IC is in the power off condition. To protect the IO, an additional passive component such as a series 5-ohm resistor need to be placed between the TVS and the IO pin. To protect this specific IC, a transmission line is necessary between the TVS and the IC. It needs to provide enough delay for the TVS to be turned on. The minimal length is related to the rise time of the pulse. A better choice maybe using a diode from the input pin to VDD as TVS. B. Simulation II: 8 KV ESD contact discharge to a USB connected device Thirty percent of the USB 2.0 cables sampled from the market had no shield. If such a cable connects to a device and a person discharges to the device, then the current will equally distribute on the four wires in the USB cable. As the initial pulse is suppressed one can expect about 5 A on D+, as shown in Fig. 8 (b). The simulation configuration is shown in Fig. 17. R1 is the source impedance which is used to terminate the reflected wave. The VDD of the IC has been set to 3.3 V. The TVS diode model is placed before the transmission line.
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Figure 17.
Discharge to a USB connected device using an unshielded USB cable.
C. Simulation III: 8 KV ESD contact discharge to a flex connected USB connector shell The simulation emulates contact mode discharge to the USB connector shell. As described in section II part D, the shell was connected to the large grounded return path through the LUSB-GND. The D+ and D- pins have been terminated by 50 Ohm. Cases with three different LUSB-GND values were investigated. Fig. 19 shows 35 Vpp for the case in which the USB connector shell was not connected to an enclosure, while even a moderate connection (5 nH) reduced the voltage to about 6 V. The simulation used 50 Ohm termination, but in reality the ESD protection of the IC would have clamped the voltage. The voltage levels are large enough to cause softfailures, possibly latch up, but are too small to directly damage most ICs.
Figure 19. Noise coupled to the signal pins due to 8 KV ESD contact discharge considering three different USB shell grounding conditions. Other passives on the flex traces and PCB traces = 0ȍ, flex shield and PCB ground = 0ȍ, flex shield and bulk ground = 0ȍ, RPIN-USB = 0ȍ, 50ȍ, 50ȍ, 0ȍ.
Figure 18. 8 KV ESD contact discharge to a USB connected device, with and without TVS diode. (top) Voltage at the IO pin, (bottom) Current into the IO pin
In Fig. 18, if the TVS was not present, the voltage at the IO pin was around 5 V (not shown) which is clamped by the on-chip ESD protection. The current that injected into the IO pin was approximately 5 A; this current level is very likely to damage the IO pin. In the other case, if the TVS was attached, then both the pin voltage and the current decreased apparently. Similarly, to the above simulation, the ringing in the voltage waveform is due to the reflection between the TVS diode and the IO pin, and the duration, 1 ns, is the double delay time of the transmission line. As the current is lower than 1 A, the IO pin can survive from this USB cable discharge event.
D. Simulation IV: The worst case of 8 KV discharge to flex cable connected USB shell A more severe case is given if the USB shell was not grounded, and the ground on the flex cable was not connected. In this model, the GND pin of the USB is connected to the shell, as otherwise sparking would occur. The S-parameter result is shown in Fig. 14; since the performance of the CPWlike structure and the usual flex structure are very similar, only the worst case of the usual structure was considered in this simulation. To obtain the current that flows into the IC, the model contains the ESD protection of the IC. Fig. 20 shows the peak to peak voltage around 16 V and a current of 4 A. If we assume only 1.5 A robustness of the IC (but measured using a longer pulse), one may conclude that the IC will be damaged; however, due to the short duration of the pulse this conclusion is not certain.
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If a TVS is used in addition to the IC’s internal ESD protection, then the interplay of these devices can also be simulated using the SEED methodology. Here, the simulation shows strong ringing due to the trace length of the TVS and the IC. ACKNOWLEDGMENT The authors would like to thank Dr. Harald Gossner for his guidance in the TVS characterization and the modeling work. REFERENCES Figure 20.
Simulated voltage and current on
[1]
the IO pin [2]
IV.
CONCLUSION
The risk of damage or upset to a system by ESD to a USB connector can be ranked as follows: Worst: Direct discharge to a pin. This is not likely to occur as the spark will reach the metallic shell instead. For that reason, this case was not considered here. This case would damage the IC, as, e.g., at 8 kV a peak current of larger than 30 A may be injected into the IC. Second worst: Discharge to a USB connected device which is connected via an unshielded USB cable. Here, the current would equally distribute over the four wires and 5-8 A (at 8 kV ESD) would flow into the IC, most likely damaging it. Third worst: Discharge to the USB connector shell in a design that has no metallic enclosure. If, in addition, the shield on the short flex cable is not connected, then the simulations show a current of 4 A flowing into the IC. Further reductions of the noise levels can be achieved by connecting the USB connector shell to an enclosure, using a two layer flex with good ground connections on both sides, and avoiding parasitic inductances in the connector.
[3]
[4]
[5] [6] [7] [8]
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