3-D Integration of Nanophotonics with CMOS

Invited Paper

3-D Integration of Nanophotonics with CMOS electronics Bahram Jalali, Tejaswi Indukuri, Prakash Koonath and Koichiro Kishima University of California Los Angles, Department of Electrical Engineering Los Angeles, CA 90066 [email protected] ABSTRACT A novel approach to three-dimensionally (3-D) integrate nanophotonic and electronic devices in silicon is described. The method is based on the SIMOX (Separation by Implantation of OXygen) process, to realize three-dimensionally (3-D) integrated devices in a monolithic fashion. In this approach, photonic and electronic devices are realized on vertically stacked layers of silicon, separated from each other by a dielectric layer of silicon dioxide formed through the process of oxygen implantation. Opto-electronic integration is demonstrated by realizing photonic circuits in a subterranean silicon layer and Metal-Oxide-Semiconductor (MOS) transistors on a surface layer of silicon. Optical and electronic functionalities are thus separated into two different layers of silicon, paving the way towards dense three-dimensional opto-electronic integration. This has the significant advantage that photonic devices do not consume any of the expensive silicon real estate required for CMOS circuitry. The versatility of the technique of SIMOX 3-D sculpting in obtaining complex optical circuitry is also demonstrated by synthesizing a cascaded microdisk structure that may be utilized to tailor the passband characteristics of optical filters. Keywords: Silicon photonics, microcavity, nanophotonics, monolithic integration, opto-elelctronics.

1. INTRODUCTION Silicon-on-Insulator (SOI) materials system has proven to be an efficient platform for the realization of both electronic and photonic devices. Recent years have seen significant amount of research in the area of silicon photonics, resulting in the demonstration of a variety of both active and passive optical functionalities1-8. These technologies have demonstrated the feasibility of using silicon for the realization of integrated optical devices. One of the most attractive features of the silicon is the prospect of full integration of optical and electronic devices on the same substrate. On the other hand, the cost of manufacturing CMOS devices increases exponentially as the feature size continues to scale further down nano-scale dimensions, with the number of transistors projected to reach 2 billion per chip. In order for this scaling to be economically feasible, it becomes necessary to maximize the real estate usage on silicon wafers. It is desirable, therefore, to realize opto-electronic integration in silicon in such a way that the photonic devices consume minimal amount of real estate on a silicon wafer. These requirements unequivocally point to the separation of electronic and optical functionalities to different layers of silicon and integrate these layers vertically in a three-dimensional (3-D) fashion. Innovative fabrication technologies need to be developed to realize this 3-D integration in a monolithic fashion, at the same time being compatible with the well established CMOS foundry processing techniques. From the perspective of optical devices, vertical integration is an efficient way to fabricate densely integrated 3-D structures, thereby enhancing the functionality of the chip. Apart from this inherent advantage, in the realization of optical waveguide structures, vertical integration offers the prospect of precise control of coupling coefficient in vertically coupled devices. Here, the control over the critical dimension is more precise than laterally patterned structures, where the limits are set by the photolithography. Thus, complex optical circuitry with accurately controlled evanescent coupling between devices is possible by employing vertically integrated optical devices. We have developed the process of SIMOX 3-D sculpting, a novel method based on the SIMOX (Separation by Implantation of OXygen) process, to realize 3-D integrated nanophotonic and electronic devices on the same silicon substrate in a monolithic fashion. In this approach, photonic devices are confined to a buried silicon layer, separated a from a surface silicon layer by an intervening silicon dioxide layer. Opto-electronic integration is then achieved by fabricating Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) on the surface silicon layer. One of the most attractive features of the technique of SIMOX 3-D Sculpting is that the integration photonic devices do not

Integrated Optics, Silicon Photonics, and Photonic Integrated Circuits, edited by Giancarlo C. Righini, Proc. of SPIE Vol. 6183, 618314, (2006) · 0277-786X/06/$15 · doi: 10.1117/12.669074

Proc. of SPIE Vol. 6183 618314-1

impact the availability of silicon real estate from the point of view of electronic circuitry, as optical and electronic functionalities are separated to two different layers of silicon.

2. PROCESS OF SIMOX 3-D SCULPTING SIMOX process involves the implantation of Oxygen ions into a Silicon substrate, followed by a high temperature anneal (around 1300ºC) of the substrate in order to cure the implantation damage and to effect SiO2 formation. The thickness and the depth of the buried oxide layer are respectively determined by the implantation dose and energy. It has been observed that in order to achieve good quality buried oxide and to keep the defect densities in the range of < 105 /cm2, implantation dose should be in the range of 1×1017-9×1017 ions per cm2, with implantation energies in the range of 40 – 200 KeV9. The process is conventionally used to obtain thin silicon layers (of the order of 3000 Ǻ) on top of a buried oxide layer of thickness of the same order of magnitude. There has been an attempt previously to fabricate 3-D structures in SOI wafers using the SIMOX process, combining it with epitaxial growth of Silicon10. The complete process involved two implantation steps and two epitaxial growths in order to grow vertically integrated SOI waveguides. The waveguides fabricated in this case were planar in nature with guiding layer thickness of the order of 2 micrometers. A method, utilizing the implantation of Oxygen ions into a masked SOI substrate, is employed to realize buried rib waveguides. Figure 1 depicts the process flow of the fabrication of vertically integrated structures using the technique of SIMOX 3-D Sculpting. Implantation of oxygen ions is performed on an SOI substrate that has been patterned with thermally grown oxide. The thickness of the oxide mask may be chosen suitably to decelerate the Oxygen ions that penetrate into the area underneath the mask. The angled side-wall of the buried rib waveguide formed after the high temperature anneal arises due to the lateral straggle of the implanted oxygen ions. After the anneal, devices may be defined on the top layer using conventional lithography and etching process, as shown in Figure 1. Silicon Silicon Dioxide

Substrate Oxygen Implantation

Substrate After Anneal

Substrate After top layer definition

Figure.1 Process flow of SIMOX 3-D Sculpting

3. FABRICATION OF DEVICES A SOI wafer (made by SOITEC Inc.) with 0.6 µm of Silicon on top of a buried oxide layer of 1.0 µm thickness was oxidized and patterned using reactive ion etching process to form oxide stripes of thickness 0.06 µm, and of width 2 µm. The patterned wafer was then implanted with oxygen ions with a dose of 5×1017 ions per cm2, at energy of 150 KeV. The implanted wafers were then annealed at 1320ºC for 7.5 hours in an ambient of Argon, with 1% Oxygen, to cure the implantation damage. Figure 2 shows the SEM photograph of a buried rib waveguide structure that was fabricated employing the technique of SIMOX 3-D sculpting, dimensions of which are shown in the figure. It may be seen from the figure that the process has resulted in the formation of submicron rib waveguides in the bottom Silicon layer, separated from the continuous Silicon layer on the top by the oxide layer formed after the oxygen implantation and subsequent anneal. These waveguides act as a bus waveguides to the microdisk resonators that are realized in the same buried silicon layer. Figure 3 shows an optical micrograph of the top view of a microdisk resonator, situated in a buried layer, coupled laterally to the bus waveguides. These devices consist of 2µm wide waveguides acting as input and output ports to a microdisk resonator of radius 20µm. One of the bus waveguides acts as the input port where the optical power is launched. The resonant wavelengths are directed to the drop port of the device whereas those wavelengths that are out of resonance are collected at the throughput port of the device, as denoted in Figure 3.


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238nm

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Figure.2 Cross-sectional SEM view of the buried rib waveguide formed by the process of SIMOX 3-D sculpting.

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Figure. 3 Optical micrograph of top view of a 20µm radius disk resonator. The entire device is 350nm below the surface of the SOI wafer

After the fabrication of optical devices in the buried silicon layer, conventional processing is used to the realize MOS transistors on the surface silicon layer. The wafers are subjected to a uniform boron implantation and subsequent anneal activation and drive-in to achieve a doping of 2x1017 cm-3 in the body region. Then, the active area where transistors are to be fabricated is defined via lithography, and field oxidation is performed everywhere except in the active region to obtain electrical isolation of the devices on the surface silicon layer. Subsequently, gate oxidation and polysilicon deposition are performed, followed by lithography to define the gate region. Gate oxide of thickness 25nm is used in this work. A self-aligned phosphorus implant is then employed to define the source and drain regions of the transistor. Photolithography followed by a subsequent boron implantation step is used to obtain the body contact. The dopants are then activated using rapid thermal annealing (RTA) in nitrogen ambient. A layer of low temperature oxide (LTO), of thickness 500 nm, is deposited and patterned to define vias for electrical contact during the deposition of metal. Aluminum sputtering, followed by lithography and wet etching, is then used to define the metal pads required for the electrical probing of these devices. Figure 4 shows an optical micrograph of an MOS transistor fabricated on the surface silicon layer, on top of a microdisk resonator that is situated in the buried silicon layer.

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40gm Figure. 4 Optical micrograph of a MOS transistor fabricated on the surface silicon layer, on top of a microdisk resonator that is situated in the buried silicon layer

4. DEVICE CHARACTERISTICS 4.1 Subterranean Photonics Figure 5 shows the transmission properties of the throughput port of the resonator, characterized using an Amplified Spontaneous Emission (ASE) source. The un-polarized light from the ASE source was passed through an inline fiber polarizer and a polarization controller that can rotate the state of polarization of the light to any desired state. This polarized light was coupled into the bus waveguides using a tapered fiber that has a spot diameter of 2 µm. The light


Normalized Power (dB)

output from the throughput port of the resonator was collected using a tapered fiber, similar to the one used at the input. The collected light was observed using an optical spectrum analyzer. The spectrum displayed in figure 5 is normalized with respect to the maximum transmission of the throughput port, after correcting for the spectral shape of the ASE source. Sharp resonances are observed with a free spectral range of around 5 nm, with extinction ratios in excess of 20 dB.

Wavelength (nm)

Figure. 5 Spectral characteristics of the microdisk resonator

4.2 3-D Integrated MOS transistors The electrical characteristics of these n-channel MOSFETs, realized on the surface silicon layer, were extracted using a HP4145B semiconductor parameter analyzer. Figure 6 shows the drain current (ID) versus gate voltage (VG) characteristics demonstrating gate control in the fabricated MOSFETs. Figure 7 shows the drain current versus drain voltage (VD) characteristics of the inversion channel. These transistors had a gate length of 1 µm. The devices exhibit a threshold voltage of 2.5 V which is close to the theoretically expected value. These characteristics clearly illustrate the realization of MOS transistors that are monolithically integrated with buried optical devices. It can be noticed that in the sub-threshold region, non-zero leakage currents are observed. It has been previously observed that, in the presence of defects in the silicon wafer, there can be diffusion of dopants from source and drain regions11. This can result in electrically active leakage paths from source to the drain, contributing to leakage currents in subthreshold regime. It is known that SIMOX process can result in the creation of defects during the implantation of oxygen ions12. After the annealing of the wafers subsequent to oxygen implantation, we measured defect densities of order of 5x104 cm-2 using Secco etching. We believe that these defects are responsible for the leakage currents observed. Currently, process optimization is in progress to further lower the defect densities. 1600

1400 1200 1000

Vd = 1V Vd = 2V

Drain Current (µA)

Drain Current (µA)

1600

Vd = 3V Vd = 4V

800 600 400 200 0 0.00

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1000 800 600 400 200

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Gate Voltage (V) Figure 6 Gate control characteristics (ID vs VG) of the fabricated MOSFET

0 0.00

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Drain-Source Voltage (V) Figure 7 Drain characteristics (ID vs VD)of the fabricated MOSFET


4.3 Vertically-coupled Microcavity Structures It has been demonstrated that cascaded resonator structures may be utilized to improve the filter characteristics of devices employing microcavities, including the flatness of the pass-band, the sharpness of the roll-off from the passband to the stop-band and the suppression of adjacent channel cross-talk13-14. SIMOX 3-D sculpting has been utilized to fabricate devices that consist of two microdisk resonators vertically coupled to each other, through the oxide layer formed after the implantation and subsequent anneal. The resonators themselves are coupled to bus waveguides that act as the input and output ports of the device.

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Figure.8 3-D schematic of the cascaded microcavities input

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Figure. 9 Top view of the vertically-coupled cascaded microcavity

Figure 8 represents a schematic of the device showing the vertically-coupled microresonators and the bus waveguides, with the arrows indicating the direction of flow of light through these devices. Figure 9 shows the top view of the fabricated two-stage device with cascaded microdisks of radius 20 µm, coupled to bus waveguides of width 2 µm. When optical energy is introduced to the input port of the device, resonant wavelengths are transmitted to the drop port, after traversing through the cascaded disk structure. It may be emphasized here that, we have realized waveguides as well as microdisk structures on both layers of Silicon, coupled vertically through an intervening layer of SiO2. These devices distinctly demonstrate the capability of the SIMOX 3-D sculpting to engineer 3-D structures in Silicon (the intervening layer of oxide through which the coupling of light takes place is omitted in figure 8 for the simplicity of illustration). Figure 10 shows the drop port transmission response, characterized by launching optical power at input port and collecting the optical spectra at the drop port of the device. Fabricated disks show a free spectral range of around 5.7 nm, with maximum extinction ratios ~ 12 dB.

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Figure. 10 Drop port spectral characteristics of the cascaded microcavity

Figure. 11 Comparison of the filter characteristics of the cascaded device with a single stage device


A comparison of the performance of the two-stage device to that of a single stage device, as shown in figure 11, illustrate the superior characteristics of the two-stage resonator in terms of its steeper roll-off, better out-of-band rejection and flatter pass-band. Note that the frequency scale in this figure is normalized to the 3-dB bandwidths of the individual filters. The shape factor, which is a measure of the flatness of the passband, defined as the ratio of the -1-dB bandwidth to the -10-dB bandwidth, is 0.47 for the two-stage device, compared to a value of 0.22 for the single stage device. Also, at twice the value of the 3-dB bandwidth, the two-stage device shows 4-dB improvement in the out-of-band signal rejection over the single stage device. It may be noted that the single stage device used for the purpose of this comparison is fabricated on the same chip as that of the two-stage device.

5. SUMMARY We describe a novel approach to three-dimensionally integrate nanophotonic and electronic devices in Silicon. These devices are realized on vertically stacked layers of silicon separated from each other by a dielectric layer of silicon dioxide formed through the process of oxygen implantation. Opto-electronic integration is thus achieved by confining the photonic and electronic devices to separate layers of silicon. This has the significant advantage that photonic devices do not consume any of the expensive silicon real estate required for CMOS circuitry. The versatility of the technique of SIMOX 3-D sculpting in obtaining complex optical circuitry is also demonstrated by synthesizing a cascaded microdisk structure that may be utilized to tailor the passband characteristics of optical filters. REFERENCES 1. 2.

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