3 Designing Digital Systems with Algorithmic State Machine Charts
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3 Designing Digital Systems with Algorithmic State Machine Charts
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ASM charts are similar in appearance to flowcharts used in the early days of com-
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university of applied sciences hamburg Prof. Dr. J. Reichardt
DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Prof. Dr. B. Schwarz
3
Designing Digital Systems with Algorithmic State Machine Charts • An ASM chart is a method of describing the sequential operations of a digital system
which has to implement an algorithm. An algorithm is a well defined sequence of steps that produces a desired sequence of actions and/or calculation results in response to a given sequence of control and data inputs. • ASM charts are similar in appearance to flowcharts used in the early days of com-
puter programming. Unlike the traditional flowchart the ASM chart includes timing information because it implicitly specifies that the FSM steps from one state to another only after each active clock edge. ASM charts are constructed of three elements.
university of applied sciences hamburg Prof. Dr. J. Reichardt
DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Prof. Dr. B. Schwarz
Ö Registered mathematical operations: COUNT ← COUNT + 1 ; MULT ← A * B The activated state will assert the enable signal which causes the counter to increment and the multiplier to operate a multiplicand and a factor. Ö Registered signal assignments: INT_REG ← INPUT_1 REG ← A(2:0) @ C(4:0) concatenation. • Condition symbol: A diamond shape contains the input condition on which depends the
branching from a given state. It has one entry point and two exit path. Condition symbols can be concatenated. Ö X means that the input signal X has to be tested. Ö X1 ∧ X2 indicates that X1 = X2 = 1 has to be true. • Conditional output box: An oval or rectangular with rounded edges represents an action,
university of applied sciences hamburg Prof. Dr. J. Reichardt
DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Prof. Dr. B. Schwarz
3.2
FSM as a Server's Polling Circuit • A polling circuit for a client-server system with 3 clients has to determine which client
is to be serviced by a server of many clients. • A client i requests service by asserting its service-request flag Ri to the client. In each
clock cycle the polling circuit polls its inputs Ri to determine whether service is being requested and to identify the requesting client having the highest priority. • In general the client having the highest priority is to be serviced. As long as a client
requests for service it will be granted by the polling circuit independently of other client requests. • After a request flag Ri is deasserted the polling circuit will enter the polling state at
university of applied sciences hamburg Prof. Dr. J. Reichardt
DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Prof. Dr. B. Schwarz
• Each client has a polling priority level: client0 > client1 > client2. The request Ri with
the highest priority is granted by the polling circuit with the corresponding grant bit Gi. Only one bit Gi a time can be asserted. • The FSM states are called: IDLE, GNT0, GNT1,GNT2. In IDLE state no Gi is as-
serted. • Start with a block diagram and decide which FSM type will be appropriate.
university of applied sciences hamburg Prof. Dr. J. Reichardt
DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Prof. Dr. B. Schwarz
VHDL Code for the Polling Circuit -- Polling circuit: client arbiter entity arbiter is port( CLK, RESET : in bit; R: in bit_vector(2 downto 0); -- device requests G: out bit_vector(2 downto 0)); -- device grants end ARBITER; architecture BEHAVIOUR of ARBITER is type STATE_TYPE is (IDLE, GNT0, GNT1, GNT2); -signal STATE, NEXT_STATE: STATE_TYPE; begin REG: process(CLK, RESET) begin if RESET = '1' then STATE
