3D chip-stacking technology with through-silicon ... - Semantic Scholar

3D chip-stacking technology with through-silicon vias and low-volume leadfree interconnections Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added timeto-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with leadfree solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 lm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mX.

Introduction The refinement of integrated circuits has been doubling the number of devices per chip area every two years, following Moore’s Law. However, physics-based constraints will force many changes in materials, processes, and device structures as the industry moves down to 32 nm and below. Consequently, it is increasingly difficult to sustain this growth rate and implement each successive generation of chip technology. Three-dimensional (3D) integration technology is expected to make it possible to extend the density growth rate by stacking chips rather than by simply shrinking device dimensions. Moreover, 3D integration makes it possible to stack heterogeneous technologies or different subsystems such as microelectromechanical systems, radiofrequency devices, nanodevices, or sensors [1, 2], in addition to processors and memory [3]. A processor chip can be stacked on top of multiple memory chips by using

K. Sakuma P. S. Andry C. K. Tsang S. L. Wright B. Dang C. S. Patel B. C. Webb J. Maria E. J. Sprogis S. K. Kang R. J. Polastre R. R. Horton J. U. Knickerbocker

3D integration technology. Processors and memory would be electrically connected through multiple vertical interconnections. Three types of 3D stacks are now emerging: wirebonded chip stacks, package on package, and package in package. While these approaches allow known-gooddevice testing prior to stacking devices, the disadvantages include long connection lengths and limited connections between chips. To overcome these wiring connectivity problems, 3D chip-stacking technology using throughsilicon vias (TSVs) is attractive because it offers a way to solve interconnection problems while also offering integrated functions for higher performance [4–6]. Some of the key technologies needed to enable chip stacking include wafer bonding, wafer thinning, chip alignment, and fabrication of TSVs with high-density lead-free solder interconnects. Figure 1 shows a configuration of face-to-back 3D chip integration. Each layer is electrically

Copyright 2008 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied by any means or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor. 0018-8646/08/$5.00 ª 2008 IBM

IBM J. RES. & DEV.

VOL. 52 NO. 6 NOVEMBER 2008

K. SAKUMA ET AL.

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Back end of the line Thin silicon

MOSFET

In this paper, we describe a 3D chip-stacking technology and investigate a joining process using lowvolume lead-free interconnects. We also present results of fabrication and characterization of a 3D chip-stacking test vehicle using chip-to-wafer technology.

3D chip integration technology

TSV MOSFET

Low-volume lead-free solder interconnect

Thin silicon

Metal-oxide semiconductor field-effect transistor (MOSFET)

Thick silicon

Three-dimensional chip integration is an attractive technology to meet future performance needs of integrated circuits [7–13]. Advantages can be realized in power consumption [14], latency, area, and packaging density, and the short vertical interconnects replace long two-dimensional wires. For 3D chip integration, there are different approaches under development. They include chip-to-chip, chip-to-wafer, and wafer-to-wafer approaches. Each has benefits and limitations. Comparisons of 3D integration technologies are summarized in Table 1.

Figure 1 Three-dimensional chip stacking using the face-to-back approach.

Chip

C4 solder interconnect

Chip Low-volume lead-free solder interconnect Substrate

Substrate

80 m

Intermetallic compounds

Chip

Chip