Oct 16, 2014 - L1 Cache. CPU. L1 Cache ... http://www.hybridmemorycube.org/technology.html. 10/16/2014 .... + Lowest uni
eda 2 asic
Tackling the Memory Wall with 2.5D and 3D ICs
memcon, Oct 15, 2014 Herb Reiter, eda 2 asic Consulting,
[email protected]
10/16/2014
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Agenda
• Introduction • How to Tackle the Dreaded Memory Wall… • … and Meet the Growing Functional Requirements of Specific Market Segments • Summary • Appendix 10/16/2014
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Top 5 Semiconductor Vendors
http://en.wikipedia.org/wiki/Semiconductor_sales_leaders_by_year#Ranking_for_year_2013
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CPU
CPU
L1 Cache
L1 Cache
CPU
CPU
L1 Cache
L2 Cache
L1 Cache
CPU
CPU
L1 Cache
L1 Cache
CPU
CPU
L1 Cache
Other
L1 Cache
Latency and Bandwidth limit system performance
NV Memory
Latency and Bandwidth limit system performance
Program Storage
Memory is Everywhere in a System
Data Storage DRAM
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The Dreaded Memory Wall
Current and especially new applications demand - higher bandwidth and smaller latencies - at lower power and smaller form-factors Until Now:
Starting Now:
Fighting the Memory Wall with: - More package pins - Stronger I/O buffers - SERDES lanes - Wire-bonded SiP
Fighting the Memory Wall with: - Multiple dice vertically stacked (3D) in a package - Adjacent dice on an interposer (2.5D)
High cost Large formfactor High power High overhead 10/16/2014
2.5/3D ICs
Lower system cost Smaller systems Less power dissipation Modularity = Flexibility 6
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Agenda
• Introduction • How to Tackle the Dreaded Memory Wall… • … and Meet the Growing Functional Requirements of Specific Market Segments • Summary • Appendix 10/16/2014
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eda 2 asic How to Improve Latency & Bandwidth Chip 2 Chip, wire-bonded 8 to 64 bits wide buses Logic chip
SiP
I/O Buffer with ESD Bonding pad: >50x50µm
Bonding wire: >10µm x …mm Bonding pad: >50x50µm I/O buffer with ESD Memory chip 10/16/2014
Dice on interposer with 100s of bits wide buses Logic die
2.5D
I/O Buffer w/o ESD Microball or copper stud Interposer traces (and 10x100µm TSVs)* Microball or copper stud I/O buffer w/o ESD
TSV-interconnected dice 1000s of bits wide buses Logic die
3D
Core logic I/O buffer Microball or copper stud (and 5x50µm TSVs)** Core logic I/O buffer Memory die
Memory die
Additional benefits: Less boardspace, thinner pkg, lower power 8
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Mary Meeker, KPCB, May 2014, pg 72 http://www.kpcb.com/internet-trends
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eda 2 asic Application-specific Memory Solutions • 1) Hybrid Memory Cube (HMC) – in a Package – Primarily for near and far memory in computers
• 2) High Bandwidth Memory HBM) – a Dice Stack – Primarily for designs with very wide busses, e.g. graphics
• 3) Wide I/O 2 – an Interconnect Standard – Primarily for high bandwidth and low power applications
• 4) Other Memory Solutions, e.g.: – a. Tezzaron’s DiRAM – b. Samsung’s V-NAND 10/16/2014
next presenter 10
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1) Hybrid Memory Cube Micron specifies that HMC offers, versus DDR3 DIMMs: - 15 x performance - 70% less energy/bit - 90% less space Sampling since early 2014. Production ramp-up end of 2014
http://www.hybridmemorycube.org/technology.html 10/16/2014
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eda 2 asic • • • • • • • • • •
HMC in a Package: Key Features
Four or eight 512 MB DRAMs stacked on a logic die TSVs connect these dice to 2 or 4 Gbyte cubes 64 memory vaults w separate memory controllers JTAG, BIST and repair, internal ECC logic Packet based data/command interface, 16 -128 Bytes Multiple 16 (or 8) lane full-duplex serial links 10, 12.5 or 15 Gbps SERDES I/Os Max. Bandwidth: 160 to 320 Gbytes/sec 896 pins BGA, 31 x 31 x 3.8 mm (1.2 x 1.2 x 1/8”) Intel announced 5 x performance gain with HMC http://www.hybridmemorycube.org/download/ HMC Spec 1.1 (123 pages) http://en.wikipedia.org/wiki/Hybrid_Memory_Cube 10/16/2014
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HMC Organization
http://www.hybridmemorycube.org/download/ 10/16/2014
HMC Spec 1.1 page 8 13
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2) HBM Die-Stack: Key Features
Four DRAM dice stacked - on an optional logic die Each die contains 2 independent channels Each channel is 128 bits wide and bi-directional 1 - 2 Gbps per signal at 500-1000 Mhz DDR 128-256 GB/sec Bandwidth per stack with 4 dice Four HBMs (2GB each) surround the Nvidia GPU on an organic interposer 1TB/sec bandwidth • Equals 3 x the BW of their previous GPU board • At 6-7 pJ/bit versus 18-22 pJ/bit with GDDR5 • • • • • •
http://www.jedec.org/standards-documents/results/jesd235 (124 pages) Also: Nvidia presentation at the June 2014 Memory Forum 10/16/2014
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HBM Architecture
http://www.jedec.org/standards-documents/results/jesd235 10/16/2014
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4K VIDEO Demands HDMI 2 (18 Gbps)
http://www.sandisk.com/goto/storage/?utm_source=WirelessWeek&utm _medium=display&utm_campaign=PhaseII2014&utm_content=OEM
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eda 2 asic 3) Wide I/O 2 Standard: Key Features • Spec supports 8, 16 and 32 Gbits SDRAM – Stacking 1, 2 and 4 memory dice on top of logic
• • • • • •
Max. BW: 34 Gb/s @ 4 channels, 68 Gb/s @ 8 Max. I/O speed: 1066 Mbits/s Unterminated CMOS I/O signaling Supply Voltage: 1.1 V 512 data bits total, 8 channels with 64 bits each Application: Low power & high BW designs, e.g.: – HD Video on smartphones and tablets JC 42.6 Committee:
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http://www.jedec.org/standards-documents/docs/jesd229-2 17
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Top View of Micropillar Assignment for one Wide I/O 2 Quadrant
http://www.jedec.org/standards-documents/docs/jesd229-2
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4a) DiRAM4TM 3D Memory
http://www.tezzaron.com/products/diram4-3d-memory/ 10/16/2014
… much more about DiRAMTM in the following presentation !
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eda 2 asic 4b) Samsung’s Monolithic 3D V-NAND • 128 Gbits of NAND Flash ⁻ ⁻ ⁻ ⁻ ⁻
24 layers of memory cells (next target: 96 layers) Vertically connected with high aspect ratio vias For NV storage, especially for Solid State Disks Smaller, lower power, faster vs “2D NAND” Introduced in Summer 2013; in production now http://www.samsung.com/global/business/ semiconductor/html/product/flashsolution/vnand/overview.html http://www.gizmag.com/samsung-vnand-flash-chip-ssd/28655/
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Agenda
• Introduction • How to Tackle the Dreaded Memory Wall… • … and Meet the Growing Functional Requirements of Specific Market Segments • Summary • Appendix 10/16/2014
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+ Energy Harvesters + MEMS + Image Sensors + Analog & RF + NV-Memory + DRAM + SRAM
Logic Source: IC Insights, Sept 2014
10/16/2014http://www.3dincites.com/2014/09/major-trends-shaping-future-ic-industry/
Consider Multiple-Dice in a Pkg
+ High Voltage/ Current
SoC Zone
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Major Market Share Changes, added Requirements
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Source: TSMC
CMOS Process Technology Evolution
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Design Starts per Node http://www.eetimes.com/ author.asp?section_id=36 &doc_id=1323755 (IBS Dec 2012)
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Source: Dr. Aart de Geus Keynote at SNUG 2014
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Heterogeneous Integration 2.5D
Interposer-based Design (“2.5D – IC“) + No TSVs to be added to dice + All dice accessible by heatsink + Low NRE, short Time-to-Market + Si interposer w integrated passives + Organic or glass interposer lower cost - Interposer cost increases unit cost - Interposer traces add delay & power 10/16/2014
3D
Vertically-stacked dice (“3D – IC“) + Highest performance at lowest power + Smallest formfactor, lowest footprint + Lowest unit cost (no interposer) - All but top dice need to have TSVs - Higher NRE, longer Time-to-Market - More thermal & mechanical challenges - Demands interconnect standards 25
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Agenda
• Introduction • How to Tackle the Dreaded Memory Wall… • … and Meet the Growing Functional Requirements of Specific Market Segments • Summary • Appendix 10/16/2014
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3D-ICs Demand Close Cooperation
Equipment
Materials Process
EDA
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Key Points
• Our industry will continue growing complexity and performance of semiconductor chips • Chips will contain ONE or MORE (heterogeneous) dice • Logic plus memory = most common combination, then Analog/RF, MEMS, CIS, Energy Harvesters,… • Consolidation in the supplier base will continue and drive towards a well-structured eco-system • We need standards to lower cost, risk, time-to-market • The ability to adapt determines future success 10/16/2014
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Agenda
• Introduction • How to Tackle the Dreaded Memory Wall… • … and Meet the Growing Functional Requirements of Specific Market Segments • Summary • Appendix 10/16/2014
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eda 2 asic Real Leadership Lessons of Steve Jobs
Focus Simplify Take responsibility end to end When behind, leapfrog Put products before profits Don’t be a slave to focus groups Bend reality Impute Push for perfection Tolerate only “A” players Engage face-to-face Know both the big picture and the details Combine the humanities with the sciences Stay hungry, stay foolish Innovators and Disruptor get rewarded!
10/16/2014
http://hbr.org/2012/04/the-real-leadership-lessons-of-steve-jobs/ar/1
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eda 2 asic Latest Book about 3D Memories covers -
History of 3D-ICs Types of transistors New memory technologies 3D V NAND Flash TSV use in 3D-ICs ….
http://www.amazon.com/dp/ 1118760514/ref=rdr_ext_tmb ( ~ USD 80.- for Kindle)
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eda 2 asic • • • • • • • • • • • • • • • • • • • • • • • • • •
Examples for 2.5/3D-IC Books
Vertical 3D Memory Technologies by Betty Prince (Oct 2014) Handbook of 3D Integration: Volume 3 – 3D Process Technology by Phil Garrou, Mitsumasa Koyanagi and Peter Ramm (June 2014) Design and Modeling for 3DICs and Interposers by Madhavan Swaminathan and Ki Jin Han (Jan 2014) Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia and Krishnendu Chakrabarty (2013) Advanced Flip Chip Packaging by Ho-Ming Tong, Yi-Shao Lai and C.P. Wong (Apr 4, 2013) Designing TSVs for 3D Integrated Circuits (SpringerBriefs in Electrical and Computer Engineering) Nauman Khan, Soha Hassoun (2012) Through-Silicon Vias for 3D Integration by John Lau (Sep 20, 2012) Chips 2020: A Guide to the Future of Nanoelectronics (The Frontiers Collection) by Bernd Hoefflinger (2012) Handbook of 3D Integration: Volumes 1 and 2 - Technology and Applications of 3D Integrated Circuits Garrou, Bower and Ramm (2012) Electrical Modeling and Design for 3D System Integration: 3D Integrated Circuits and Packaging, Signal Integrity... by Er-Ping Li (2012) Design for High Performance, Low Power, and Reliable 3D Integrated Circuits by Lim, Sung Kyu (2012) Design Technology for Heterogeneous Embedded Systems by Nicolescu, Gabriela, O'Connor, Ian and Piguet, Christian (2012) Semiconductor Packaging: Materials Interaction and Reliability by Andrea and Chen (2012) Handbook of Wafer Bonding by Peter Ramm, James Jian-Qiang Lu and Maaike M. V. Taklo (2012) Handbook of 3D Integration: Volumes 1 and 2 - Technology and Applications of 3D Integrated Circuits by Garrou, Bower, Ramm (2012) Stress Management for 3D ICs Using Through Silicon Vias:: International Workshop on Stress Management for 3D ICs... Ehrenfried Zschech, Riko Radojcic, Valeriy Sukharev and Larry Smith (2011) 3D IC Stacking Technology by Banqiu Wu, Ajay Kumar and Sesh Ramaswami (2011) 3D Integration for NoC-based SoC Architectures (Integrated Circuits and Systems) Abbas Sheibanyrad, Frédéric Pétrot ,Axel Jantsch (2010) Reliability of RoHS-Compliant 2D and 3D IC Interconnects (Electronic Engineering) by Lau, John H. (2010) More than Moore: Creating High Value Micro/Nanoelectronics Systems by Zhang, Guo Qi and Roosmalen, Alfred (2010) Wafer Level 3-D ICs Process Technology (Integrated Circuits and Systems) by Tan, Chuan Seng, Gutmann, Ronald J. and Reif, L. Rafael (2010) Three Dimensional System Integration: IC Stacking Process and Design by Papanikolaou, Antonis, Soudris, Dimitrios, Radojcic, Riko (2010) 3D Integration for NoC-based SoC Architectures (Integrated Circuits and Systems) by Abbas Sheibanyrad, Frédéric Pétrot and Axel Jantsch (2010) Ultra-thin Chip Technology and Applications by Burghartz, Joachim (2010) 3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme by Deng, Yangdong and Maly, Wojciech P. (2010) Three-dimensional Integrated Circuit Design (Systems on Silicon) by Pavlidis, Vasileios F. and Friedman, Eby G. (2010)
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eda 2 asic Major Conferences with 2.5/3D Content International Symposium on Microelectronics (IMAPS) 13-16 October 2014, San Diego, CA Annual Global Interposer Technology (GIT) Workshop GeorgiaTech 5-7 Nov 2014, Atlanta, GA International Wafer-Level Packaging (IWLPC) 11-13 Nov 2014, San Jose CA 3D Architectures for Semiconductor Integration & Packaging (3D ASIP) 10-12 Dec 2014, Burlingame, CA European 3D TSV Summit 20-21 January 2015, Grenoble, France International Solid-State Circuits Conference (ISSCC) 22-26 February 2015, San Francisco, CA International Symposium on Quality Electronic Design (ISQED) 2-4 March 2015, Santa Clara, CA IMAPS Device Packaging Conference 15-16 March 2015, Scottsdale, AZ Design, Automation, and Test in Europe (DATE) 9-13 March 2015, Grenoble, France IITC and MAM 2015 18-21 May 2015, Grenoble, France Electronic Components and Technology Conference (ECTC) 26-29 May 2015, San Diego, CA Design Automation Conference (DAC) 7-11 June 2015, San Francisco, CA SEMICON West 14-16 July 2015, San Francisco, CA 10/16/2014
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