IBM - T.J. Watson Research, New York, USA. NSF Workshop – 2/02/2012. 3D
Integration & Packaging Challenges with through-silicon-vias (TSV). Substrate ...
NSF Workshop – 2/02/2012
3D Integration & Packaging Challenges with through-silicon-vias (TSV)
Dr John U. Knickerbocker IBM - T.J. Watson Research, New York, USA
IBM Research
Substrate
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Acknowledgements IBM Research & S&TG - P. Andry - E. Colgan - B. Dang - T. Dickson - M. Farooq - C. Jahnes - J. Maria - R. Polastre - C. Tsang - C. Tyberg - B. Webb - S. Wright
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System Trends & 3D Technology Integration Benefits
Consumer / Network Appliances / Sensors
Applications
Applications
Low Cost
Power Efficiency
Pocket Size / Small Form Factor Increasing Function @ Same or Smaller Size Lower Power Local transactions Wireless
3
Computers / Servers / Cloud / HPC
3D
Performance
Power – Efficiency
- Multi-core
Technology
Scalability / Modularity Heterogeneous Integration Increasing BW / Function Lower Cost
- Multi-thread - High Bandwidth - Heterogeneous Integration
High Bandwidth / High Data Rate
Cost
Security
Security
High Volume / Time to Market
Reliability
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Packaging Integration Density
Integration Density (I/O per square cm)
I/O: 6 μm pitch 3D IC Integration 2,500,000 I/O / sq. cm Wiring pitch: 90 nm
Si on Si Package & Chip Stacking w / TSV
I/O: 50 μm pitch 40,000 I/O / sq. cm Wiring pitch: 2 μm
Organic & Ceramic Pkg (SCM & MCM) I/O: 200 μm pitch 2,500 I/O / sq. cm Wiring pitch: 50 to 200μm
I/O: 150 um pitch 4,400 I/O / sq. cm Wiring pitch: 40 to 150μm
Time 4
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3D Integration Advantages: Short vertical interconnects Miniaturization Higher Bandwidth / lower latency New Function in small form factor Lower power / energy savings Improved performance / streaming Lower Cost Challenges: Architecture / Design to leverage 3D technology Power Delivery / Thermal Mgt – Application Dependent Industry Compatibility & Standards MFG Equipment, Process, Assembly & Fine pitch Wafer Test 5
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3D-Technology Challenges & Readiness 3D Challenges
3D Readiness
1. 3D Architecture. Circuits, Timing, EDA Tools, Modeling
Data Library / Fabrication Rules
2. 3D Technology & Integration Elements
Material, Structure, Processes
- Thinned Si - Through – Silicon - Via (TSV) - Silicon - Silicon Interconnection (SSI)
Chip Stack
- Low power link - Module Integration - Assembly
- Test (WLT for KGD)
- Power delivery
- Cooling
3. Introduction of New Function or New Competitive Product - Industry Infrastructure, 3D Standards - 3D Products Volume Lower Costs Design / Architecture for lower costs Power Efficiency, Performance
Substrate Value Add - Miniaturization - Function (Perf., Power, Het. Integ.) - Standards
New Applications / Size / Function 6
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VLSI Design for Stacked Die with TSV’s
Design considerations for 3D stacked die with TSV’s - Design tools, know-how, micro-architecture - EDA tools - Physical floor planning & partitioning - Electrical design and models - Checking and verification - Power & thermal models
Processor Memory
Substrate
- Chip Infrastructure - Power & ground delivery and distribution - Clock distribution Processor
- IP Blocks
Memory
- Custom and random logic - SRAM, eDRAM and other memory - FPGA - Analog, special functions - In die-stack link - Off die-stack I/O
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Memory
Substrate
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3D Silicon Integration 3D Silicon Pkg Integration Cooling SSI Cu Wiring Silicon Package
Circuits , Trench Capacitors
TSV
Substrate
3D Die Stack & Si Pkg Integration TSV
Die Stack
SSI
Si Package Base Substrate
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Architecture - Design - Build - Characterization Few Examples of 3D Test Vehicles - TV’s silicon through via development - TV’s high density wiring, signal integrity
TSV
& cross talk (Si Carrier & Die Stack (TSV, Link & uC-4) - TV’s high I/O interconnection & chip stacking - TV’s active circuit die stacks (Funct., EDA, etc) - TV’s optical, thermal, module assessments - TV’s for reliability Cooling Chip Chip
Substrate
Si Si CMOS IC
Silicon Thru-via
OE
Decoupling Capacitors
Cooler Chip 1 Chip 2
waveguide
18-bump chain.
Organic Chip Package
*ECTC 2008 – Doany et al.
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High Bandwidth Wiring & Link characterization Wiring - Signal & Ground Test Vehicle
TSV Characterization (Example) - Inductance - DC resistance BEOL Characterization - Signal integrity vs Distance & Data rate - Far end X-talk: Design dependent
Micro-joint solder ( 25 um dia & 50 um pitch) - DC resistance - DTC - EM Decoupling Capacitors - 10 - 14 uF/cm2 demonstrated / with TSV
Chip To Chip & Chip Stack Link Characterization Modeling and Data Library - Signal integrity, Data rate, X-Talk, …. - Frequency & Time Domain
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High Bandwidth, Link Characterization & Energy Efficiency
Dickson et al. VLSI 11
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Thin die & Multi-high uC-4 Die Stack Assembly TSV = Cu or W TSV pitch = 50 um uC-4 = Solder uC-4 pitch = 50 um
Top Chip Si Die
Ceramic or Organic Substrate
Si Si Si Si carrier
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Farooq et al. IEDM 2011 / IEEE copyright 13
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3D-Technology Research & Manufacturing Summary
3D Integration
Dev / Mfg / Products -- Architecture
- Design / Structure / Size
-- Application Sizing
- Wafers 200 mm / 300mm
- - Cost Sizing
- Design Kits
- - Technology Qualifications
- Technology Platforms
- - Product Qualifications
Research
3D Chip
3D Stack & Si Pkg
Si Pkg
- Architecture / Design
- Assembly (C2C, C2W, W2W)
- Design Tools / Circuits
- IP Library & Models & Low power links
- TSV Dia, Pitch / Si Thickness
- Electrical, Mechanical, Thermal
- CMOS Wafer Integration & Finishing
- Test & Reliability
- Stack Interconnection size, pitch:
- Modeling Performance, Power, Cost
Time 14
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Summary Opportunity to Improve our Quality of Life Sensors Data Management Energy efficiency / Green Personal Handheld Servers & High Performance Computers
IBM 3D Technology Advancements / Mfg 3D Technology Elements TSV Higher density Die Stack Integration platforms Silicon Package Integration platforms Low power electrical interconnects 3D Stack & 2.5D Pkg
System / Hardware Demonstrations Application Dependent on 3D Architecture & Design Efficient Integration & Optimization over time Cost Benefits, Power Efficiency, Performance, Size, … 3D Silicon Integration Demonstrations
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Si Pkg
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