3D Monolithic Integration: stacking technology and applications
Ionut RADU, Bich-Yen NGUYEN, Gweltaz GAUDIN and Carlos MAZURE Soitec, Chemin des Franques, Parc Technologique des Fontaines, 38190 Bernin, France
[email protected] Abstract- Wafer level stacking of single crystal films enables 3D monolithic integration of electronic devices. The monolithic stacking technology based on Smart CutTM enables front end integration of large variety of devices with nanometer alignment capability; therefore it provides more degree of freedom for the designers and integration for high density and better performance. Several applications can fully take the advantage of using the monolithic 3D stacking technology. Keywords—wafer stacking, 3D monolithic, Front End integration.
I.
INTRODUCTION
3D integration technology is an emerging technology that complements conventional 2D scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically. The benefits of 3D IC stacking, such as increasing inter-die communication bandwidth, reducing form factor and lower power consumption are proven and the technology barriers to die stacking are being steadily removed. While several design and technology challenges still need to be solved, currently the biggest challenge for 3D-IC is the manufacturing cost factor which depends on the industry’s learning curve.
approach at the device level has been previously suggested in the early 2000 by many authors [1-3]. The 3D sequential integration, also called monolithic integration, would involve obtaining a thin crystalline template atop an already processed semiconductor substrate (CMOS, DRAM, etc). Hence, a new silicon surface on which new devices can be processed is available for front end of line device integration but at a temperature constrained by the underlying layer composition. The main challenge for the 3D sequential integration scheme resides on the development of low-thermal budget processes for obtaining high quality devices. Successful demonstration of various 3D sequential integration schemes within CMOS process has already been reported, the new crystalline template being obtained either by amorphous silicon deposition and subsequent crystallization [1] or by low temperature wafer bonding and layer transfer from an initial silicon on insulator (SOI) substrate [3]. In order to make such sequential integration a viable alternative for 3D IC fabrication, the development of low temperature 3D stacking processes compatible with high volume manufacturing is required. II. LAYER STACKING BY SMART CUT Smart CutTM technology [4] provides a path to monolithic 3D integration and enables the transfer of a blanket layer of single-crystal Si film onto a processed wafer (Figure 2). In combination with low temperature processing, layer transfer of very thin films (typical thickness is less than 1µm) onto CMOS processed handle wafers is achieved at the wafer level making the technology attractive for very high density vertical integration. Moreover, this integration scheme can be repeated in an iterative mode by using recycling techniques of donor wafer. B la n k e t W a fe r
Fig. 1.
P r o c e s s e d W a fe r
3D Integration: Transistor scaling & functional diversification
3D integration aims at providing highly integrated systems by vertically stacking and connecting various materials, technologies, and functional components together. In this emerging field, new technologies and integration schemes will be necessary to meet the associated manufacturing challenges. The current 3D-TSV technology for integrated circuits is struggling with challenges such as reliability, yield and process cost for high volume manufacturing. 3D integration
Fig. 2.
Schematic of layer stacking by Smart CutTM.
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Smart Cut without SPER Theoretical (TCAD simulation)
Al contact
P+ N+ SiO2 bonding layer
Handle Substrate
Current Density (A/cm²)
On this new single-crystal Si surface, a second level of devices can be processed and this integration can be repeated in an iterative mode. This technology benefits from existing high-volume manufacturing SOI infrastructure in addition to optimum donor wafer recycling techniques for lower cost-ofownership. Compared to standard back thinning techniques, the Smart Cut enables ultrathin films (down to few tens of nm) with excellent uniformity, thus simplifying and lowering the cost-of-ownership of the TSV process, or simply replacing TSV with cost effective regular backend vias instead, thus making this technology attractive for applications that require higher interconnect densities. The throughput of this process is ~20-25 wafers/hour because no critical alignment is required during the bonding process.
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dielectrics, metals, silicides
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Fig. 4.
I(V) diode characteristics after the low temperature layer transfer process [8].
Single crystalline films
III. Partially or fully processed wafers: e.g. CMOS, DRAM, etc Fig. 3.
Schematic of 3D monolithic stacking technology
There are a number of 3D stacking integration options enabled by Smart Cut - using low temperature oxide bonding [5] and metal-metal non-thermo compression bonding, enabling formation of electrical interconnects during the bonding process [6]. This is based on our ability to develop low temperature bonding processes that are critical for successful Smart Cut. Typical processing prior wafer stacking includes surface planarization of handle substrate (e.g. chemical-mechanical polishing of CMOS processed wafer) maintaining wafer edge quality and wafer micro-roughness
