micromachines Article
3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance Ying Wang 1, *, Chan Shan 2 , Wei Piao 1 , Xing-ji Li 3 , Jian-qun Yang 3 , Fei Cao 1 and Cheng-hao Yu 1 1
2 3
*
Key Laboratory of RF Circuits and Systems, Ministry of Education, Hangzhou Dianzi University, Hangzhou 310018, China;
[email protected] (W.P.);
[email protected] (F.C.);
[email protected] (C.-h.Y.) College of Information Engineering, Jimei University, Xiamen 361021, China;
[email protected] National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment, Harbin Institute of Technology, Harbin 150080, China;
[email protected] (X.-j.L.);
[email protected] (J.-q.Y.) Correspondence:
[email protected]
Received: 11 November 2018; Accepted: 11 December 2018; Published: 14 December 2018
Abstract: In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2 . Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id -V g ) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed. Keywords: bulk NMOS devices; radiation hardened by design (RHBD); total ionizing dose (TID); Sentaurus TCAD; layout
1. Introduction The total ionizing dose (TID) effect is one of the mechanisms that causes radiation-induced anomalies in semiconductor devices. The TID mechanism induces the generation of trapped charges in the dielectrics and interface states along the Si/SiO2 interfaces, causing degradation of a transistor’s performance [1–4]. Due to the downscaling, the net-charge trapping in oxides with a thickness of less than 10 nm is modest [5–9]. Since the thickness of the gate oxide of the simulated transistors is 2 nm, in this work, the net-charge trapping in the oxides is negligible. Therefore, the effects on thick oxides, such as the shallow trench isolation (STI), dominate the TID response of metal-oxide-semiconductor field-effect transistors (MOSFETs) [10]. Moreover, the charge trapped in the spacer oxide or at its interface modifies the parasitic series’ resistance, reducing the drive current [11]. In a conventional non-radiation-hardened single gate layout, the STI’s parasitic conduction path (the red arrow in Figure 1a) induced by the TID effect, which is visible only in an n-MOSFET, occurs along the sidewall oxide between the source and the drain, and leads to an increase in the drain current as the radiation dose increases [1]. A widely studied layout with radiation hardness, called the
Micromachines 2018, 9, 659; doi:10.3390/mi9120659
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enclosed gate layout [12–14], which requires tradeoffs in application [14,15], is presented in Figure 1b. For instance, a very small length ratio (W/L) is notisrealistic an Enclosed Layout Layout Transistor (ELT), for width which over the minimum achievable W/L 2.26 [15],for which is a significant Transistor (ELT), for which[16]. the minimum W/L is 2.26 [15],will which is aasignificant concern concern in analog circuits Moreover,achievable a larger gate capacitance cause longer time delay,in analog [16]. Moreover, larger gate capacitance will a longer time delay, which is not which is circuits not favorable for digitala circuits. A large footprint is cause another disadvantage of the enclosed favorable for digital circuits. A large footprint is another disadvantage of the enclosed gate layout. gate layout. In circuit design, the area penalty induced by design has been the main drawback [17]. In circuit design, the area penalty induced byand design has been main drawback In order to eliminate the parasitic path overcome thethe disadvantages of [17]. an enclosed gate order to eliminate parasiticlayout path and disadvantages of an layout,Infor the first time, an the n-MOSFET withovercome a Z gate isthe proposed. Moreover, theenclosed proposedgate Z layout, for the time, anto n-MOSFET layout withstructures, a Z gate is proposed. Moreover, the proposed gate layout is first applicable more complicated such as fin-field-effect transistorsZ gate layout is applicable to more complicated structures, such as[18–22]. fin-field-effect (FinFETs), (FinFETs), tunnel-field-effect transistors (TFETs), and nanowires In this transistors paper, devices with tunnel-field-effect transistors (TFETs), and nanowires [18–22]. In this paper, devices with the proposed the proposed Z gate layout achieve total-dose hardness by eliminating these edges, but at the Z gate layout achieve total-dose byasymmetric eliminating these but at the ofFigure fabrication expense of fabrication feasibility hardness due to the activeedges, area design, as expense shown in 1c. feasibility due to the asymmetric activelayout area design, as shown Figurecurrent 1c. First, effectivenessbyof First, the effectiveness of the proposed to eliminate the in leakage is the demonstrated layout eliminate thethe leakage current is demonstrated by Id -Vof Then,current, the total Idthe -Vg proposed curves. Then, thetototal shift of threshold voltage and the variation the leakage g curves. shift of theafter threshold voltage is and the variation of the leakage before and the after the radiation before and the radiation applied, are calculated for the current, single gate layout, enclosed gate is applied, are Z calculated for the single gate layout,the thethree enclosed gate layout, Z gate layout, layout, and the gate layout, respectively. Further, simulated layoutsand arethe compared with respectively. thevoltage three simulated are compared with respect the threshold respect to the Further, threshold shift andlayouts the leakage current increase as atofunction of thevoltage fixed shift and the leakage current increase as a function ofofthe chargetransistor density. Comparing static charge density. Comparing the static characteristics thefixed different layouts, it isthe found characteristics of the different transistor layouts, it is found that the Z gate layout exhibits the best TID that the Z gate layout exhibits the best TID response compared with the conventional layouts and response compared with the conventional layouts and ELTs. ELTs.
Figure1.1. Schematic Schematic structures thethe conventional layout, (b) the gateHlayout, and (c) the Figure structuresofof(a)(a) conventional layout, (b)Hthe gate layout, andproposed (c) the layout. STI, shallow isolation. proposed layout. STI, trench shallow trench isolation.
DeviceStructure Structureand andSimulation Simulation 2.2.Device TheZZgate gatelayout layoutachieves achievesthe theradiation radiationhardness hardnessby byintroducing introducingtwo twoshort shortextra extragates gatesthat that The separatethe the active active area area and should bebe noted thatthat the the precise, effective W/LW/L ratio separate and the theisolation isolationoxides. oxides.It It should noted precise, effective model of the proposed layout is not available at present; so, the channel width of the Z gate layout ratio model of the proposed layout is not available at present; so, the channel width of the Z gate in thisinwork is defined as shown in Figure 1c. A 1c. report [15] proposed an effective W/L W/L model of an layout this work is defined as shown in Figure A report [15] proposed an effective model gate gate layout, and and concluded that that the only way way to obtain a lowa aspect ratioratio is to is increase the L ofenclosed an enclosed layout, concluded the only to obtain low aspect to increase value. In the rectangular shape of an enclosed gate layout, the minimum W/L achievable is 2.26, and the L value. In the rectangular shape of an enclosed gate layout, the minimum W/L achievable is 2.26,is almost reached with L with = 7 um which considerable waste of area and largeand capacitance and is almost reached L =[15], 7 um [15],implies which aimplies a considerable waste ofaarea a large issue. Although a precise W/L model of the Z gate layout is not available at present, the drain current capacitance issue. Although a precise W/L model of the Z gate layout is not available at present, the level of the Z gate layout, when compared with the drain current of a single gate layout with the same drain current level of the Z gate layout, when compared with the drain current of a single gate W, L, and , V gt = V gsvoltage − V th ), (V is gtnearly thatsame. a Z gate layout withthe theoverdrive same W, voltage L, and (V thegt overdrive , Vgt =the Vgs same. – Vth),Itisassumes nearly the It layout does not need to increase the L value that high to achieve the same effective W/L with single assumes that a Z gate layout does not need to increase the L value that high to achieve theasame gate layout, hasgate a smaller footprint andhas gate capacitance. effective W/L and, with thus, a single layout, and, thus, a smaller footprint and gate capacitance. thesimulation, simulation,the themain mainparameters parameterswere werekept keptthe thesame samefor forall all three three layouts. layouts. The Thelateral lateral InInthe spacers were formed by a layer of SiO and a thick layer of Si N , and the STI was inserted using the 3 4,4and the STI was inserted using the spacers were formed by a layer of SiO2 2and a thick layer of Si3N SiO2.2Because . Becausethe theenclosed enclosedgate gatelayout layoutwas wasnot notable abletotoachieve achieveaasmall smallW/L W/LatatLL= =0.12 0.12μm, µm,the thevalues values SiO
of R1 and R2 were 0.15 μm and 0.27 μm, respectively, and the effective W/L was calculated by the formula given in [14], and it was equal to 13.6. The main parameters of the transistors in the simulation are listed in Table 1.
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of R1 and R2 were 0.15 µm and 0.27 µm, respectively, and the effective W/L was calculated by the formula given in [14], and it was equal to 13.6. The main parameters of the transistors in the simulation are listed in Table 1. The TID effect on the MOSFET was modeled by adopting the fixed-charge insulator model provided by the sentaurus technology computer-aided design (TCAD) software, which can be used to set a fixed charge density between the STI and the active region [23]. All simulations were performed using a hydrodynamic model with high-field saturation and mobility degradation models that included doping dependence and carrier–carrier scattering. We simulated the effects of the total radiation dose by increasing the fixed charge density on the sidewall oxide [24]. It should be noted that this work is focused only on the effects of fixed charges; so, the interface states were neglected for the reasons below. When a complementary metal-oxide-semiconductor (CMOS) device is exposed to radiation, hole trapping results in fixed charges and interface states in the thick oxides. According to a report on the radiation-induced fixed charge density and interface state density in MOS capacitors [25], the radiation-induced flat band voltage is predominantly shifted by the fixed charges. The effect of the interface states is minor. Therefore, in this simulation, the interface states were neglected, and only the fixed charge density was modified to reflect the total ionizing dose effect [24]. Moreover, the effects of interface traps were left out of the simulations due to a lack of empirical information about several parameters of interface traps, such as trap energy and density and the capture cross-section, which are necessary for accurate simulations [26]. In addition, we can see from the literature [26] that the tendencies of ∆V th and ∆SS extracted from the simulation results are in good agreement with those from the experimental data of 5 Mrad. Through the three-dimensional (3D) simulation results, they confirm that, for sub-100 nm gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), the fixed charges in the gate spacer predominantly determine ∆V th and ∆SS, i.e., the TID effect. Note that interface traps were not taken in the simulation in this paper. Although that may result in some disagreement in the current levels as obtained with the experimental counterparts, this case does not have much impact on our findings, because the focus of this paper is not on the exact values of currents but on the general trends and relative results of Z gate, enclosed gate, and single gate layouts due to the TID effect. Table 1. The parameters that were used for the device’s simulation. Parameter
Value
Length of channel Width of channel Thickness of n-type poly gate Thickness of gate oxide Doping of source/drain region Depth of source/drain region Doping of p-type substrate
0.12 µm 0.21 µm 100 nm 2 nm 1.0 × 1019 cm−3 100 nm 4.0 × 1017 cm−3
3. Results and Discussion 3.1. The Id -Vg Simulation Results In order to verify that the Z gate layout is able to work well in a non-radiation environment, we simulated the Id -V g curves of the Z gate layout, the enclosed gate layout, and the single gate layout at the fixed charge density of 3 × 1010 cm−2 to model the non-radiation scenario. The following simulation results focus on the analysis of the radiation tolerance characteristics of the proposed layout. The degradation of devices is mainly characterized by the threshold-voltage shift and the off-state leakage current [27]. As we know, IDSS is the maximum current that flows through a FET transistor, which is when the gate voltage (VG) supplied to the FET is 0 V. Additionally, it is only valid when the FET transistor is a junction field-effect transistor (JFET) or depletion MOSFET. However, as the proposed Z gate layout transistor is an enhanced MOSFET, we think that the parameters of IDSS and
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the IDSS /Ioff ratio are unnecessary to investigate. The threshold-voltage is determined by the linear extrapolation method inPEER the linear region; thus, the simulation was performed with a very small 4Vof DS8, Micromachines 2018, 9, x FOR REVIEW i.e., 20 mV, 50 mV, and 100 mV [24,27,28]. In this paper, V DS was taken as 20 mV. Moreover, the TID effect will be more serious when V DS reaches V DDcharges [27]. This mainly attributed to the fact that mainly attributed to the fact that more trapped at can the be STI/body interface will sufficiently more trapped chargesbarrier at the STI/body will sufficiently reduce the potential barrierInand result reduce the potential and resultinterface in a larger leakage current at a high drain voltage. addition, in current a high drain In addition, a 20 mV bias gives thea larger use ofleakage a 20 mV drainatbias gives thevoltage. best results for thethe Z use gateoflayout in drain comparison to the the best results for the Znot gateshown). layout Thus, in comparison to thethe alternatives (results shown). Thus, this alternatives (results in this paper, three layout types not are simulated at theindrain paper, layoutsweeps types are the drain of 20 mV, which sweeps the gate bias from bias ofthe 20 three mV, which thesimulated gate biasat from 0 V tobias 1.5 V. results of the Id-Vg curves of the single gate layout are shown in Figure 2a, where 0 V toThe 1.5 simulation V. it can besimulation seen that the leakage significantly increases as the are fixed charge density The results of thecurrent Id -V g curves of the single gate layout shown in Figure 2a,increases, where it andbethat slightly as increases the fixedascharge density The simulation can seenthe thaton-current the leakageincreases current significantly the fixed charge increases. density increases, and that results of the Idincreases -Vg curvesslightly of the enclosed gate layoutdensity are shown in Figure where the Id-Vg curves the on-current as the fixed charge increases. The2b, simulation results of the overlap with each other, demonstrating a small impact of the TID effect on the enclosed gate Ialmost -V curves of the enclosed gate layout are shown in Figure 2b, where the I -V curves almost overlap d g d g layout. with each other, demonstrating a small impact of the TID effect on the enclosed gate layout. The simulation simulation results results of ofthe theIIdd-V -Vgg curves of the Z gate layout are shown shown in in Figure Figure 2c, 2c, wherein wherein The slightly as as thethe fixed charge density increases. The itit can be seen seen that thatthe theleakage leakagecurrent currentincreases increases slightly fixed charge density increases. radiation tolerance characteristic of theofZthe gate was verified by comparison with that the The radiation tolerance characteristic Z layout gate layout was verified by comparison withofthat single gate layout. The curves of the Z gate layout areare similar totothose of the single gate layout. The curves of the Z gate layout similar thoseofofthe theenclosed enclosed gate gate layout; namely,the the leakage current increased very little as charge the fixed charge density increased, namely, leakage current increased very little as the fixed density increased, demonstrating −2 , demonstrating that the Z radiation gate layout was radiation tolerant the fixed at12the that the Z gate layout was tolerant at the fixed chargeatdensities at charge the STI densities of 3.5 × 10 cmSTI of 3.5 × 10as12 the cm−2enclosed , the same as layout. the enclosed gate layout. the same gate
(a)
(b)
(c)
Figure2.2. The The simulation simulation results resultsof ofthe theIIdd-V -Vgg curve of (a) the single gate gate layout, layout, (b) (b) the the enclosed enclosed gate gate Figure layout,and and(c) (c)the theZZgate gatelayout. layout. layout,
3.2. 3.2. Comparison Comparison of of Key Key Transistor TransistorPerformance PerformanceParameters Parameters To TID response of the fairly,fairly, the threshold voltagevoltage and leakage Tocompare comparethe the TID response of transistors the transistors the threshold and current leakage 10 − 2 12 −2 to model parameters were extracted at the fixed charge density of 3 × 10 cm and 3.5 × 10 cm 10 −2 12 current parameters were extracted at the fixed charge density of 3 × 10 cm and 3.5 × 10 cm−2 to the pre-the andprepost-radiation scenarios, respectively. The results the threshold voltage and leakage model and post-radiation scenarios, respectively. Theofresults of the threshold voltage and current listedare in Tables 2 and 3, 2respectively. leakageare current listed in Table and 3, respectively. In In Table Table2,2,the thethreshold thresholdvoltage voltageof ofthe thenon-radiation-hardened non-radiation-hardened single single gate gate layout layout at at prepre- and and post-radiation is 363 mV and 138 mV, respectively, and the total shift is 225.56 mV; for the post-radiation is 363 mV and 138 mV, respectively, and the total shift is 225.56 mV; for the other other two two radiation-hardened radiation-hardened layouts, layouts, the the total total shift shift is is below below 30 30 mV. mV. Thus, Thus, regarding regarding the the shift shift value value in in descending order, the order of three layout types is the single gate layout, the Z gate layout, descending order, the order of three layout types is the single gate layout, the Z gate layout, and and the the enclosed enclosedgate gatelayout. layout. Table 2. Vth in the pre- and post-radiation scenarios. Layout single gate enclosed gate Z gate
Vth-pre (mV) 363 374 354
Vth-post (mV) 138 374 329
ΔVth (mV) 226
