1 Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA. 2 University of California, Los Angeles, Los Angeles, CA. Abstract - This paper ...
A 65nm CMOS 140 GHz 27.3 dBm EIRP Transmit Array with Membrane Antenna for Highly Scalable Multi -Chip Phase Arrays 2 2 12 ] l 2 2 Adrian Tang , Nacer Chahat , Yan Zhao , Gabriel Virbi/a , Choonsuip Lee , Frank Hsiao ' Li Du , Yenl 2 Cheng Kuan ,Mau-Chung Frank Chani, Goutam Chattopadhya/ , Imran Mehdi 1
Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 2 University of California, Los Angeles, Los Angeles, CA
Abstract - This paper presents a scalable transmit phase
II. LOCALLY SYNCHRONIZED ARRAYS
array operating at 140 GHz which employs a local PLL reference generation system. Unlike traditional CMOS phase arrays, this
LO Distribution with Global Synchronized
LO Distribution with Local Synchronized
enables the array to be formed over multiple chips while avoiding
GS-PLL (High Frequency distribution)
LS-PLL (Low Frequency distribution)
the challenges of distributing mm-wave signals between them. The prototype chip consumes 131 mW of power and occupies 2 of chip area when implemented in 65 nm CMOS
1.95 mm
technology.
Index Terms - Locally Synchronized PLL, Phased Array Transmitter.
o
c:: o
I. INTRODUCTION
While
mm-wave
combining
phase
arrays
:�
m20 E::!..
enable
efficient
power
[1], beam-steering for mm-wave imaging and
detection [2], and Gb/s wireless data-links over I-10m ranges
�
� 40
1- .....
o .....
t-
'r=------.
1.0mm 10mm Array Size (m)
[3], the maximum antenna gain they can provide remains limited by their effective aperture or physical size they can offer. Large array gain is highly desirable for enabling increased communication distances and higher resolution imaging/radar systems which need narrow beams (typically diffraction limited by aperture). While prior work in phase arrays
offers
excellent
performance
for
their
.....
100mm
(e) Fig. 1 (a) Conventional single-chip phase array using a high-frequency LO distribution network with a globally synchronized PLL (GS-PLL). (b) Multi chip array approach where a low frequency reference is distributed to multiple SoC chips. (c) LO transmission loss vs. array size for a low-frequency off chip (LS-PLL), and high-frequency on-chip (GS-PLL) based LO distribution network approach.
intended
applications, each was implemented with all array elements on
We propose a new approach to enable multi-chip phase
a single chip. These existing arrays first generate a mm-wave
arrays where the array size is only thermally & mechanically
LO using a globally synchronized PLL (GS-PLL) locked onto
limited. As shown in Fig 1b, each pixel contains a local
an external reference, and then distribute this LO to each pixel
synchronized PLL (LS-PLL) which locally generates the mm
on chip as depicted in Fig la. This Single chip implementation
wave LO from a low-frequency reference signal which is
employing a GS-PLL directly limits the scalability to the
distributed across the array. Figure lc shows the transmission
larger array sizes (and effective apertures) for several reasons:
losses of distributing a 140 GHz LO on-chip with the
1) the maximum die size is limited by adverse effects to the
conventional GS-PLL approach as a function of array size,
overall chip yield, 2) the losses of the LO distribution network
and compares it with the proposed LS-PLL approach where
become unmanageably high for large array sizes, and, 3)
only the low frequency 50 MHz is distributed across a PCB
physical limitations are imposed by wafer size. Given these
substrate. As seen in Fig lc, the conventional global approach
constraints, phase array systems formed across multiple dies
becomes impractical beyond several mm as LO distribution
or even wafer sections are needed for implementing larger
losses become too-high and large numbers of amplifiers would
arrays. While constructing an array across multiple die is
be required, while the local synchronized PLL based approach
conceptually simple, LO distribution becomes a challenging
incurs almost no loss even at large array sizes. Additionally,
problem. While small on-chip arrays benefit from relatively
by adding a tunable time delay to each pixel's reference signal
low-loss distribution of mm-wave LOs, the LO path in a
path,
multi-chip array is subject to interconnect and assembly losses
accomplished without the need for an mm-wave phase shifter
beam-forming
and
beam-steering
operations
are
of PCB traces and flip-chip bumps or bond-wire connections.
in the RF or LO signal path.
978·1-4799-3869-8/14/$31.00 ®2014 IEEE
The antenna for each pixel is provided by a specialized membrane
��::�����:-+--+----!-+� Digital Control
antenna
module,
which
was
developed
for
spaceflight applications at NASA's Jet Propulsion Laboratory. These antennas are fabricated by deposing gold onto a 1.0 um thick silicon-nitride membrane implemented on top of a silicon support window designed to make the membrane coplanar with the surface of the CMOS chip.
Connection
between the antenna and SoC chip is provided by a beam-lead transmission line, which is essentially a back-etched extension Fig. 2. Detailed block diagram of the system-on-chip (each SoC is an separate array pixel) with externally originating low-frequency reference and digital control signals.
of the metallization used for the antenna structure. The antenna structure and performance is described in Fig 4. Membrane Antenna Cross Section
r-;:;;;;;=--nil-...................,.� Sil.,.,itride
In order to demonstrate a phase array based on LS-PLLs we have implemented the pixel SoC transmitter with block diagram shown in Fig 2. In this prototype pixel, the time delay
Top View
nJfnll�
setting and other control functions of each element SoC are controlled by an addressable USART bus (each element has unique address ID). Upon entering the chip, the low-frequency
-300
z
reference signal first encounters the digitally controlled time
Theta
300
(0)
H-Plane Pattern
delay which allows for pixel-relative phase-shifting of the LO generated by the proceeding local PLL. The LS-PLL is a higher-frequency
variant
of
the
frequency
multiplying Phi (0)
synthesizer presented in [4] with digital frequency tuning (DiCAD), and a wide range of bias adjustments in the charge pump, mm-wave stages, and divider stages, all accomplished by embedded calibration DACs placed throughout the Soc. The transmitter chain is implemented as a cascade of 6 stages, again with digitally adjustable biases at each stage. The front
[TRP/P,.-l [(4nPmR')/(Pp,.,..A...1l
63%
Radiation Efficiency
7.7 dBi
Peak Gain
Fig. 4. Mechanical construction of the coplanar membrane antenna, beam-lead interconnect structure, and measured radiation performance. (Measured powers used for calculating antenna gain/efficiency are discussed in Fig 3.)
end design and performance is summarized in Fig. 3. In order for beam-steering to occur correctly, not only the phase, but the amplitude of each element must be well controlled.
While
power
matching
each
element
is
conceptually simple, its implementation is complicated by both die-to-die and assembly variations. These variations prohibit equalized power to be delivered by each element through an open loop approach. We therefore adopt a closed loop Transmitter
Cham Measurements
Transmitter Center Frequency
Output Power
Transmitter Probed
at
the
challenge
presented
by
die-to-die
and
assembly
variations is that the digital tuning and bias settings to achieve PLL locking within the synthesizer may not be fixed from
U+-+�8
element to element. For this reason the control voltage is also monitored by the ADC (selectable through a multiplexer) to allow tracking of PLL locking conditions. Once the PLL's
Measured Power
captured at 5mm
��
integrated
order to accomplish such purposes, a 10 bit, 1.5bit per stage second
Flange
sensor
cycle-pipelined ADC is integrated within the pixel Soc. A
na:::dhuP Waveguide
power
transmit power by manipulating power amplifier biases. In
13.2 dBm
Transmitter EIRP
Surface
a
139.SGHz
Transmitter 3 dB Power Bandwidth
Chip
with
transmitter output to continuously monitor and regulate the
11.21 dBm
Total Radiated Power
approach
Value
�w::-
MeawredPower
A.....l.W.O.I·
PM·O.ldBm
'--,,-'---.---.
EIRP =
PM
"n1::m�
TRP =
PM
(5::�
I'lant
=
control voltage approaches either Vdd or ground, the PLL will JJGnIS,CD) sinlS) dCDdS
pro�:�wer X 100"
Fig. 3. IX mm-wave front-end schematic diagram and measured output power performance for a single array pixel. Note: Ihe frequency response measurement is limited to the locking range of the frequency tripler in the LO path and reports power captured by the open waveguide. IRP is computed from the antenna efficiency and probed output power of the Ix.
be considered unlocked. Alternatively, if the control voltage settles between 25% and 75% of Vdd, locking is considered achieved. Using this approach, the bias and tuning settings of each synthesizer in a pixel SoC are manipulated while control voltages are monitored to ensure the entire array is coherent
978'1-4799-3869-8/14/$31.00 ®2014 IEEE
with respect to the globally distributed reference. This process occurs as soon as the array is initialized. �-------,
!.� !flU '"
.:'t.
iE'
..
.t
•.....=�.I ., 30cm Mechanical Stage (AVEI)
iO·5ddBB ·10
f�::'�;or
·15
Azimuth
(b)
(e)
Fig. 5. (a) Photograph of test PCB with prototype 2x4 multi-chip array. (b) Measurement setup diagram. (c) NormalIzed beam patterns of With the beam steered at + 15° (top), and _25° (bottom) offset In aZimuth achieved through adjustment of digitally controlled time delays for each pixel.
Fig. 7. CMOS die photo of the Tx Pixel SoC for the multi-chip phase showing major circuit blocks.
III.
In order to characterize the multi-chip LS-PLL based phase array,
a
PCB
was
constructed
capable
of
supporting
8
elements in a 2x4 array configuration as shown in Fig. 5. Each chip is pin-programmed with a wire-bonded address ID. In future designs integrated flash memory can take the place of the mechanical pin programming. The total radiated power, EIRP, array radiated power, and antenna efficiency, are again characterized using the open waveguide approach shown in Fig 3. Finally, in order to demonstrate the beam-steering properties of the prototype phase array, a programmable motorized azimuth/elevation stage was used in combination with a power detector to measure the normalized radiation pattern while two different digital time delay settings were
CONCLUSIONS
In summary, we have demonstrated a new technique based on local LO synthesis to enable multi-chip and highly scalable phase arrays. The measured DC power consumption of the prototype pixel chip is 131 mW. The SoC pixel occupies a 2 total die area of 1.95 mm . Fig. 6 compares our pixel SoC design with that of prior arts for phase array transmitters. As seen, the area and power overhead of extra circuit blocks (ADC + PLL) to enable multi-chip arrays with large array scalability is very competitive against other state-of-the-art designs. Fig. 7 shows a die photo of the prototype SoC pixel CMOS chip with major circuit blocks identified.
applied to each pixel. Two beam-steering cases (-25° and ACKNOWLEDGEMENT
+15°) are shown in Fig. 5, and while the captured beams may
not be as well focused as on-chip arrays with precisely controlled element spacing,
they do show beam-steering
operation is attainable by applying a time delay to the reference signal of the multi-chip array. (1]
nilS Work
JSSC
National Aeronautics and Space Administration.
2012
ISSCC 2013
Multi·Chip
Single·Chip
Single-Chip
LO Distribution
Local PLL
NoPLL
GlobalPLL
140
280
94
Power Consumption
131
51.51
150
PerPixel (mm� Total Radiated
PowerPer Pixel
�
Total Array EIRP' (dBm) Technology
REFERENCES
[I]
Frequency (GHz)
Chip Area
California Institute of Technology, under a contract with the
(2]
Array Configuration
PorPjx�
The authors are grateful to TSMC for 65nm support. Part of this work was carried out at the Jet Propulsion Laboratory,
_
.ill),
fTX' PLL • ADC) ,
0.45
1.95 -
+10.2 dBm'
(84rnW 1 8 alemenls)
l-
.(f)(' PLL), 0.95
·19.6 dBm
·9dBm
(190uW 116 alemenls)
(0.316mW 14 alemenls)
27.3
9.4
Not Reported
65nm CMOS
45nm SOl CMOS
65nmCMOS
Fig. 6. Performance summary of demonstrated 140 GHz multi-chip phase array and comparison with state-of-art phase. *TRP is measured for all . elements and normalized to the number of pixels. ThiS value Includes the array combining losses unlike the single pixel TRP (quoted in Fig 3.)
K. Sengupta and A. Hajimiri, "A 0.28THz Power-Generation and Beam-Steering Array in CMOS based on Distributed Active Radiators," IEEE Journal of Solid-State Circuits, vol. 47, no. 12,
[2]
pp. 3013-3031. . Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jn Lee:
A
94GHz
3D-image
radar
engine
with
4TX/4RX
beamforming scan technique in 65nm CMOS. IEEE Int'l Solid State Circuits Conference (ISSCC), Feb. 2013. [3] Kim, Sang Young, and Gabriel M. Rebeiz. "A low-power BiCMOS 4-element phased array receiver for 76-84 GHz radars and comm systems." IEEE Journal of Solid-State Circuits, vol 47 no 2, pp 359-367. [4] A. Tang, et-al, "D-Band Frequency SynthesisUsing aU-band PLL and Frequency Tripier in 65nm CMOS Technology", IEEE International Microwave Symposium (IMS 2012), July 2012
978·1-4799-3869-8/14/$31.00 ®2014 IEEE
