5 overview of direct torque control of induction machines

First Edition 2008 © NIK DIN MUHAMAD 2008

Hak cipta terpelihara. Tiada dibenarkan mengeluar ulang mana-mana bahagian artikel, ilustrasi, dan isi kandungan buku ini dalam apa juga bentuk dan cara apa jua sama ada dengan cara elektronik, fotokopi, mekanik, atau cara lain sebelum mendapat izin bertulis daripada Timbalan Naib Canselor (Penyelidikan dan Inovasi), Universiti Teknologi Malaysia, 81310 Skudai, Johor Darul Ta’zim, Malaysia. Perundingan tertakluk kepada perkiraan royalti atau honorarium. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical including photocopy, recording, or any information storage and retrieval system, without permission in writing from Universiti Teknologi Malaysia, 81310 Skudai, Johor Darul Ta’zim, Malaysia. Perpustakaan Negara Malaysia

Cataloguing-in-Publication Data

Modelling and control of power converters and drives / editor Nik Din Muhamad. Includes index ISBN 978-983-52-0648-1 1. Electric current converters. I. Nik Din Muhamad. 621.313 Editor: Nik Din Muhamad Pereka Kulit: Mohd Nazir Md. Basri & Mohd Asmawidin Bidin Diatur huruf oleh / Typeset by Fakulti Kejuruteraan Elektrik

Diterbitkan di Malaysia oleh / Published in Malaysia by PENERBIT UNIVERSITI TEKNOLOGI MALAYSIA

34 – 38, Jln. Kebudayaan 1, Taman Universiti, 81300 Skudai, Johor Darul Ta’zim, MALAYSIA. (PENERBIT UTM anggota PERSATUAN PENERBIT BUKU MALAYSIA/ MALAYSIAN BOOK PUBLISHERS ASSOCIATION dengan no. keahlian 9101) Dicetak di Malaysia oleh / Printed in Malaysia by UNIVISION PRESS SDN. BHD.

Lot. 47 & 48, Jalan SR 1/9, Seksyen 9, Jalan Serdang Raya, Taman Serdang Raya, 43300 Seri Kembangan, Selangor Darul Ehsan, MALAYSIA.

v

Contents

CONTENTS

Preface

vii

Chapter 1

Control Loop Design of DC-DC Converter Systems Using PSpice

Chapter 2

Simulation of Power Converters with Sliding Mode Control Using PSpice

18

Chapter 3

Dynamic Evolution Control for Step-down DC-DC Converter

37

Chapter 4

Digital PI Controller Design for Power inverter Using MATLAB-SIMULINK

50

Chapter 5

Overview of Direct Torque Control of Induction Machines

67

Chapter 6

Study on Stability and Performances of DTC Due to Stator Resistance Variation

99

Chapter 7

A Quick Dynamic Torque Control for Direct Torque Control Hysteresis-based Induction Machines

118

1

vi

Contents

Chapter 8

Improved Torque Capability through Overmodulation for Direct Torque Control Hysteresis-based Induction Machines

133

Chapter 9

The Modeling and Simulation of Improved DTC of PMSM Drives Using Matlab/Simulink

148

Chapter 10

Modeling and Simulation of a Network of Adjustable Speed Drives

162

Index

175

vii

Preface

PREFACE

Power electronics technology is used for efficient control of motors in electric cars, industrial and consumer motor drives, and the development of more reliable, lightweight switching power supplies for sophisticated computer and communication equipment. Recent advances in microprocessor technology are leading to the integration of microelectronics and power electronics technologies for smart and efficient control of motor drives and power supplies. Switching power supply research has been spurred by needs for higher performance, smaller size, and lighter weight power sources to be compatible with the shrinking size of all forms of communication and data handling systems. Everyday usage of portable battery operated equipment in everything, from home appliances and hand-tools to mobile communication devices, has also prompted increased switching power supply research. Static DC-DC converters and DC-AC inverters provide natural interfaces with new direct energy sources such as solar cells, fuel cells, and thermoelectric generators, and form the integral part in most uninterruptible power sources. Energy Conversion Department has emerged as a leading department for power electronics and drive research and education in Malaysia. Research programs undertaken by the department are diversified and include the following disciplines: modeling, simulation, and control of power electronics; grid-connected inverters, inverters for photo-voltaic (PV) applications; and electric drives.

viii

Preface

A vast amount of technology in switching power supply and electric drives has been generated at ENCON in the past three years. The research results have been published in numerous conference proceedings and technical journals. These papers serve as invaluable teaching tools and reference guides for power electronics engineers. To facilitate future referencing, ENCON has organized in three books. Each book is grouped according to these topical areas: Part I : Modeling and Control of Power Converters and Drives Part II : Recent Advances in Power Inverters Part III : Power Electronics Applications in Renewable Energy ENCON will strive to maintain, update and expand the series. Future plans for Energy Conversion Publication Series are additional books with new topics of interest to industry and power electronics community.

Nik Din Muhamad Faculty of Electrical Engineering Universiti Teknologi Malaysia 2008


1

1 CONTROL LOOP DESIGN OF DC-DC CONVERTER SYSTEMS USING PSPICE Nik Din Muhamad Abdul Jaafar Shafie

1.1 INTRODUCTION In recent years, there are many SPICE-based models developed for simulating dc-dc converters. In general, three types of model can be identified: the detailed model, the large-signal averaged model, and the small-signal model. All three models are valuable in analysis and design of dc-dc converter systems. The smallsignal model is required to design the control system of a dc-dc converter. There are a number of well-documented techniques and guidelines for designing the control system of a dc-dc converter [16]. Nevertheless, the design of a feedback compensator is still not a simple task, especially for a new designer. The task involves the tedious, mechanical and human error prone computation of the transfer functions, and repetitive fine-tuning of compensation network component values. Moreover, the designer’s judgment and experience are often required in the design process. In this paper we demonstrate that the design guidelines can be programmed in compact form in PSpice. For this purpose, an option available in PSpice called Analog Behavioral Modeling (ABM) is used. We choose to program the control loop design procedure [4] due to its generic, systematic and a widely adopted procedure [7-10]. The chosen design procedure is made as a subcircuit model and stored in PSpice’s library. In this manner,

2

Modeling and Control of Power Converters and Drives

the design procedure is treated as a library component, which makes it easy to use. The methodology of development is presented in detail. The presence of the design guideline’s subcircuit model along with the existing models makes a new approach to using PSpice simulator in the design process. The proposed approach includes both design as well as simulation tools thus making extensive use of the SPICE in dc-dc converter design cycle. Moreover, both the flexibility and capability of SPICE as a stand-alone program can be enhanced. Using SPICE-aided design approach in dc-dc converter development can reduce the time and cost. Throughout this paper, a buck converter with voltage mode control is used as an example to develop and verify the control loop design procedure. The general procedure, however, can still be readily extended to include other converters with different control schemes provided that their transfer functions and design guidelines are available. 1.2 DESIGN BASED ON SMALL SIGNAL MODEL 1.2.1 Buck Converter Power Stage

The buck converter power stage with PWM modulator of this study is depicted in Fig. 1. We assume that the converter is operated in continuous conduction mode. Using the averaging and linearization techniques, the control-to-output transfer function of the buck converter including PWM modulator, can be obtained as: ⎛ s ⎞ ⎜⎜1 + ⎟ ω zESR ⎟⎠ vˆo ⎝ = g co vˆc s s2 1+ + Qω o ω o2 where

(1)


g co =

Vg Vp

,

ωo =

1 LC

, ω zESR

=

3

R 1 , and Q = rC ω oL L

+ C

Vg +

-

R

Driver

vo -

PWM Modulator d

+ Comparator

vc Vp Sawtooth Generator

Figure 1 Buck converter with PWM modulator

It can be seen from (1) that the control-to-output transfer function is dependent on the operating point. As the operating point of the converter is wide, the conventional way of designing the controller involves selecting the worst case operating point that is under the minimum line voltage (minimum Vg) and maximum load current (minimum R) conditions 1.2.2 K-factor Approach

The loop shaping approach is simple and effective for dealing with the plants having complex dynamic behavior. Among popular loop shaping method in power electronic applications is K-factor approach, introduced by [4]. The main feature of K-factor approach is that the pole-zero placement and resultant circuit component values can be obtained without trial-and-error. That is one of the reasons why the k-factor approach widely accepted by

4


many researchers [6-10]. The type-3 K-factor compensator is frequently used for compensation of buck, boost and buck-boost circuits due to its ability to provide the phase boost, Øboost: 0 ≤ φ boost ≤ 180 o (2) The transfer function of the type-3 K-factor compensator is given by

Gc ( s ) =

⎞ ω co ⎛ K ⎜ s + 1⎟⎟ ⎜ Aco K ⎝ ω co ⎠ ⎛ s ⎞ + 1⎟ s⎜⎜ ⎟ ⎝ K ω co ⎠

2

2

(3)

where ωco is the desired crossover frequency, K is the pole frequency and zero frequency control factor. The value of K can be adjusted depending on the phase boost (Øboost) required to make the phase compensation. Given the desired phase margin, PM, and the crossover frequency, ωco, the phase boost that the compensator should be provided: φ boost = PM − 90 o − φ co (4)

and the K-factor is calculated from equations 2 and 3 as: ⎛φ ⎞ K = tan 2 ⎜ boost + 45 o ⎟ ⎝ 4 ⎠

(5)

It is important to point out here that this design procedure is general in the sense that it can be used to any suitable application. For specific application, this design procedure must be suited to the requirements of those applications. In the case of buck converter, an important constraint is that the crossover frequency must be less than one-fourth of the switching frequency. This constraint is required to avoid the large signal instability [1].


5

1.2.3 Type-3 K-factor Error Amplifier Fig. 2 shows the circuit diagram of the type-3 K-factor error amplifier or compensation network. The compensation network consists of the circuit elements as follows: C1, C2, C3, R1, R2, R3, and Rbias. This network has three poles and two zeros. C3 C2

C1

R2

R1

R3

+ vc

-

vo

Rbias

Vref

Figure 2 Type-3 K-factor compensation network

The small-signal transfer function for the compensation network is given by

vo 1 = (−1) × vc s (C 2 + C 3 ) R3 (1 + s( R1 + R3 )C1 )(1 + sR2 C 2 ) ⎛ ⎛ C C ⎞⎞ (1 + sR1C1 )⎜⎜1 + sR2 ⎜⎜ 2 3 ⎟⎟ ⎟⎟ ⎝ C 2 + C3 ⎠ ⎠ ⎝ or

(5a)

6


ω (1 + s ω z1 )(1 + s ω z 2 ) vo = (−1) i vc s (1 + s ω p1 )(1 + s ω p 2 )

(5b)

By matching (5a) and (5b) we can obtain

ωi =

1

R3 (C 2 + C 3 ) 1 ω z1 = ( R1 + R3 )C1 1 ω z2 = ( R2 C 2 ) 1 ω p1 = R1C1

ω p2 =

1.3

C 2 + C3 R2 C 2 C 3

(7) (8) (9) (10)

(11)

PROPOSED APPROACH Figure 2 shows the flowchart of the overall procedure to determine component values of the error amplifier. The flowchart consists of three computational blocks: power stage, K-factor, and compensator. The computation is, therefore, performed in three steps: I. The first step is to determine the magnitude, Aco, and phase, Øco, of the power stage Gp(s) at the crossover frequency, fco, which are executed in the block of power stage. The inputs to the block are: the input voltage, vg, the value of L, the value of C, the load equivalent resistance R, the ESR capacitor, r. Besides, the user must also supply to the block the value of crossover frequency, fco.


7

II. By knowing Aco and Øco, and specifying the desired phase margin, PM, the block of K-factor can be employed to systematically find the location poles and zeros of the compensation networks. The outputs of this block are: ωi, ωp12 and ωz12. III. The block of compensator converts the location of poles and zeros of compensator to component values of the error amplifier.

Vg L C R Vp r Power Stage Gp(s)

Aco

fco

Øco K-factor

PM

ωi ωp12 ωz12 Vo Vref R3

Compensator

C1 C2 C3 R1 R2

Figure 2 Flowchart for the proposed approach

1.4 PSPICE IMPLEMENTATION The PSpice simulator is provided with an extension called Analog Behavioral Modeling (ABM). With ABM the simulator can be used like a programming language and to solve general

8


mathematical problems by translating them to an electrical circuit. ABM in PSpice is able to evaluate expressions that are functions of circuit variables (voltages, currents, and simulation time) using the controlled current and voltage sources (G and E devices). ABM can also be used to solve system of linear and nonlinear algebraic equations as well as systems of complex, transcendent and ordinary, differential equations in their implicit or explicit form. In each case, the equations are converted into electrical circuits and solved by PSpice with a DC analysis for only algebraic equations or a transient analysis for systems of algebraic and differential equations. Editing the input file of PSpice is relatively more comfortable than programming in MATLAB, C or other program languages. 1.4.1 Power Stage Block The function of this block is to compute the magnitude and phase of the control-to-output transfer function, Gp(s). The controlto-output transfer function for the buck converter has one zero and one complex pole-pair. The equation of the transfer function was previously given in (1). With s = jω, we see that transfer function is a complex number containing a real part and an imaginary part. The magnitude of a complex number is the square root of the sum of the squares of the real and imaginary parts. The phase is the inverse tangent (arctan) of the ratio of the imaginary part to the real part. Therefore, the magnitude of the control-to-output transfer function can be calculated as

⎛ ω 1 + ⎜⎜ ⎝ ω zesr

⎞ ⎟⎟ ⎠

2

Gco vo = A= vc ⎛ ⎛ ω ⎞2 ⎞ ⎛ ω ⎞2 ⎜1 − ⎜ ⎟ ⎟ + ⎜ ⎟ ⎜ ⎜⎝ ω o ⎟⎠ ⎟ ⎜⎝ Qω o ⎟⎠ ⎝ ⎠

(12)

The phase of the control-to-output transfer function can be


9

calculated as

φ = tan −1

ω − tan −1 ω zesr

ω Qω o ⎛ω ⎞ 1 − ⎜⎜ ⎟⎟ ⎝ ωo ⎠

2

(13)

To implement (12) and (13) in PSpice, the frequency is assigned as a variable, and other parameters are assigned as constants. The .PARAM statement is used for this purpose. By using the .PARAM statement we can create parameters and assign algebraic mathematical expressions to it. 1.4.2 K-factor Block This block is used to implement K-factor approach in designing feedback compensator in PSpice. The inputs to this block are gain, Aco, and phase, Øco, of the control-to-output transfer function at the crossover frequency, fco (or ωco). By knowing Aco and Øco, and speciying the phase margin, PM, the phase boost required can be calculated as

φ boost = PM − 90 o − φ co

(14)

Then, K-factor is calculated as ⎞ ⎛φ K = tan 2 ⎜ boost + 45 o ⎟ ⎠ ⎝ 4

(14)

The two poles of the compensator are located at

ω p12 =

ω co K

The two zeros of the compensator are located at

(15)

10


ω z12 = K ω co

(16)

The integrator gain of the compensator is

ωi =

ω co Aco K

(17)

(14)-(17) are also implemented in PSpice by using the .PARAM statement. 1.4 .3 Compensator Block The function of this block is to convert the values of poles and zeros to component values of the error amplifier. The inputs to this block are ωp12, ωz12, and ωi that were obtained earlier from Kfactor block. Besides, the user must provide reference voltage, Vref, and Rbias.The conversions occur as follows:

C3 =

f z12 (ω i R3 f p12 )

⎛ f p12 ⎞ − 1⎟⎟ C 2 = C 3 ⎜⎜ ⎝ f z12 ⎠ 1 R2 = 2πf z12 C 2 R3 R1 = ⎛ f p12 ⎞ ⎜⎜ − 1⎟⎟ ⎝ f z12 ⎠ 1 C1 = 2πf p12 R1

Rbias =

Vref Vo − Vref

R3

(18) (19) (20) (21)

(22) (23)


11

(18)-(23) are also implemented in PSpice by using the .PARAM statement. To make the values of C3, C2, C1, R1, R2, and Rbias available in the schematic after the simulation finished, the relevant parameters are represented by dependent voltage sources. The three blocks above were implemented in a single subcircuit. The PSpice netlist of the subcircuit and its symbol are shown in Appedix 1. 1.4 APPLICATION EXAMPLES Two examples are included in this section to demonstrate the effectiveness of the proposed approach in designing feedback for dc-dc converters. The first example is a buck converter operated at the switching frequency of 100 kHz. The second example is a similar buck converter, but the switching frequency is doubled and the inductor is halved. 1.4.1 100 kHz Buck Converter The buck converter is designed to operate in continuous conduction mode. Following are the parameters of the converter: Vg = 10V to 15V, Vo = 5V, L = 30µH, R = 1.25Ω, fs = 100 kHz, Vp = 3V, Vref = 2.5V, Rbias = 10 kΩ. By knowing the converter parameters, the design of feedback compensator can be performed by using the developed subcircuit in PSpice. Before doing the design, two parameters should be chosen. The first is to choose the crossover frequency, fco. This parameter determines how quickly the system responds to transient. In practice, fco lies between fs/10 and fs/3. In our design we choose fs = fs/6, as a compromise. Another parameter to choose is the phase margin, PM, desired in the overall loop. Typical PMs range 45° to 75°. Lower PM, like 45°, give good transient response at the expense of peaking of the closed loop transfer function and output impedance. Higher PMs, like 75°, give flat closed-loop transfer function and minimum peaking of output impedance, but at the expense of speed and settling time. A good compromise is 60°.

12


Using the above parameters, the developed subcircuit was tested using the DC analysis in PSpice. The result is shown in Fig. 4. The time required to finish the simulation was just 0.13s, using PSpice Version 9.2.

R = 1.25

VG = 10V

VREF = 2.5V

C = 100uF RESR = 19m

24.42V

K

134.2V

PBOOST

L = 30uH

VP = 3V VO = 5V

C1

4.526nV

Type-3-all

C2

2.383nV

U14

C3

101.7pV

WI

R1

427.0V

21.19KV

WZ12

R2

19.81KV

517.5KV

WP12

RBIAS

10.00KV

106.5mV ACO -164.2V 40.25KV

PCO

R3 = 10K PM = 60

FCO = 16.6667KHZ

Figure 3 The result of DC analysis to give component values of the compensator.

To check the developed subcircuit working properly or not, the obtained component values of the compensator were used in the average model. Frequency response of loop-gain was simulated by PSpice AC analysis. Bode plot of loop-gain is shown in Fig. 5. From the bode plot, we can see that the crossover phase is –119.6°, indicating stable operation with PM of 60.4°. The crossover frequency is 16.623 kHz. The small differences between our target (PM = 60.0° and fco = 16.667kHz) and the results of PSpice are due to round-up error.


13

Figure 4 Bode plot of loop-gain (gain in dB and phase in degrees)

1.4.2 200 kHz Buck Converter The parameters of this converter are the same as the previous example, except the switching frequency is doubled (fs = 200kHz) and the inductor is halved (L = 15µH). It would be expected that the transient response of this converter is faster than the previous one. Without the developed subcircuit design procedure, any changes in the parameters made the whole system must be redesigned. With the developed subcircuit in hand, the process of redesign doesn’t make any problem; the simulator can do it for us and give the result as shown in Fig.6. The time taken to simulate the whole process of redesign was 0.13s. For comparison between the two examples for a transient response, the switch model simulation (cycle-by-cycle) for a load step was performed. The load steps were made to occur at 8.0 ms (from 4A to 1A) and 8.3 ms (from 1A to 4A). The result is shown in Fig. 7. As expected, the 200kHz buck converter has a faster transient response due to the higher fco and the smaller inductor value.

14


VG = 10V

R = 1.25

VO = 5V

C = 100uF VREF = 2.5V

L = 15uH

VP = 3V

RESR = 19m

17.40V

K

126.1V

PBOOST

C1

1.877nV

55.37mV

ACO

Type-3-all

C2

433.6pV

-156.1V

PCO

U14

C3

26.44pV

217.4KV

WI

R1

609.7V

50.21KV

WZ12

R2

45.94KV

873.7KV

WP12

RBIAS

10.00KV

R3 = 10K PM = 60

FCO = 33.333kHz

Figure 5 DC analysis to compute compensator’s parameters for 200 kHz buck converter.

5.2V 5.1V 5.0V 4.9V 4.8V 4.7V 7.9ms

8.0ms V(OUT

8.1ms

8.2ms

8.3ms

Time

Figure 6 Load steps response

1.5 CHAPTER SUMMARY

8.4ms

8.5ms


15

A new approach to using PSpice in designing feedback of dcdc converter system has been introduced. In this new approach, the feedback design procedures are programmed and made as a subcircuit in PSpice. The component values of the errror amplifier have been easily obtained by means of PSpice DC analysis. The extension of this approach to other converters and control schemes like peak current mode (PCM), Average current control (ACC) and power factor correction (PFC) is straightforward provided that there exist small-signal models and design procedures. REFERENCES [1] Lloyd H. Dixon, “Closing the feedback loop,” Unitrode Power Supply Design Seminar Handbook: SEM 700A, 1990.

[2]

W. Tang, F. C. Lee and R. B. Ridley, “Small-Signal Modeling of Average Current-Mode Control,” IEEE Trans. Power Electronics, Vol. 8, no. 2, Apr. 1993, pp. 112-119.

[3]

B. Holland, “Modeling, Analysis and Compensation of the Current-Mode Converter,” Proceeding of the Powercon 11, 1984, pp. I-2-1-I-2-6.

[4]

H. Dean Venable, “The k-factor: A New mathematical Tool for Stability, Analysis, and Synthesis,” Proceeding of Powercon 10, San Diego, CA, March 22-24, 1983.

[5]

Lloyd H. Dixon, “Average Current Mode Control of Switching Power Supplies,” Unitrode Application Note, 1999.

[6]

J. Sun, R. M. Bass, “Modeling and Practical design issues for Average Current Control,” Proc. of APEC, Vol. 2, pp. 980986,1999.

[7]

S.A. Chickamenahalli et. al., “Effect of target impedance and control loop design on VRM stability,” Proc. Of APEC, 2002, Vol. 1.

[8]

Abraham I. Pressman, Switching Power Supply Design,

16


McGrawHill, 1998. [9] N. Mohan, T. M. Undeland, W. P. Robins, Power Electronics: Converters, Applications and Design, John Wiley, 1995. [10] C. M. Liaw, T. H. Chen, W.L. Lin, “Dynamic modelling and control of a step up/down switching-mode rectifier,” IEE Proc. - Electric Power Applications, Vol. 146 Issue: 3, May 1999, pp. 317–324. APPENDIX 1 * source ERROR-AMP .SUBCKT Type-3-all Aco C1 C2 C3 k Pboost Pco R1 R2 + Rbias wi wp12 wz12 PARAMS: + Vg=12 Resr=20m R3=10k Vo=12V Vp=3V Vref=3V L=100uH fco=10kHz + PM=50 C=400uF R=5 .PARAM C2={C3*((wp12/wz12)-1)} w={2*pi*fco} R1={R3/(k-1)} C3= + {wz12/(wi*R3*wp12)} mag1={SQRT((1+(w*w)/(wzesr*wzesr)))} R2= + {1/(wz12*C2)} Pboost={PM-90-Pco} wi={w/(Aco*k)} wz12={w/sqrt(k)} + Rbias= {Vref*R3/(Vo-Vref)} + k={(Tan(((Pboost/4)+45)*pi/180))*(Tan(((Pboost/4)+45)*pi/180))} +phase={-atan((w/(Q*wo))/(1-(w*w)/(wo*wo)))*180/pi} +Mcomp={(1/mag)} Pco={Pcomp+phase1} + phase1={atan(w/wzesr)*180/pi} wo={1/SQRT(L*C)} + Aco= {Mcomp*mag1*Vg/Vp} + Pcomp={IF((1-((w*w)/(wo*wo))) 0 for S ( x) < 0,

(2)

20


where S(x) is a scalar function of the state x and u switches between two different inputs, umin and umax. If the switch could be switched on and off infinitely fast the state vector of the plant would stay on the sliding surface given by the equation S(x) = 0. This mode is called sliding mode and S(x) = 0 describes the desired motion of the plant. The conventional way to select the sliding surface is by using a linear combination of the state variables as: S ( x) = c1 x1 + c 2 x 2 = C T x = 0

(3)

where CT = [c1, c2] is the vector of sliding surface coefficients. Sometimes an integral term is added in (3) to eliminate the steady state error. (2) and (3) are chosen so that both existence and reaching conditions are satisfied. A detailed discussion of the sliding mode control principle can be found in [1]. The common method of implementing the sliding mode control is based on the control law described in (2) and (3). As the switching frequency is limited, the implementation of (2) is easily accomplished by refining it into: ⎧u max u=⎨ ⎩u min

for S ( x) > κ for S ( x) < − k

(4)

where κ is an arbitrarily small value. The introduction of a hysteresis band with the boundary conditions S(x) = κ and S(x) = κ provides a form of control to the switching frequency of the converter. This also resolves the practical problem of a very high frequency switching operation. 2.2.2

Simulation in PSpice

The sliding mode control system is shown in Figure 1. Inside each block is given the related equations. The control law equation described in (4) is a hysteresis comparator. In practice, this comparator is commonly realized by using comparator IC such as LM 311 with two different resistors connected in positive feedback


21

configuration. Unfortunately, this simple configuration often causes numerical instability in PSpice. First is due to fast switching transition between the high and low states caused by high gain of the comparator and the second is due to the positive feedback configuration.

umax

u

y

Eq. (1)

umin

x Eq. (4)

Eq. (3)

Figure 1 Sliding mode control system under study

The hysteresis comparator, based on our experience, always becomes a bottle neck in simulation of power electronics converters with sliding mode control in PSpice. Therefore, careful implementation of this part is extremely important. There are several ways to realize the hysteresis comparator in PSpice. This paper proposes a reliable hysteresis comparator model that can simulate in a wide range of frequency with little or no convergence problem. The high switching frequency, up to megahertz range, is usually required to simulate a near ideal sliding mode principle. As such, the theoretical aspect of the sliding mode control can be carefully examined, without a second order effect. In this paper, the realization of the hysteresis comparator model in PSpice is based on behavior model. It is realized through ABM parts. Some guidelines to avoid convergence problem will also be given. The detailed development of the model will be discussed in the next

22


section. The control law equation described in (3) computes the instantaneous state-variable trajectory S(x). In practice, this is realized through an analog or digital computer. In Pspice, this is easily realized through an ABM part. The realization of (3) through the ABM parts in PSpice rarely gives numerical instability due to the continuity of the state variables. The plant equation described by (1) is in general. For power electronic circuits, the plant usually consists of a voltage source, a resistor, an inductor, a capacitor, fully-controlled switches such as MOSFET and diodes. There are several ways to implement the plant in PSpice. The easy way is to implement it as it is. However, this tends to raise convergence problem especially for power electronics circuits that consist of more than one fully-controlled switch, such as inverter circuits. In addition, it also requires a big size of memory space to store the data and takes a long time to run the simulation. In this paper, due to its simplicity, the buck converter circuit will be implemented as it is. But, for the inverter circuit, a system level simulation will be employed. This means that neither fully-controlled switch nor diode is directly used in the circuit. Therefore, the convergence problems related to the use of fully controlled switch and diode are eliminated. 2.3

COMPARATOR

2.3.1 Comparator and Hysteresis Comparator Figure 2 shows a basic comparator. A comparator works by comparing the voltages at its two terminal inputs. When the voltage at the positive terminal, v+, is greater than the voltage at the negative terminal, v-, the output voltage is high and when it is lower the output is low. This is due to large open-loop gain A in the comparator. The mathematical equation that describes this property is given by: ⎧+ V v o = A(v + − v − ) = ⎨ ⎩− V

v+ > v− v+ < v−

(5)


23

vo +

+ o

v+- v-

-

-V

Figure 2 A basic comparator and its characteristics

Figure 3 shows a comparator with hysteresis. Unlike the basic comparator, the voltage v+ of the hysteresis comparator is not independent. As we can see from the Figure 2, the voltage v+ depends on vo, R1 and R2. In particular, the positive terminal voltage is v+ =

R1 vo R1 + R 2

(6)

R2 R1

+ o 0

vi

-

vo +V v+ - v-V HB

Figure 3 A hysteresis comparator and its characteristics

Since the output voltage vo can assume any two values, so does

24


v+. When the output voltage vo = +V, the positive terminal voltage is v+ =

R1 V ≡ VUB R1 + R 2

(7)

When the output voltage vo = -V, the positive terminal voltage is v+ = −

R1 V ≡ V LB R1 + R 2

(8)

(3) and (4) define the upper boundary (UB) and lower boundary (LB) of the hysteresis band (HB). The hysteresis band, HB is given by VUB − V LB =

R1 2V ≡ HB R1 + R 2

(9)

If we define R1/(R1+R2) = K and let V =10 Volt, we can find that K = (1/20)HB = 0.05HB. Hence, the terminal positive of comparator, v+, for both (7) and (8) as a function of HB can be written as v + = 0.05 × HB × v o (10) 2.3.2 PSpice Implementation There are several ways to implement the comparator in PSpice. In this paper, we implement the comparator which is described in (1) by using If-Then-Else function. ABM2

+ -

IF(V(%IN1)>V(%IN2), 10, -10)

Figure 4 A basic comparator model in PSpice


25

By using ABM2 part which has two inputs and one output, we can write the expression for the comparator as shown in Figure 4. As usual, we use the value of V = 10 Volt. To implement the hysteresis comparator, the only difference is that the terminal positive of the comparator is not independent; it depends on the output voltage as in (10). However, this can be easily added in PSpice by using ABM1 part which has a single input and a single output as shown in Figure 5. ABM2

ABM1 0.05*HB*V(%IN)

+

-

IF(V (%IN1)>V(%IN2), 10, -10)

PA RAM ET E RS:

HB = 1

Figure 5 A hysteresis comparator model in PSpice

Notice that ABM1 part takes the output of ABM2 as its input, does the computation and outputs the value to the positive terminal of ABM2. Parameter HB is used in ABM2 and it is defined by PARAM part. HB is the only parameter needs to be changed to suit various applications. 2.3.3 Simulation The above described behavioral model of the hysteresis comparator has been simulated using PSpice to demonstrate its validity. A sine wave signal with frequency of 500 kHz and amplitude of 10 V is applied to the inverting input of the hysteresis comparator. The hysteresis band HB is set as a default value i.e. 1. The simulation parameters (.option) are set as their default values too.

26


(a)

(b) Figure 6 Simulation results of the hysteresis comparator (a) Using default maximum step size (b) Using maximum step size at 0.001 µs.

The simulation results for the input and the output are shown in Figure 6a. From the results we can see that the rise and the fall of the output waveform are less sharp. It means that the accuracy of the simulation result is quite poor when the default values of simulation parameter (.option) are used. To make the accuracy of the output waveform to be acceptable, we have to set just one simulation parameter (.option) i.e. the maximum step size. From our experience, the maximum step size should be set at least 1/100 of the period of any fastest source in a circuit. The result for the output waveform when the maximum step size is set at 0.001 µs is shown in Figure 6b. In order to use the model properly, the trade-off between accuracy and simulation times is always to be made.


2.4

27

SIMULATION EXAMPLES

2.4.1 Buck Converter In the following, the simulation of a buck converter is described to illustrate the modeling approach described previously. Figure 7(a) shows the buck converter with the sliding mode control. With the chosen values for the components, the converter is operating in the continuous conduction mode. This circuit uses only standard elements from the library of the student version. The block called SMC accomplishes the task of sliding mode controller. The inputs to this block are the output voltage (terminal a) and capacitor current that was translated into voltage by the element H (terminal b). The only output is the rectangular voltage (terminal c). This output is fed to the MOSFET gate driver to turn on and off the mosfet. The MOSFET gate driver is implemented by the element E1.

0.15

IRF150

L1

out

110u F

RL

IC = 0

V1

C1 +

D4 Dbreak

+ -

-

+ -

24V

V

E1

Ic

H1

GAIN = 1

GAIN = 12

c

100uF

IC = 0

H + -

0

a

b SMC

(a)

Rload 6

28


ABM2a

a

b

1 3 2

(1/(Beta*RL))*(Vref- Beta*V(%IN2)) -V(%IN1)

ABM1

ABM2b

0.05*HB*V(%IN)

+ -

c IF(V(%IN1)>V(%IN2), 10, -10)

Hysteresis Comparator PARAM ET ERS:

PARAM ET ERS:

HB = 0.3

Beta = 0.275 Vref = 3.3 RL = 6

(b) Figure 7 (a) Buck converter with sliding mode controller (b) Sliding mode control.

Figure 7(b) shows the circuit that implements the sliding mode controller (SMC). ABM2a part implements a standard sliding mode control law for buck converter which is given by S (v o , i c ) =

1 (V ref − βv o ) − i c [3]-[4]. βR L

(11)

All parameters used in the schematic are defined by using PARAM parts. Theoretically, with the control law in (11), neither the output voltage nor the inductor current experiences overshoot. In the schematic, the hysteresis band HB used for the hysteresis comparator is 0.3, resulting in the switching frequency around 200 kHz. This parameter can be adjusted to produce the desired switching frequency. Figure 8 shows the simulation results for the buck converter using the sliding mode control law as described in (11). It can be seen


29

that no overshoot occurs during start-up event for both the inductor current and the output voltage, verifying the theory.

Figure 8 Simulation results for start-up event

Figure 9 shows the simulation results for the converter when the load disturbances occur at 5 ms and 7 ms. At 5 ms the equivalent load resistance was step-downed from 6 Ω to 3 Ω, while at 7 ms the reverse. Obviously, the output voltage response follows the first order system during the sliding mode, agreeing with the theory. Figure 10 shows a phase plane plot of ic versus (Vref -βvo). A point in phase plane, which is called a representative point, completely defines the state of the system at one instant in time. The steady state operating point is the origin, where the error is zero. The control equation (11) represents a straight line through the origin with slope -1/βRL. This line is known as a sliding line.

30


Figure 9 Simulation results for load disturbances

We can see that the representative point moves towards the sliding line during start-up, slide on it to the origin, then stay at the origin during steady-state. We can also see that when a step change in load occurs, the representative point will leave the sliding line (mode). The representative point will follow two families of trajectories in the phase plane, depending on whether the control system imposes u = umin (corresponding to duty cycle, d = 0) or u = umax (corresponding to duty cycle, d = 1). This condition will last till the representative point reaches the sliding mode region again. This explains the use of wide sliding mode region in the design. The phase plane plot is a very important tool to study and design sliding mode control, especially for second order systems.


31

Figure 10 A phase plane plot of the buck converter

2.4.2 Single Phase Inverter Figure 11 shows a conceptual single phase inverter system with bipolar switching. The operation of the inverter is represented by two voltage sources and a single pole double throw (SPDT) switch. By operating the SPDT switch back and forth between the position 1 and 2, this conceptual inverter will ideally produce a bipolar output voltage which is similar to a physical inverter. The LC low pass filter at the output is used to reduce the output harmonics. We choose to model this conceptual inverter in PSpice, instead of a physical inverter, for system level simulation. Without semiconductor switch, the model is so simple. Such a model completely eliminates any convergence problems related to the use of semiconductor switches.

32


Rl

L

C Rload

1 E

2 + -

-

Resr

E

+

0

Figure 11 A conceptual single phase inverter

Figure 12 shows the single phase inverter with the sliding mode control model in PSpice. As with the buck converter, this circuit also uses standard elements from the library of the student version. The block called SMC accomplishes the task of sliding mode controller. The inputs to this block are the output voltage (terminal a) and capacitor current that was translated into voltage by the element H (terminal b). The only output is the bipolar voltage (terminal c). This output is multiplied by DC link voltage, VDC, to produce the output voltage of the inverter before filtering. Figure 13 shows the circuit that implements the sliding mode controller (SMC). ABM2a part implements a common sliding mode control law for the inverter, which is given by S (v& c , v c ) = k (v& c _ ref − v& c ) + (Vc _ ref − v c ) [5].

(12)

The only design parameter in the (12) is k. By choosing a suitable value for k, the inverter with sliding mode control can be realized. As usual the hysteresis band HB is used to limit the switching frequency. For the simulation purpose, we choose k = 0.001 and HB = 50. With these parameters the switching frequency around 3 kHz can be achieved. In practice, it is not easy to


33

determine the value of k for this system due to the fact that the load step changes in this system results in unbounded disturbance. In [5] k is determined solely by simulation study and experimental investigation.

0.15

L1

Vc

6m

IC = 0 C1

360*V(%IN+, %IN-)

100uF

E1 IN+ IN-

OUT+ OUT-

RL 20

IC = 0 GAIN = 10k

EVALUE

Ic

c

b

+ -

0 H1

10m H

a

SMC

Figure 12 A single phase inverter with SMC

Figure 14 shows a phase plane plot of derivative of error versus error as in (12). The control equation (12) represents a straight line through the origin with slope -1/k i.e. the sliding line. We can see that the representative point always stays on the sliding line under steady-state condition. When a step change in load occurs, the representative point will leave the sliding line. The representative point will follow two families of trajectories in the phase plane as with the buck converter system case, depending on whether the control system imposes u = umin or u = umax. This condition will last till the representative point reaches the sliding mode region again.

34


ABM1

ABM2b

0.05*HB*V(%IN)

+

-

c IF(V(%IN1)>V(%IN2), 10, -10)

PARAM ET ERS:

HB = 50 PARAM ET ERS:

ABM2a

k = 1m

k*(V(Vc_dot_ref)-V(%IN1))

b

a

1

3

+(V(Vc_ref)-V(%IN2)) Vc_dot_ref VAMPL = 0.891 FREQ = 50 PHASE = +90

2

Vc_ref

V1

V2 VAMPL = 280 FREQ = 50

0

Figure 13 A schematic of SMC for the inverter

If the representative point is not on the switching line, its motion is governed by a simple second order system. However, for this inverter system the representative point always reaches the sliding line and the representative point remains on it if it hits the sliding line within the sliding mode region. This explains why the sliding mode region should be as wide as possible. Figure 15 shows a phase plane plot of the inverter system when k = 0.05m was used. The system was subjected to the same load disturbance as the previous example. The simulation result shows a poor performance of the sliding mode control system. This happens due to the fact that by reducing the value of k will result in a smaller size of the sliding mode region, giving rise to several second order motions in the phase plane. This shows that by only adjusting the controller gain k, it is possible to adjust the size of sliding mode region to obtain the desired performance.


35

Figure 14 A phase plane plot for the inverter system with k = 1m

Figure 15 A phase plane plot for the inverter system with k =

0.05m

2.5 CHAPTER SUMMARY Simulation of power electronics circuit with sliding mode control has been presented. Two common sliding mode control systems, i.e. a buck converter and a single phase inverter, have been given as examples. The methodology to model the sliding mode control systems in PSpice has been described. The development of the hysteresis comparator model, i.e. the key

36


element in the sliding mode control system, has been described in detail. The simulation results obtained with the models agree with the theory. The models are thus well suited to the analysis and design of power electronic circuits with sliding mode control. REFERENCES [1] V. Utkin, J. Guldner, and J. X. Shi, A Sliding Mode Control in Electromechanical systems. London, U. K.: Taylor & Francis, 1999. [2] H. Sira-Ramirez, “A geometric approach to pulse-width modulated control in non-linear dynamical systems,” IEEE Trans. Autom. Control, vol. 43, no. 2, pp. 234–237, Feb. 1998. [3] P. Mattavelli, L. Rosetto, G. Spiazi, and P. Tenti, “General purpose sliding mode controller for DC/DC converter applications,” in Proc. IEEE PESC rec., Jun 1993, pp. 609– 615. [4] S. C. Tan, Y. M. Lai, M. K. H. Cheung, and C. K. Tse, “On the practical design of a sliding mode voltage controlled buck converter,” IEEE Trans. Power Electron., vol. 20, no. 2, pp. 425–437, Mar. 2005. [5] M. Carpita, and M. Marchesoni, “Experimental study of a power conditioning system using sliding mode control,” in Proc. IEEE Trans. Power Electron., vol. 11, no. 5, pp. 731742, Sept. 1996. [6] M. Ahmed, M. Kuisme, K. Tolsa, and P. Silventoinen, “Implementing sliding mode control for buck converter,” in Proc. IEEE PESC Rec., Jun 2003, vol. 2, no. 2, pp. 634–637.


37

3 DYNAMIC EVOLUTION CONTROL FOR STEP DOWN DC-DC CONVERTER Ahmad Saudi Samosir Abdul Halim Mohd Yatim

3.1 INTRODUCTION In recent years, the application of power electronics converter has grown extremely. Some applications that are increasingly being dominated by power electronics are: 1) switched-mode power supplies; 2) adjustable speed motor drives; 3) efficient control of heating and lighting; 4) efficient interface for photovoltaic; 5) fuel cell and high voltage dc system for efficient transmission of power, etc. Much power electronic application operated with parameter variation, non linearity, load disturbance, etc. Therefore, there is an increasing need for a good controller design to perform tight regulation under high unpredictable load variation. In designing of classical control theory, e.g. PID controller, small signal linear approximations have been applied to the nonlinear system. This approach enables the designer to use a simple linear controller to keep the system stable. But the main disadvantage using this type of control is that it is applicable for operation only near a specified operating point. Since power converters are non-linear time-varying systems, the design of controllers must have capability to cover up the nonlinearity and time-varying properties of the system.

38


In this paper, a new approach for converter controllers synthesis based on Dynamic Evolution Control theory is presented. The Dynamic Evolution Control exploits the non-linearity and time-varying properties of the system to make superior controller. The Dynamic Evolution Control tries to overcome the mentioned problem of linear control by explicitly using dynamic equation model of the converter for control synthesis. The Dynamic Evolution Control has several advantages, i.e. wide range stability, zero steady state error, simple synthesis process and suitable for digital control implementation, because it requires a quite low bandwidth for the controller, because it requires simple calculations, which can be realized digitally easily. Moreover, The Dynamic Evolution Control is operated at constant switching frequency, so that it causes less power filtering problems in power electronics applications. 3.2 DYNAMIC EVOLUTION CONTROL THEORY

The objective of the Dynamic Evolution controller is to control the dynamic characteristic of the system to operate on the target equation, Y = 0. In Dynamic Evolution controller, the dynamic characteristic of converter system is forced to make evolution by following an evolution guideline. The selected evolution guideline is an exponential function as shown in Fig. 1. The equation of this exponential function can be written as:

Y = Ce − mt

(1)

Where C is the initial value of Y, and m is proportional to the initial decrease rate of Y. In this exponential function, the value of Y is decrease


39

exponentially to zero as a function of time. The decrease speed of Y is proportional to the decrease rate m. Let Y represent the state error function of the converter. Then, the state error function(Y) is forced to follow the evolution guideline as show in fig.1, so the dynamic evolution of the state error function (Y), with initial value Yo, will fixed according to the equation (2).

Y = Yo.e− mt

(2)

It means that the state error function (Y) is driven decrease to zero exponentially with decrease rate m.

Fig. 1. Dynamic Evolution Guideline

Since, Y is the state error function of converter as describe in equation (2), therefore, the derivative of Y is given as:

dY = − m.Yo.e − mt dt

40


dY = − m.Y dt As a result, the Dynamic Evolution Function can be written as equation (3). dY + m.Y = 0; dt

m>0

(3)

Where, m is a design parameter specifying the rate of evolution. In order to synthesize the control law, the dynamic equation of the converter system is analyzed and substituted into the Dynamic Evolution Function (3) to generate the control law of controller, which ensure the state error function (Y) of converter decrease to zero follow the evolution guideline. The obtained results work on the full non-linear system. Hence, the designer does not need to make any simplification in the modeling process to obtain a linear model as in classical control theory. 3.3

SYNTHESIS OF SEP DOWN DC-DC CONVERTER CONTROLLER

The Buck or step-down converter is one of the most common topologies. It is used extensively in high efficiency power supplies. The Buck Converter scheme is shown as Fig. 2. As already mentioned, to synthesize the control law of the Dynamic Evolution Controller, the dynamic equation of the converter system must be analyzed and substituted into the Dynamic Evolution Function (3). In this time, we use the average model of Buck Converter. The


41

dynamic equation is obtained as follows:

Vg .α = L

diL + Vo; dt

0