50GHz Double-Balanced Up-Conversion Mixer Using CMOS 90nm Process Ivan Chee Hong Lai, Yuki Kambayashi, Minoru Fujishima School of Frontier Sciences, Department of Frontier Informatics The University of Tokyo Kashiwa, Japan
[email protected] Abstract—This paper reports the first millimeter-wave doublebalanced up-conversion mixer that is realized using a standard CMOS 90nm process. The circuit integrates passive on-chip baluns for single-ended to differential–ended conversions at the high frequency LO and RF ports and an active balun at the IF port. The passive baluns use a stacked configuration and also provide impedance matching to improve conversion gain. The active balun employs the quasi-symmetric properties of the drain and the source of the MOSFET to provide a balanced output. The mixer has a measured 11dB conversion loss and a LO rejection of 26.5dB. The power consumption is 13.2mW.
I.
INTRODUCTION
CMOS circuits operating at high gigahertz frequency have been reported frequently in recent years [1]. The developments are driven by the availability of the 60 GHz license-free band as well as applications in the highgigahertz bands below 50 GHz such as the automotive radar system operating at 22-29 GHz. High frequency upconversion mixing is important for realizing the transmitter front-end in these applications. To date, the state-of-the-art microwave up-conversion mixers are not realized on CMOS [2], [3] due to the low available conversion gain and the lossy silicon substrate at millimeter-wave frequency. Furthermore, characterization of the devices to generate models for circuit design has been challenging. CMOS is desired for implementing low-cost, highly integrated single chip transceiver solutions. Attempts to build high frequency mixer circuits have been attempted but limited to simple topologies [4], [5]. For the upconversion mixer, simple topology cannot reject the LO and advanced processes are limited by the low supply voltage. Thus, no double-balanced Gilbert topology has been reported on 90nm process technology so far to the authors’ knowledge.
frequency fT of the 90nm process technology up to 150 GHz, conversion gain can be obtained and it can be compromised with high frequency amplification that has been proven difficult with previous processes.
A. Mixer Topology The Gilbert double-balanced topology is used. The local oscillator (LO) signal at the output can be reduced. However, to realize good LO rejection at high frequency is difficult because of the high-speed switching of the MOSFET results in a non-ideal alternating on-off of the differential pairs. Figure 1 shows the schematics of the mixer circuit.
Vdd
Vdd Balun 1
M3
LO
M4
W=40μm
M5
Output RF
M6
W=40μm
Balun 2
Vg1 (biasing)
Vdd L1
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C1
L2
M1 W=60μm
Input IF
However, the additional advantage of using CMOS at present is also to take advantage of the improved process technology which has the potential to integrate high density digital circuits for control functions. With the unity
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CIRCUIT DESIGN
II.
M2 W=60μm
W=40μm
M7 L3
Gnd
C2
L4
Double-balanced Gilbert Cell Mixer
Vg1 (biasing)
Fig. 1. Circuit diagram of the up-conversion mixer circuit.
At the high frequency LO and RF ports, passive baluns can be employed due to the shorter corresponding wavelengths for reduced on-chip sizes. However, at the relatively lower frequency IF port, an active balun is used instead. The choice of the baluns in the topology has to take into considerations of the low Vdd requirements of the process technology. M1, M2 is biased for maximum transconductance and M3-M6 requires voltage headroom for switching. Any additional active components should not demand further voltage headroom. In the topology employed, a compromise is made for increased chip area by the inductors L1-L4 and capacitors C1 and C2. These components, however, serve the important function of impedance matching to the Gilbert mixer circuit. B. Passive Balun Structure Passive baluns do not consume any power and topologies such as the Marchand-type balun provide broadband response with low losses at the pass-band. The Marchand balun provides single-ended signal to differential signal conversion by using coupling across a half-wavelength line. Signal is input into the half-wavelength line at port 1 as shown in Fig. 3 and output is taken from the ends of two quarter-wavelength lines at ports 2 and 3. -90º Differential Port 2
Singleended Port +90° δ metal6
-90° Differential Ports
Substrate shield (metal1)
Fig. 3. Layout of the on-chip balun at the LO and the RF ports..
The loss in the structure can further be reduced with substrate shielding. The substrate shield is realized with slotted shield structures are placed underneath the balun. This shield reduces the speed of the propagating wave and results in a shorter physical length that corresponds to the required wavelengths [7]. The shield also prevents the electric field from penetrating the conductive silicon substrate. C. Active IF Balun The active balun of Fig. 4 is employed to realize the single-to-differential conversion of the input IF signal to the mixer. This topology utilizes the anti-symmetry of the MOSFET current at the drain and the source node.
coupling
Single-ended Port 1
Top pad metal
coupling Differential Port 3 +90 º
Vg1 (biasing)
Vdd
Fig. 2. Marchand balun operating principles.
Stacked on-chip passive Marchand baluns [6] are used to convert the single-to-differential input for the LO signal and to convert the differential-to-single output for the RF signal. Figure 3 illustrates the structure of the baluns. The shape of the balun is constructed in the form of a square to minimize required chip area and to allow the differential ports to be located closely. It is necessary to locate the ports closely since they connect to the switching transistors that need to be well matched. Any extra length on the layout for the interconnections between the balun and the transistors will affect the transfer characteristics. However, due to physical layout constraints, the differential ports cannot fully couple to half the length of the half-wavelength line and leaves a gap with a distance of δ. This distance δ between the terminals of the differential ports must be spaced closely to achieve good anti-phase.
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Phase 180º Input IF
W=40μm
matching
Phase 0º
Gnd
Vg1 (biasing)
Fig. 4. Schematics of the input IF balun.
This topology is commonly employed at low frequency for its simplicity and performance. At high frequency, the non-symmetry of the MOSFET gate-drain capacitance and the gate-source capacitance causes the phase balance to degrade. At the operating frequency of 10 GHz, the simulated amplitude imbalance achieves a low value of 1.1dB and the phase imbalance reaches 19.3 degrees. The output signals of the balun are directly used for driving the double-balanced mixer where the results are shown in the next section. III.
LO
IF
EXPERIMENTAL RESULTS
The up-conversion mixer was designed and fabricated using a six-metal 90nm CMOS process. The additional pad metal layer available is utilized as one of coupled lines of the passive baluns. Measurements had been performed on a separate 22.4 GHz to 37.3 GHz balun test structure, occupying an area of 229μm×229μm. Figure 5 shows the measurement results of the balun test structure.
S21
-10
S31
200 180
-20
160 Amp. imbalance 0±1dB: 22.4 GHz~44.4 GHz
140
Figure 7 shows the S-parameter measurements of the circuit. The single-ended output of the balun at the RF port has an optimum match at 46.5 GHz and extends from 40 to 51 GHz for a return loss better than 5dB.
-30
|S21|, |S31| (dB)
0
120 100
RF, LO return loss (dB)
phase difference (deg)
0
220
Fig. 6. Chip micrograph of the up-conversion mixer.
Due to instrument restrictions, measurements are made with an input IF of 11 GHz and an LO of 40 GHz from signal generators. The RF signal cannot be measured below 50 GHz because of the non-availability of an appropriate harmonic mixer.
Phase diff. 180˚±10˚: 11.6 GHz~37.3 GHz 240
RF
-40 0
10
20
30
40
50
60
70
Frequency (GHz)
Fig. 5. Amplitude response and phase imbalance of a 22.4 GHz to 37.3 GHz stacked on-chip Marchand balun.
Using stacked on-chip Marchand balun designs for the 50 GHz mixer, on-wafer measurements can be performed because the fabricated circuit allows a GSG single-ended IF input, a GSG single-ended RF output and the LO supplied through another GSG single-ended input. Figure 6 shows the micrograph of the mixer. The occupied areas of the baluns are 105μm×105μm and 92μm×105μm for the LO feed and the RF output, respectively. The chip size is 600μm× 1050μm.
-2
-4
LO
-6
0
10
20
30
RF 40
50
60
Frequency (GHz) Fig. 7. Return losses of the LO and RF ports where the passive baluns are located
Figure 8 shows the measured power characteristics of the mixer. The circuit has a conversion loss of 11dB at the linear region and the linearity is indicated by the 1-dB compression point at 1 dBm input referred. The high conversion loss can be partly attributed to the loss of the active balun.
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output RF Power (dBm)
-10
RF=51GHz, IF=11GHz LO power=0dBm
600μm×1050μm. At 51 GHz, the measured mixer achieves a conversion loss of 11 dB with a maximum power dissipation of 13.5mW from a 1.2V dc power supply using a LO power of 0 dBm. Input referred 1-dB compression point is 1 dBm. The LO and RF return loss are better than 5 dB for frequencies from 40-51 GHz.
IP1dB= 1.0dBm
-20
ACKNOWLEDGMENT This study is supported by the strategic information and communications R&D promotion programme (SCOPE) of the ministry of internal affairs and communications of Japan. The chip fabrication was facilitated by the chip fabrication program of the VLSI Design and Education Center (VDEC), University of Tokyo, in collaboration with STARC, Fujitsu, Ltd., Matsushita Electric Industrial Company, Ltd., NEC Electronics Corporation, Renesas Technology Corporation, and Toshiba Corporation.
Conversion loss = 11dB
-30 -20
-15 -10 -5 0 Input IF Power (dBm)
5
Fig. 8. Measured power compression curve of the mixer.
Measurements are taken at a RF of 51 GHz and an IF of 11 GHz with an LO input power of 0dBm. The LO leakage at the output port is -26.5dBm and the power consumption is 13.2mW
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[2]
IV.
CONCLUSION
This work reports the first millimeter-wave doublebalanced mixer up to 50GHz using CMOS 90nm technology. On-chip stacked Marchand baluns are used to enable a single-ended LO input and a single-ended RF output. The stacked Marchand baluns are constructed with the top pad metal and the next highest metal layer for increased coupling and they provide impedance matching to improve conversion gain. Slotted substrate shields are laid under the balun structures to reduce substrate losses and provide reduced physical lengths. The occupied areas of the baluns are 105μm×105μm and 92μm×105μm for the LO feed and the RF output, respectively. The active balun employs the quasisymmetric properties of the drain and the source of the MOSFET to allow a single-ended IF input for the doublebalanced mixer. The fabricated chip has a total size of
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[7]
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