60-GHz Direct-Conversion Transceiver on 130-nm CMOS with Integrated Digital Control Interface B.N. Wicks, C.M. Ta, F. Zhang, P. Nadagouda, B. Yang, Z. Liu, Y. Mo, K. Wang, T. Walsh, G. Felic, R. J. Evans, I. Mareels, E. Skafidas NICTA, Department of Electrical and Electronic Engineering, The University of Melbourne, Victoria 3010, Australia
[email protected] Abstract— This paper describes the system architecture and design procedure for an integrated 60-GHz direct-conversion transceiver with integrated digital control interface on a 130-nm CMOS process. This transceiver incorporates both a transmitter and receiver. The transmitter achieves a Psat of 6.5 dBm, an OP1dB of 1.6 dBm. The receiver achieves a conversion gain of 8.1 dB with an IIP3 of -13.74 dBm.
I. INTRODUCTION The 60-GHz channel with an allocation of 7 GHz of unlicensed spectrum is seen as a suitable channel for gigabit per second high-density, short range wireless links. To achieve low cost and high levels of integration CMOS process technology is utilized. Undesirably the CMOS process when compared to more expensive processes such as Silicon Germanium (SiGe) and Gallium Arsenide (GaAs) has greater process variation, lower carrier mobility and smaller device breakdown voltage. This makes the design of millimeter-wave integrated circuits (MMICs) more difficult especially the design of high transmit power amplifiers (PAs), low noise amplifier (LNA) and low phase noise voltage controlled oscillators (VCOs) [1 – 6]. Advances in the CMOS process are allowing significant portions of a transceiver utilizing this channel to be incorporated into a single substrate or package achieving low cost but individual components into a single transceiver still remains a significant challenge due to the constraints placed by the integration. This paper presents an integrated 130-nm CMOS 60-GHz transceiver based on direct-conversion architecture, shown in Fig. 1. The architecture and the design process for the transmitter, receiver, and DCI respectively. II. TRANSMITTER A. Architecture The transmitter presented in this paper is implemented as a direct conversion architecture and is shown in Fig. 2. The transmitter accepts a pair of baseband differential signal inputs, an inphase (I) and quadrature (Q), which are denoted by tx_bb_i_p, tx_bb_i_n, and tx_bb_q_p, tx_bb_q_n, respectively. These signals are amplified and filtered by variable gain amplifiers (VGA) which are tunable to ensure sufficient output power. The output of the VGA is upconverted by double balanced mixers (MXRs). The mixers in this transmitter are based on double balanced Gilbert-cell structure. This structure is inherently immune to LO-to-RF
Fig. 1 Micrograph of the transceiver
feed through and has higher gain than the dual gate mixer [7]. The high LO-to-RF isolation maintains low DC offset signals. The differential up-converted RF signals are converted to single ended signals by differential-to-single ended converters (D2S) and these I and Q channels are combined by a power combiner (CBN). A five-stage cascaded power amplifier (PA) amplifiers the combined signal before a 2nd-order microstrip rectangular open-loop band-pass filter (BPF) filters before passing the signal to an interconnect to allow an off-chip antenna. A micrograph of the transmitter is shown in Fig. 3 and is covered in greater detail in [7]. B. Experimental Results The transmitter consumes a total DC power of 515mW. The capability of the transmitter is presented in Fig. 4. Fig. 4 (a) shows the saturated output power of 4 transmitters at different frequencies in the 56–64-GHz band. The output power is at its maximum at 6.5 dBm for frequency from 58 to 60 GHz. At the high end of the spectrum, the output power is reduced to about 2 dBm. The output 1-dB compression power was also measured and the collected data is plotted in Fig. 4 (b). At 60 GHz the output P1dB 1.6 dBm.
Fig. 2 Architecture of the 60-GHz direct-conversion transceiver
The controllability of the baseband variable gain amplifiers were characterized by measuring the output RF power at different gain control voltage of the VGAs. As shown in Fig. 4 (c), by changing the control voltage of the VGA from 150 mV to 550 mV, the gain of the VGA can be varied by 45 dB.
which allows dynamical control of the biasing voltages of the receiver from the digital section of the chip.
B. Experimental Results The performance of the receiver including its conversion gain and linearity was measured by on-wafer probing. Noise III. RECEIVER figure measurement was not carried out due to the lack of appropriate noise sources. The receiver consumes a total A. Architecture power of 54 mW. The conversion gain of the receiver was The receiver architecture is based on direct-conversion derived from the measurement of the input power and the architecture and is shown in Fig. 2 with a micrograph in Fig. 6. output power of the receiver. Losses due to cables at RF and The direct-conversion architecture was chosen owing its IF ports were measured and de-embedded at each RF and IF simplicity which permits high level of integration and low frequencies. The conversion gains from the input of the BPF power consumption [8]. The well-known LO leakage problem to the differential output of the I channel mixer (or Q-channel in direct-conversion receivers was solved by employing a mixer) are presented in Fig. 7 (a) and (b) as functions of the double-balancedup-conversion mixer that has an LO-to-RF LO frequency and IF frequency, respectively. A maximum isolation of more than 36 dB at the carrier frequency [10]. The conversion gain of 8.1 dB is achieved with fLO = 58 GHz and signal flow in the receiver is the reverse of that in the fIF = 200 MHz. In Fig. 7 (a), the conversion gain of the transmitter whilst the LO path of the receiver is similar to that receiver is reduced at high LO frequencies because of the of the transmitter. For each of the I and Q channels, a receive degraded performance of all building blocks of the receiver at signal strength indicator (RSSI) is added to sense the power at high frequency. In Fig. 7 (b), the drop in conversion gain at the output of each mixer. The RSSI generates an output high IF frequencies is due to the limited bandwidth of the IF voltage in proportional with the input signal power which can outputs. There is a 5-dB dip from 300 MHz to 400 MHz in the be used later in an automatic gain control (AGC) mechanism. IF response due to component matching. Similarly to the transmitter the receiver adopts an on-chip DCI The linearity of the receiver, quantified by its input inter-
Fig. 3 Micrograph of the transmitter
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(b)
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Fig. 4(a) Psat of 4 transmitters (b) Output-referred 1-dB compression point and 3rd-order intercept point (c) VGA tune ability.
modulation product (IIP3), was measured from a two-tone test. Two signal generators were used to generate the two testing tones for the measurement. Due to the lack of equipment, the LO power cannot be set up properly for optimum performance of the receiver. Thus the conversion gain of the receiver was reduced substantially. It is assumed that the output power of the fundamental tone and the third-order intermodulation (IM) tone were degraded by the same factor so that the IIP3 computed for the non-optimum operation closely tracks the IIP3 of the receiver in its optimum operation conditions. The measured IIP3 data is plotted in Fig. 8 (a). The IIP3 of the receiver is approximately -13.74 dBm. IV. DIGITAL CONTROL INTERFACE The transceiver adopts an on-chip digital control interface (DCI) which allows dynamical control of the biasing voltages and modes of operation of the analog and RF front-end from the digital section of the chip. Any variation in process parameters during fabrication or variation in power supply and temperature during operation can lead to poor performance or even malfunction. In order to maintain the performance a mechanism to deal with these variations is required. An algorithm implemented on the digital chip with variables such as power output, I and Q imbalance and an will tune the biasing conditions until an acceptable performance is obtained. This negates the process variation characteristics of primitive circuit elements, such as transistors and resistors, built on CMOS technology. Digital signal is inherently resilient against noise and small changes in the performance of the circuit and has integration capability and low manufacturing cost. A serial peripheral interface bus (SPI) with clock speed of 200 MHz was selected to program operational parameters into internal addressable register bank. The read and writable register bank is 6 bit wide, with one 6-bit control register, one 6-bit status register and sixty 6-bit data registers summing up to 62 deep. The output of 6 bit register group is individually connected to 6 bit digital to analog converter (DAC). There are 60 such DACs in the system. In tern the output of individual DAC is connected to respective RF component tunning signals. The DCI control for the transceiver was accessed via a port on the transceiver board via wirebonding, shown in Fig. 8 (b).
V. CONCLUSIONS The transceiver demonstrates a very high level of integration of digital, analog, and millimeter-wave circuits, both passive and active components, on a single silicon die. The integration of a digital control interface on the CMOS chip as a method to complement the low-grade performance of CMOS circuit at high frequency, which is a unique solution that only available on CMOS technology, is an important step to move millimeter-wave circuits and systems onto low-cost CMOS chip. The successful implementation of this transceiver has qualified CMOS technology for low-cost millimeter-wave design. ACKNOWLEDGEMENT The authors would like to acknowledge support from IBM, MOSIS and National ICT Australia. National ICT Australia is funded by the Australian Government's Department of Communications, Information Technology, and the Arts and the Australian Research Council through Backing Australia's Ability and the ICT Research Centre of Excellence programs. REFERENCES [1] [2]
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Fig. 6 Micrograph of the receiver
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Fig. 7(a) Conversion gain of the 60-GHz receiver versus LO frequency. (b) Conversion gain of the 60-GHz receiver versus IF frequency
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(b) Fig. 8 (a) Measured IP3 of the receiver (b) Board mounted transceiver.
