Body PiN diode inactivation with low on-resistance achieved by a 1.2 kV-class 4H-SiC SWITCH-MOS Yusuke Kobayashi1,2, Naoyuki Ohse1, Tadao Morimoto2, Makoto Kato2, Takahito Kojima1, Masaki Miyazato1,2, Manabu Takei1,2, Hiroshi Kimura1 and Shinsuke Harada2 1
Fuji Electric Co., Ltd., Matsumoto, Nagano, Japan, email:
[email protected],
[email protected] 2 National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan
Abstract— Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss. Particularly in lower breakdown-voltage-class SBDintegrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode. Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5μm was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer. The fabricated 1.2 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific onresistance, and low leakage current. I. INTRODUCTION Reducing the power loss and total chip area of power devices contributes greatly to achieving highly efficient and compact power conversion applications. SiC power devices have attractively low power loss because critical electric field of SiC is higher than that of Si. In addition, the power loss of SiC MOSFETs has been reduced by using a trench gate with low specific on-resistance (RonA) [1–2], characterized by a small cell pitch and high channel mobility on the trench sidewall [3]. Moreover, the total area of the chip, including that of the freewheeling diode, can be reduced by eliminating an external Schottky barrier diode (SBD). In this case, the body-PiN-diode embedded in the MOSFET is employed as a freewheeling diode. However, the forward voltage drop (VF) increases under forward conduction stress, because stacking faults grow with bipolar current flowing in a phenomenon known as forward degradation [4]. Moreover, the switching loss in a reverse recovery period is increased by a bipolar action. The solution to these body-PiN-diode-related problems lies in integration of the SBD into the MOSFET, thus reducing the conduction current flowing through the p-n junction [5–7], and further suppressing the voltage drop at the p-n junction (Vpn) in comparison with an external SBD because the voltage drops in the drift layer and substrate are not applied to the Vpn. However, such SBD integration results in an increase in the RonA of the MOSFET, because additional space is required to embed the SBD. Therefore, reduction in the cell pitch is important to achieve low RonA in the SBD-integrated MOSFET. Here, we developed a novel device structure of an SBD-integrated MOSFET with a small cell pitch, and demonstrate inactivation of the body-PiN-diode in the presence of a low RonA in a 1.2 kV-class SiC MOSFET.
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II. SIMULATION AND DEVICE CONCEPT Reduction in cell pitch is more effective in the lower breakdown-voltage-class MOSFETs from the perspective of RonA reduction, because the channel resistance becomes dominant in the RonA (Figure 1). Cell pitch reduction is also important for inactivating the body-PiN-diode in an SBDintegrated MOSFET. Figure 2 shows the simulation results for different PiN widths of an SBD-integrated PiN diode with a voltage initiating PiN diode action, which is defined as VF at a hole current density of 10 A/cm2 (VF_bipolar). High VF_bipolar means low Vpn, indicating improved suppression of the body– PiN-diode action. The VF_bipolar of the SBD-integrated PiN diode is higher than that of a PiN diode with an external SBD and increases with decreasing PiN width. Vpn in the case of the SBD-integrated PiN diode is equal to the voltage drop at the Schottky interface (VSBH) and the voltage drop by the spreading resistance (Vsp) (Figure 3). Therefore, reducing Vsp with a narrow PiN width induces a low Vpn. Reducing the PiN width is especially important in low breakdown-voltage-class MOSFETs, because Vsp dominates VF. Therefore, cell pitch reduction becomes more important in lower breakdownvoltage-class MOSFETs, not only for RonA reduction but also for inactivation of the body-PiN-diode. In other words, a small cell pitch in an SBD-integrated MOSFET simultaneously achieves low RonA and inactivation of the body-PiN-diode in a low breakdown-voltage-class MOSFET. Here, we developed a novel SBD-integrated MOSFET with a small cell pitch, called an SBD-wall-integrated trench MOSFET (SWITCH-MOS). An SBD surface and MOS channel are formed on the trench sidewall to reduce the cell pitch (Figure 4). On the basis of experience with a conventional trench gate MOSFET without SBD [8], buried p+ layers are arranged under both trenches to suppress the offstate electric field at the trench bottoms. Notably, extension of the buried p+ layers beyond the trenches effectively suppresses the electric field to below 1.5 MV/cm (Figure 5). Furthermore, the spread resistance is extremely small by the narrow PiN width, because of the presence of buried p+ layers divided into two regions in a unit cell (Figure 6). As a result, a VF_bipolar of over 10 V was obtained by the SWITCH-MOS with a cell pitch of 5 μm and PiN width of 1.5 μm, and the current density (JC) initiating PiN diode action was estimated to be about 10 times the rated JC (Figure 7). The small cell pitch of the SWITCH-MOS in a 1.2 kV-class MOSFET was thus expected to achieve a low RonA, inactivation of the body-PiNdiode until a high JC was reached, and a low electric field on the trench bottoms.
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III. DEMONSTRATION Figure 8 shows a cross-sectional image of a fabricated 1.2 kV SWITCH-MOS with a cell pitch of 5 μm. The gate trench and SBD trench were simultaneously etched. Extended buried p+ layers were formed under the trenches by ion implantation, followed by epitaxial growth for the n-type region and the pbase. After deposition and annealing of the ohmic metal, the Schottky metal was deposited on the trench sidewall. Schottky barrier height (SBH) is 1.33 eV, which is higher than the SBH on the Si face [7] because the SBH in SiC depends on the crystal axis [9]. Figure 9 shows the typical output characteristics of the fabricated SWITCH-MOS, measured at room temperature. Figure 10 shows the RonA and threshold voltage (Vth) when the p-base was formed with varying doping concentrations. The Vth was extracted at ID = 0.018 A/cm2.The distribution is similar to that for a conventional UMOS (in which the SBD is not integrated) with the same cell pitch. Figure 11 shows the blocking characteristics of the SWITCH-MOS. The breakdown voltage and leakage current are almost identical to those of the conventional UMOS, indicating that the electric field at the Schottky interface is adequately suppressed by the junction barrier of the extended buried p+ layers. The extended structure contributes to this suppression, because the leakage current increases with increasing negative extension. These results indicate that the integrated SBD in the SWITCH-MOS exhibits no degradation of on- and off-state static characteristics compared with the conventional UMOS without an SBD. Figure 12 shows the forward characteristics of the body diode. The body-PiN-diode in the conventional UMOS has lower resistance than a junction barrier Schottky (JBS) diode, because of the conductivity modulation in drift layer induced by bipolar action, when the forward voltage is higher than 2.4 V for the built-in potential. Therefore, the inflection point of the SWITCH-MOS corresponds to the appearance of bipolar action in the body-PiN-diode. The inflection point of a SWITCH-MOS with a 5 μm cell pitch appears at 2800 A/cm2—far higher than the 200 A/cm2 for a SWITCH-MOS with 16 μm cell pitch, demonstrating the impact of cell pitch reduction in improving inactivation of the body-PiN-diode. Consequently, the 1.2 kV-class SWITCH-MOS that we developed adequately inactivated the body-PiN-diode. Figure 13 shows the reverse recovery switching waveforms of the body diode. The reverse recovery charge (Qrr) is halved in the SWITCH-MOS, indicating that the bipolar action is suppressed owing to inactivation of the bodyPiN-diode. The Qrr of the SWITCH-MOS is related to the displacement current of the output capacitance, which is largely determined by the breakdown-voltage-class. Figure 14 shows forward degradation as a function of current stress. ΔVF was examined after the application of each current density stress for 90 s, followed by 180 A/cm2 stress for 10 min. Although the ΔVF of the body-PiN-diode in the conventional UMOS increases because of forward degradation, the ΔVF of the SWITCH-MOS was not detected until 1640 A/cm2 (the limit of our stress-test equipment). Figure 15
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shows photoluminescence mapping images after application of a stress of 1640 A/cm2. Although many stacking faults are observed in the conventional UMOS, no such faults are generated in the SWITCH-MOS. These results demonstrate that forward degradation due to bipolar action in the bodyPiN-diode is successfully suppressed. These results indicate that our 1.2 kV-class SWITCHMOS with a 5 μm cell pitch inactivated the body-PiN-diode at high current density, with a low RonA and low leakage current. IV. CONCLUSION Reduced cell pitch in an SBD-integrated MOSFET was effective in achieving both inactivation of the body-PiN-diode and a low RonA, especially in low breakdown-voltage-class MOSFETs. The SWITCH-MOS successfully incorporated a reduced cell pitch, with a low electric field in the off-state, using a trench SBD and trench MOSFET with buried p+ layers. The 1.2 kV-class SWITCH-MOS with 5 μm cell pitch that we fabricated demonstrated inactivation of the body-PiN-diode at a high current density, as well as a low RonA, low leakage current and low switching loss. ACKNOWLEDGMENT This work has been implemented under a joint research project of Tsukuba Power Electrics Constellations (TPEC). REFERENCES [1] S. Harada, M. Kato, T. Kojima, K. Ariyoshi, Y. tanaka, and H. Okumura, “Determination of optimum structure of 4H-SiC Trench MOSFET,” International Symposium on Power Semiconductor Devices and ICs (ISPSD), p.253, 2012. [2] T. Nakamura, Y. Nakano, M. Aketa, R. Nakamura, S. Mitani, H. sakairi, and Y. Yokotsuji, “High performance SiC trench devices with ultra-lon ron,” IEEE International Electron Devices Meeting (IEDM), 26.5.1, Dec. 2011. [3] K. Ariyoshi, S. Harada, J. Senzaki, T. Kojima, Y. Kobayashi, Y. Tanaka, R. Iijima, and T. Shinohe, “Comparative Study of Characteristics of Lateral MOSFETs Fabricated on 4H-SiC (11–20) and (1–100) Faces,”, Materials Science Forum, Vol. 821, pp. 721–724, 2015. [4] H. Lendenmann, P. Bergman, F. Dahlquist, and C. Hallin, “Structure of recombination-induced stacking faults in high-voltage SiC p-n junction,”, Material Science Forum, Vol. 433, p.901, 2002. [5] S. Hino, H. Hatta, K. Sadamatsu, Y. Nagahisa, S. Yamamoto, T. Iwamatsu, Y. Yamamoto, M. Imaizumi, S. Nakata, and S. Yamakawa, “Demonstration of SiC-MOSFET Embedding Schottky Barrier Diode for Inactivation of Parasitic Body Diode”, Material Science Forum, Vol. 897, pp.477–482, 2017. [6] W. Sung and B. J. Baliga, “On Developing One-Chip Integration of 1.2kV SiC MOSFET and JBS diode (JBSFET)”, IEEE Transactions on Industrial Electronics, Vol. PP, 2017. [7] Y. Kobayashi, H. Ishimori, A. Kinoshita, T. Kojima, M. Takei, H. Kimura, and S. Harada, “Evaluation of Schottky barrier height on 4HSiC m-face {1–100} for schottky barrier diode wall integrated trench MOSFET”, Japanese Journal of Applied Physics, Vol.56, 04CR08, 2017. [8] S. Harada, Y. Kobayashi, A. Kinoshita, N. Ohse, T. Kojima, M. Iwaya, H. Shiomi. H. Kitai, S. Kyogoku, K. Ariyoshi, Y. Onishi, and H. Kimura, “1200V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage,”, Materials Science Forum, Vol. 897, pp. 497–500, 2017. [9] A. Itoh, and H. Matsunami “Analysis of Schottky Barrier Heights of Metal / SiC Contacts and Its Possible Application to High Voltage Rectifying Devices”, Physica Status Solidi A, Vol. 162, pp. 389–408, 1997.
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Fig. 1. Simulation results for RonA components, based on a fabricated SiC trench MOSFET [8]
Fig. 2 VF at hole current of 10 A/cm2 initiating bipolar action, as a function of PiN width, in an SBD-integrated PiN diode
Fig. 3. Components of VF in SBD-integrated PiN diodes, compared between cell pitches of 5 and 10 μm.
Fig. 4. Schematic cross-sectional illustration and features of the SWITCH-MOS
Fig. 5 Electric field of trenches in the off-state as a function of extension of the buried p+ layers beyond the trenches
Fig. 6 Components of VF in SWITCH-MOS
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Fig. 7. JC and VF at hole current of 10 A/cm2 initiating bipolar action in a 1.2 kV-class SWITCH-MOS
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Fig. 8. Cross-sectional SEM image of the SWITCH-MOS with a 5 um cell pitch
Fig. 10. RonA-Vth trade-off in the SWITCH-MOS and conventional UMOS
Fig. 11. Blocking characteristics with variation in the buried p+ layer extension in the SWITCH-MOS and conventional UMOS
Fig. 13. Reverse recovery waveform of the body diode as a freewheeling diode in the SWITCH-MOS and conventional UMOS
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Fig. 9 ID-VD characteristics of the SWITCH-MOS
Fig. 12. Forward characteristics of the body diode in the SWITCH-MOS
Fig. 14. Forward degradation as a function of forward current stress in the SWITCH-MOS and conventional UMOS
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Fig. 15. Photoluminescence mapping images of stacking faults after stress of 1640 A/cm2 for 90 seconds
