Vol. 35, No. 5
Journal of Semiconductors
May 2014
A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 m CMOS Lü Wei(吕伟)1 , Luo Duona(罗多纳)1 , Mei Fengcheng(梅逢城)1 , Yang Jiaqi(杨家琪)1 , Yao Libin(姚立斌)2 , He Lin(贺林)1; , and Lin Fujiang(林福江)1 1 Department 2 Kunming
of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China Institute of Physics, Kunming 650223, China
Abstract: This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 m CMOS technology, the proposed SAR ADC consumes 6.3 W at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 300 m2 . Key words: SAR ADC; monotonic switching; common mode stabilizer; comparator offset DOI: 10.1088/1674-4926/35/5/055006 EEACC: 2570
1. Introduction Wireless sensor networks (WSN) contain multiple sensor nodes. In most cases, changing their batteries is impractical or impossible, therefore battery-less devices that harvest energy from the environment are required. A variety of energy harvesting technologies, such as solar power, RF power and mechanical vibration, can be utilized as power sources to provide a supply voltage of around 0.6 VŒ1 . Therefore, ultra low voltage operation with high power efficiency is desirable for WSN applicationsŒ2 4 . The analog-to-digital converter (ADC) is a fundamental block for every sensor node. Among different conversion topologies, the SAR ADC is known for its low power, small area and ability to operate under a low supply voltage. SAR ADCs with a supply voltage of 0.6 V or below were reported in Refs. [5–7]. The time domain comparator in Refs. [5, 6] was proposed to reduce the input-referred noise and offset, so that the total power can be reduced, but at the cost of a slow conversion speed. The choice of capacitive DAC is also critical. The monotonic switching (MS) schemeŒ8 and Vcm -based switching schemeŒ9 are among the most energy-efficient DAC topologies. With these topologies, the energy loss due to switching is reduced by 81% and 88% respectively, compared to the conventional structureŒ10 . Although the Vcm -based switching scheme is slightly more power efficient than the MS scheme, it is not suitable for ultra-low voltage operation, as the transistor cannot be fully turned on at the Vcm . Overall, the MS DAC topology is an ideal candidate for ultra-low voltage, not only for its power efficiency, but also for its high speed and simplified digital logic.
One drawback associated with the MS scheme is that it causes a large shift of the common mode (CM) voltage, which in turn leads to a large variation of the offset in the dynamic comparator. The varying offset is the major source of integral nonlinearity (INL) in the MS schemeŒ11 . To solve this problem, Reference [8] used a fixed bias current in the dynamic comparator; however, it is not suitable for a 0.6 V design due to the limited headroom. Reference [7] proposed a supply-boost technique to increase the supply voltage of the comparator to 2VDD , which allows constant current biasing but significantly increases the power consumption. This paper introduces a novel common mode stabilizer (CMS) network to the conventional MS DAC array to stabilize the CM at the instant of comparison; it allows the use of the MS technique under 0.6 V or even below while it does not suffer from the power issue in Ref. [7].
2. Architecture design 2.1. Monotonic switching Figure 1 shows the architecture of the monotonic switching SAR ADCŒ8 , which consists of a pair of sample/hold switches, a differential capacitive DAC array, a dynamic comparator, as well as SAR control logic. The capacitive DAC array is used both for sampling the input signal and subtracting the sampled input with a digital approximation. The sample/hold (S/H) switches are implemented by NMOS transistors, with their sampling clock boosted to maintain the on-resistances constant. During the sampling phase, the sample/hold switches are
* Project supported by the National Natural Science Foundation of China (No. 61204033) and the Natural Science Foundation of Jiangsu Province (No. BK2012214). † Corresponding author. Email:
[email protected] Received 21 October 2013, revised manuscript received 5 November 2013 © 2014 Chinese Institute of Electronics
055006-1
J. Semicond. 2014, 35(5)
Lü Wei et al.
Fig. 1. Block diagram of SAR ADC based on monotonic switching (MS) scheme.
Fig. 2. Waveform of the MS procedure as well as its associated common mode (CM) shift.
turned on and all the bottom plates are reset to VDD . Since the S/H switches turn off, the signal is sampled on the DAC, and the conversion begins. At first, the comparator directly performs the first comparison without switching any capacitor. Then one of the MSB capacitors is switched from VDD to ground, while the other one remains unchanged, according to the comparison result. This procedure is repeated until the LSB is resolved. Figure 2 shows the waveform of the MS procedure. After the comparison, only one side of the DAC is switched while the other side stays unchanged, which causes not only a differential change of the DAC output, but also a gradual decreasing in the CM from 0.5VDD to VSS . This large CM shift leads to a significant variation of the offset in the dynamic comparator, which is the main source of integral nonlinearity (INL) of the SAR ADCŒ11 . 2.2. Common mode-dependent offset of the comparator
term depends on the overdrive voltage. When the MS structure is used, the input CM of the comparator gradually decreases. To save power, the preamplifier is used dynamically, which means that its tail transistor is turned on and off by the clock signal. Once the tail transistor is turned on, it operates in linear region, and the voltage drop over the tail transistor can be practically ignored. Thus the overdrive voltage of the input pair suffers the same variation as the input CM. In Ref. [8], an additional fixed current biasing transistor is used in serial with the clocked tail transistor to provide a constant current to the input pair even in the presence of large CM variation. It effectively reduced the variation range of the inputreferred offset. However, such a strategy cannot be applied to a 0.6 V design due to the limited voltage headroom. 2.3. Architecture of the proposed SAR ADC Figure 3 shows the block diagram of the proposed SAR ADC, which adds an additional CMS circuit to the existing MS SAR ADC to stabilize the input CM of the dynamic amplifier. The CMS circuit is actually a binary weighted capacitive array sharing the same top plates with the MS DAC. Each unit of the CMS circuit contains two identical capacitors whose bottom plates will experience a transition from VSS to VDD to compensate for the CM drop of the MS DAC. The size of capacitors in the CMS array is half of their corresponding capacitors in the MS DAC. The VSS to VDD transition is implemented by an OR gate whose inputs are 1P–4P and 1N–4N, the control signals of the DAC. Since most of the CM variation happens around the MSB, only four bits of CMS are applied. The CM variation after the fourth bit will cause negligible error in the ADC output. Figure 4 shows the first four bit-cycles waveform of MS DAC with CMS applied. During the i th comparison, the voltage swing on each side of the DAC is given by
In the MS structure, the offset variation in the comparator degrades the performance of the ADC. Assume that the offset voltage of the comparator is dominated by the preamplifier, whose offset voltage can be expressed asŒ12 VGS VTH S R Vos D VTH C C ; (1) 2 S R where VTH is the threshold voltage mismatch of the input pair, S=S is the size mismatch of the input pair, and R=R is the resistance mismatch of the loading pair. From Eq. (1), we can find that the offset voltage is related to the device mismatches and bias conditions. The first term in Eq. (1) is a static error which does not affect the performance of the ADC. The second
VPi D
VNi D .Bi
Bi
1/
2n
i 1
Cu
CT 2n
i 1
CT
VDD C
Cu
VDD C
2n
i 2
Cu
CT 2n
i 2
CT
VDD ;
Cu
VDD ;
(2)
(3)
where VPi and VNi are the i th voltage swing on the positive and negative side of the DAC, Cu is the unit capacitance, CT is the total capacitance of the DAC, and Bi is the ith comparison result. The first and second terms in Eq. (2) represent the contributions from the MS network and the CMS network, respectively. No matter what Bi is, the summation of VPi and
055006-2
J. Semicond. 2014, 35(5)
Lü Wei et al.
Fig. 3. Block diagram of the proposed SAR ADC with CMB.
Fig. 5. Circuit of double tail dynamic comparator.
Fig. 4. Timing of comparison, CMS, and DAC settling.
VNi remains zero, which means that the input CM keeps constant at the comparison instant.
3. Implementation and simulation results 3.1. Dynamic comparator In this design, the comparator is actually a dynamic preamplifier followed by a dynamic latch (shown in Fig. 5)Œ13 . Since the CM sticks to 0.5VDD , a NMOS input stage is chosen to enhance the comparison speed. The incoming rising edge of CLKC turns on the tail transistor M1 and turns off the loading transistors M3, which causes the discharge of the nodes FN and FP. The discharging rate depends on the magnitude of the input signal and thus can be treated as a time-varying gain stage. The dynamic latch is activated slightly after the dynamic preamplifier. 3.2. Asynchronous control logic Asynchronous logicŒ14 is adopted that removes the need for an extra high frequency clock, to save power and improve conversion speed. Figure 6 shows the diagram of the asynchronous control logic, which is comprised of three parts: selfoscillator, shift register and data register. The self-oscillator is used to generate the clock signal CLKC for the comparatorŒ15 . The comparator itself is embedded in the self-oscillator. An OR
gate is used to detect whether the comparison is completed. After the signal Valid, the output of the OR gate feeds back to reset the comparator. The alternation of comparison and reset builds a self-oscillation. The self-oscillator can be turned on and off by the system sampling clock CLKS. It is important to note that the CLKC generator should provide an adequate DAC settling time to meet the accurate requirement. The signal Valid is used to trigger the shift register. As a result, the outputs of the shift register (CK1–CK10) will successively transit from low to high, which in turn triggers the corresponding D flip–flop in the data register and stores the current comparison result. The outputs of the data register are used directly to control the switches in the DAC. 3.3. Simulation results of the CMB The proposed CMS is simulated and compared against the conventional MS scheme, with comparator offset taken into account. The transistor-level implementation of the comparator is replaced with a behavioral model. Monte Carlo simulation is employed to determine the variance of the offset at different CM input. It is worth mentioning that the comparator used in the MS scheme has a p-type input pair due to the decreasing CM. Figure 7 plots the simulated offset variance of the ptype comparator versus different CM input. It is easy to identify two operation regions in the figure: strong inversion and sub-threshold. In the strong inversion region, the offset voltage depends linearly with the input common mode. In the subthreshold region, the offset voltage is almost constant due to the almost constant overdrive voltage in this region. Although it looks like operating the comparator in the sub-threshold region can minimize the offset variation as well as its associated
055006-3
J. Semicond. 2014, 35(5)
Lü Wei et al.
Fig. 6. Block circuit of asynchronous control logic.
Fig. 7. Simulated offset voltage of the p-type input comparator versus CM.
Table 1. Monte Carlo simulation results. Parameter ENOB (bit) DNL (LSB) INL (LSB) Without CMS 9.07 5.2 6.3 With CMS 9.9 0.25 0.3
ADC conversion error, the comparator is relatively slow in this region. The simulated offset variance can be best fitted to two segmental straight-lines and included in the behavioral model of the comparator. Transient simulation is performed to check the ADC performance degradation due to the CM-dependent offset. It should be noted that the capacitor mismatch is not included in this simulation. Both the conventional MS scheme and the MS C CMS scheme are simulated. Their simulated DNL and INL are plotted in Figs. 8 and 9 and summarized in Table 1. The soundness of the CMS method is clearly seen. 3.4. Layout implementation The core layout area of the ADC is only 120 300 m2 , and the DAC array occupies more than 60% of the total area. The unit capacitor is implemented by the metal–oxide–metal (MOM) capacitors with a unit capacitance of 3.6 fF for the requirement of capacitor matching. Split DAC capacitor arrays
Fig. 8. Simulation results of (a) DNL and (b) INL without CMS.
are utilized, and an attenuation capacitor with a unit cell is used to separate the split capacitive array into a 7 bits MSB and a 2 bits LSB arrayŒ16 . The mismatch on the DAC has a major impact on the linearity of the ADC, so the symmetrical layout structure of the DAC was critical. To ease the routing between the DAC and the SAR control logic, only the first three bits in the DAC array are symmetrically-arranged. An array of dummy capacitors is used around the capacitor to ensure a uniform environment.
055006-4
J. Semicond. 2014, 35(5)
Lü Wei et al.
Fig. 9. Simulation results of (a) DNL and (b) INL with CMS. Fig. 11. Measured (a) DNL and (b) INL of the proposed SAR ADC.
Fig. 10. Die photograph of the proposed SAR ADC.
4. Measurement results The proposed ADC was fabricated using the 1P8M 0.13m CMOS process. A die photograph of the chip is shown in Fig. 10. The chip was directly mounted on a printed circuit board. The analog input signal and clock are both provided by an Agilent 33250A function arbitrary waveform generator. The digital outputs of the proposed ADC are captured by an Agilent 1681A logic analyzer and processed using Matlab to obtain their static and dynamic performance. Figure 11 shows the measured DNL and INL. The measured peak DNL and INL are 0:91/C1:58 LSB and 1:15/C1:99 LSB, respectively. Figure 12 shows 16384 point
FFT of the ADC output for fin D 40.039 kHz and 489.2578 kHz at 1 MS/s. Figure 13 plots the measured SNDR and SFDR versus the input frequency at 1 MS/s. At low input frequency, the measured SNDR, SFDR and ENOB are 52.6 dB, 67.95 dB and 8.44 bit respectively. At near Nyquist frequency, the SNDR and SFDR drop by 1.35 dB (loss of 0.22 bit ENOB) and 1.5 dB, respectively. Figure 13 also shows the measurement results of SNDR/SFDR against the sampling frequency with the Nyquist rate input. The ENOB degradation is mainly caused by the noise from the dynamic comparator. The total power consumption of the SAR ADC is 6.3 W at 0.6 V and 1 MS/s sampling rate. The analog power, including the capacitive DAC array, CMS circuit is 2.1 W. The digital power, including clock generator and output register is 2.3 W. The power of the comparator is 1.9 W. The proposed ADC achieves 21 fJ/conversion-step at the Nyquist frequency with 1 MS/s. The performance of the proposed SAR ADC is summarized in Table 2, and compared with several recently published SAR ADCs. The proposed ADC achieved a comparable performance to the published 0.6 V designs. The speed advantage of our design over the time-domain comparator based approach can also be clearly seen.
5. Conclusion This paper presents a 0.6 V 10 bit monotonic switching SAR ADC with a novel common mode stabilizer to address
055006-5
J. Semicond. 2014, 35(5)
Lü Wei et al.
Fig. 12. 16384 points of FFT spectrum at (a) fin D 40.039 kHz and (b) 489.2578 kHz.
Fig. 13. Measured (a) dynamic performance versus input frequency at 1 MS/s, (b) dynamic performance versus sampling frequency with Nyquist rate input.
Parameter
Table 2. Performance comparison with other published SAR ADC. Ref. [5] Ref. [6] Ref. [7] Ref. [8]
Sample rate (MHz) Supply voltage (V) Power (W) ENOB (bit) Nyquist input FOM D Power/2ENOB *2fin Technology Chip area (mm2 /
1.1 0.5 1.2 7.5 6.3 40 nm 0.0112
0.1 0.6 1.3 8.64 32 0.18 m 0.125
the offset variation problem in the dynamic comparator. Simulation results show that without DAC capacitor mismatch, the proposed CMS method improves the peak DNL from 5.2 LSB to 0.25 LSB, and the peak INL from 6.3 LSB to 0.3 LSB. The measured peak DNL and INL are –0.91/+1.58 LSB and –1.15/+1.99 LSB, which are still well below the simulation results without CMS. The first prototype achieved a SNDR of 51.25 dB at the Nyquist frequency with 1 MS/s, and consumes 6.3 W at the 0.6 V supply. The proposed ADC with common mode stabilizer avoids the use of the constant current biasing or supply boosting technique, and can operate at 0.6 V, which is perfectly suitable for WSN application.
0.5 0.6 5 9.45 14.3 0.18 m 0.05
50 1.2 826 9.18 29 0.13 m 0.052
This work 1 0.6 6.3 8.22 21 0.13 m 0.036
Acknowledgment The authors would like to thank the lab center of information science in USTC for EDA tools support, and Prof. Huang Lu for tapeout support, IMECAS for scholarship support, Zhu Guanglong, Cheng Gong, and Yu Mingyuan for measurement support.
References [1] Rajput S S, Jamuar S S. Low voltage analog circuit design techniques. IEEE Circuits Syst Mag, 2002, 2(1): 24
055006-6
J. Semicond. 2014, 35(5)
Lü Wei et al.
[2] Verma N, Chandrakasan A P. An ultra low energy 12-bit rateresolution scalable SAR ADC for wireless sensor nodes. IEEE J Solid-State Circuits, 2007, 42(6): 1196 [3] Yip M, Chandrakasan A P. A resolution-reconfigurable 5-to-10bit 0.4-to-1 V power scalable SAR ADC for sensor applications. IEEE J Solid-State Circuits, 2013, 48(6): 1453 [4] Harpe P, Dolmans G, Philips K, et al. A 0.7 V 7-to-10 bit 0to-2 MS/s flexible SAR ADC for ultra low-power wireless sensor nodes. IEEE European Solid-State Circuits Conference (ESSCIRC), 2012: 373 [5] Shikata A, Sekimoto R, Kuroda T, et al. A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS. IEEE J Solid-State Circuits, 2012, 47(4): 1022 [6] Lee S K, Park S J, Park H J, et al. A 1.3 W 0.6 V 8.7-ENOB successive approximation ADC in a 0.18 m CMOS. Symposium on VLSI Circuits Digest of Technical Papers, 2009: 242 [7] Lin G Y, Huang H Y, Hsieh C C, et al. A 0.05 mm2 0.6 V 500 kS/s 14.3 fJ/Conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager. IEEE Asian Solid-State Circuits Conference (ASSCC), 2012: 165 [8] Liu C C, Chang S J, Huang G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid-State Circuits, 2010, 45(4): 731 [9] Zhu Y, Chan C H, Chio U F, et al. A 10-bit 100-MS/s reference-
[10]
[11]
[12] [13]
[14]
[15]
[16]
055006-7
free SAR ADC in 90 nm CMOS. IEEE J Solid-State Circuits, 2010, 45(5): 1111 Ginsburg B P, Chandrakasan A P. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. IEEE Int Symp Circuits and Systems (ISCAS), 2005: 184 Liu C C, Chang S J, Huang G Y, et al. A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 m CMOS process. Symposium on VLSI Circuits Digest of Technical Papers, 2009: 236 Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill, Inc, 2000 Schinkel D, Mensink E, Klumperink E, et al. A double-tail latchtype voltage sense amplifier with 18 ps Setup+Hold time. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2007: 314 Chen S M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-m CMOS. IEEE J Solid-State Circuits, 2006, 41(12): 2669 Promitzer G. 12-bit low-power fully differential noncalibrating successive approximation ADC with 1 MS/s. IEEE J Solid-State Circuits, 2001, 36(7): 1138 Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1 V 3.8 W 100 kS/s SAR ADC with time-domain comparator. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2008: 246
