Advanced Materials Research Vols. 765-767 (2013) pp 2439-2443 © (2013) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/AMR.765-767.2439
A 10bit 1MHZ SAR ADC for automobile electronics MCU with Rail-to-Rail input swing Chengying Chen 1, a, Lan Dai 2,b , Xiaoyu Hu 3,a , Yong Hei 4,a 1
Institute of Microelectronics of Chinese Academy of Sciences, Beijing, 100029, CHN;
2
North china university of technology, college of information engineering,Beijing, 100144, CHN;
a
b
a
a
[email protected] ,
[email protected] ,
[email protected] ,
[email protected]
Keywords: Successive Approximation; Analog-to-Digital Converter; MCU; Digital-to-Analog Converter.
Abstract. Based on the DAC structure of single sampling capacitor that insures the rail-to-rail input swing a 10bit 1MHZ SAR ADC is implemented in GSMC 0.18µm 1P6M CMOS Mixed-Signal process for automobile electronics MCU. The measurement results show that in 1.8V power supply, 51KHZ input frequency and 1MHZ clock frequency, the SFDR is 71.364 dB, ENOB is 9.49 bit, total power is 2.24mW, which meet the application requirements of automobile electronics MCU. Introduction In recent years, with the rapid development of industrial control technology and large scale integrated circuit technology, the micro controller (MCU) is widely used in consumer electronics, industrial automation systems and various vehicle electronic equipments. Successive approximation analog-to-digital converter (SAR ADC) has advantages in accuracy, speed, power consumption and cost. And it is also easy to realize the multi-channel control, which is suitable as interface of analog IP and digital signals. So SAR ADC has become the most important part of MCU analog front end. With the continuous progress of design technology and design methods, SAR ADC is facing serious challenges of low power consumption, high performance, low cost. Based on the principle and particularity of automobile electronics MCU application, this paper introduces a design of a 16-channels 10bit 1MHZ SAR ADC. Compared with the design results before, this work has high performance and comparability, and meets the application requirements of automobile electronic MCU. MCU system and SAR ADC consideration As the core of internal operations and processing module, MCU is used all over the balloon, gating, audio and other dozens of systems. Various types of MCU play an important role in the vehicle. Figure 1 shows a block diagram of the MCU structure of automobile electronics in this design, which mainly includes the DW8051 processor, flash, SRAM memory, 16-channels 10bit ADC, LDO, PLL, digital controller and various types of interface. As the most important module of MCU, SAR ADC will bear the responsibility of converting the complex analog signal to digital signal. The signal frequency of automobile electronic MCU is generally in the range of tens of KHZ. The constraints of the SAR ADC mainly are in power, area and accuracy. The SAR ADC chip is implemented in GSMC 0.18 µ m 1P6M CMOS mixed signal process. The design goals are 10bit/1MHZSPS, 16 channels and overall power consumption is less than 3mW.
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Fig.1 Diagram of MCU SAR ADC design The basic structure of 16-channels 10bit 1MHZ SAR ADC as shown in Figure 2, consists of 16 analog sampling switches, sample and hold circuit, analog-to-digital converter (DAC), comparator, successive approximation logic register and the timing control circuit[1-5]. The principle of SAR ADC is using the binary search algorithm that makes the output of the DAC successively approximate input signal. For an N bit SAR ADC, it requires at least N+2 conversion cycle (2 of the conversion cycle is used for sampling and the end of conversion signal generation respectively).
Fig.2 DAC structure and switch timing The charge-redistribution DAC structure with MIM capacitor is shows in fig.3. In order to achieve rail-to-rail swing, single sampling capacitor structure is adopted. Although the structure meets the rail-to-rail requirements, in charge calibration each LSB will be reduced to half of the original that increases the comparator resolution requirement.
Fig.3 DAC structure The working process of DAC is divided into sampling and charge redistribution phase two stages. In the sampling phase, the S0~S9 switch are connected with GND. At the same time switch Ssample is closed, so that the lower plate of capacitor CS is connected with the VIN. While Svcm is closed, the upper plate is connected with the common-mode voltage VCM. Then the charge stores on the sampling capacitors CS. After the sampling phase and in the hold phase, the switch Svcm is off, the switch Ssample and switch S0~S9 are connected with GND. So the DAC output voltage for the time is: Vx =
Qx 64C(vcm − vin) + vcm(15C //1C + 63C) 1024 = =− vin + vcm Ct 15C //1C + 127C 2047
(1)
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In the charge redistribution phase, firstly the tenth bit (MSB) is set to 1, which means lower plate of C9 is connected to VREF through the switch S9. If vin>1/2*vref, the output of the comparator is 0 and the MSB remains 1; Otherwise the MSB is set to 0. After that the ninth bit is set to 1 and it repeats operation of the tenth bit. Then the eighth bit, the seventh bit….until the first bit (LSB) is determined. Finally the output of DAC is: 10 b 1024 (2) Vx = (−vin + ∑ 11i−i vref ) + vcm 2047 i =1 2 bi is the value of the i bit of DAC, which is 0 or 1. The comparator consists of three pre-amplifiers and a latch. The three pre-amplifiers provide 5, 10, 10 times gain respectively to overcome the effect of offset voltage. The block diagram and circuits are shown in Fig.4.
Fig.4 Comparator structure and circuit SAR logic register is realized by RTL code. A complete ADC conversion requires 14 clock cycles, including 2 sampling cycles, 11 successive approximation cycle and 1 end signal generation cycle. Figure 5 shows the SAR logic timing, where Sample is the two-cycles sampling signal, Vc is the comparator output, D9 ~ D0 are DAC digital input, B9 ~ B0 are parallel digital output of ADC , and EOC is a single cycle end signal[6]. It works as follows: when the two cycle sampling signal ends, D9 is preset to 1; While the first rising edge of the clock arrives, based on the output of the comparator, if the output of the comparator is 0, D9 remained unchanged at 1. If the comparator is 1, then D9 is set to 0. Similarly, when the second rising edge of the clock arrives, D8 is preset to 1, according to the output of the comparator the D8 remains 1 or is set to 0. And D7, D6….D0 follows. Until the EOC signal rises, the D9 ~ D0 are output as B9 to B0.
Fig.5 SAR logic control timing
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The timing control circuit is mainly composed of 14 bit gray code counter, delay unit, D flip-flop and gate circuit. The control timing is shown in Figure 6, where reset and latch are reset signal of pre-amplifier and latch in comparator[7].
Fig.6 Timing control circuit output timing Measurement result The MCU chip microphotograph is shown in Fig.7. It was fabricated in a 0.18 um 1P6M CMOS process and the SAR ADC is in the left top of MCU whose size is 0.58mm 2 (0.75mm x 0.77mm)。
Fig.7 Chip of MCU In 1.8V voltage supply, the static test results showed that DNL and INL are 0.4LSB and 0.45LSB; In Dynamic testing, when the input signal is 51KHZ, clock 1MHZ, FFT spectrum analysis result is shown in Figure 8, SFDR is71.364dB, SNDR is 58.942dB and ENOB is 9.49bit.
Fig.8 Measurement FFT result of SAR ADC Table 1 compares the performance of the proposed SAR ADC with that of previous work. The power consumption, area and resolution of this design have the very high comparability with them.
Advanced Materials Research Vols. 765-767
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[1] [2] [3] [4] This work
Tab.1 Performance Comparison of other Published SAR ADC Tech Resolution Sample Power Area ENOB (CMOS) (bit) Rate (mW) (mm2) (bit) (MHZ) 0.18µm 10 2 3.1 0.25 9.05 0.35µm 10 2 3 0.4 8 0.25µm 10 0.5 1 1.26 9.57 0.35µm 10 1 2.7 0.4 9.8 0.18µm 10 1 2.24 0.58 9.49
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FOM (pJ/conv.step) 2.92 5.86 2.63 3.02 3.09
Conclusions A 10bit 1MHZ SAR ADC is proposed and implemented in GSMC 0.18µm 1P6M CMOS Mixed-Signal process for automobile electronics MCU. By exploiting single capacitor sampling technique, the proposed ADC achieves rail-to-rail input swing. The measurement results show that in 1.8V power supply, 51KHZ input frequency and 1MHZ clock frequency, the SFDR is 71.364 dB, ENOB is 9.49 bit, total power is 2.24mW, and the area is 0.58mm 2 , which meet the application requirements of automobile electronics MCU. Acknowledgements This work was financially supported by the National Natural Science Foundation of China (No.61001052), Beijing Natural Science Foundation (No.4123096) and Scientific Research Project of Beijing Educational Committee (No.KM201110009004). References [1] S.Long, Q.Yin and J.Wu: J. Research & Progress of SSE, VOL. 27(2007), p.380-384. [2] J.Cai, F.Ran and M.H.Xu. “IC design of 2Ms/s 10bit SAR ADC with low power”, The IEEE International Conference on High Density Packaging and Microsystem Integration, Shanghai, China, pp. 112-117,2007. [3] J.Park, H.J.Park and J.W.Kim, “A 1 mW 10-bit 500KSPS SAR A/D converter”. The IEEE International Conference on Circuit and System", Geneva, Switzerland, pp. 581-584, 2000. [4] P.Confalonleri, M.Zarnprogno and F.Girardi, “A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges”, Solid-State Circuits Conference, Proceeding of the 30th European. Leuven, Belgium, pp. 255-258, 2004.. [5] H.Neubauer, T.Desel and H.Hauer, “A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 µm CMOS using self calibration and low power techniques”, The 8th IEEE International Conference on Electronics, Circuit and System, Malta, pp. 859-862,2001. [6] H.Hong, G.Lee: J. IEEE Journal of Solid-State Circuits, VOL. 42(2007), p.2161-2168. [7] B.Razavi: Design of analog CMOS and integrated circuit (McGraw-Hill, New York, 2001)
