A 1.9-GHz CMOS Low Noise Amplifier with Partial Source Degeneration L. C. Kretly, C. E. Capovilla, and A. Tavora A. S.
Abstract— A 1.9GHz fully integrated Low Noise Amplifier with Partial Source Degeneration technique (LNA-PSD) has been implemented in a 0.35µm CMOS technology. This amplifier provides a forward gain of 11dB with a noise figure of 3.4dB while drawing 11mW from a 1.8V supply source. Index Terms— LNA, wireless communications, LNA-PSD, receiver, CMOS.
I. I NTRODUCTION
I
N most receiver systems, the LNA is the first active device to amplify the signal, so it needs to give the higher gain possible with the minimum noise figure. When designing a LNA there are many compromises between impedance matching, linearity, gain, noise figure, and power consumption [1]. Usually, the main objective is to obtain Simultaneous Noise and Input Impedance Matching (SNIM) for any power consumption. There are many design techniques for LNA’s, among all, the most popular ones are: SNIM [2], Classical Noise Matching (CNM) [3], Power-Constrained Noise Optimization (PCNO) [4], and Power-Constrained Simultaneous Noise and Input Matching (PCSNIM) [5]. The most typical configurations for low noise amplifiers are common gate (CG) and common source (CS). The input impedance matching of a CG configuration is realized easier, however it has more noise sources when compared to the CS configuration leading to noise figures from 2 to 3 dB above the CS. The input impedance matching results in optimized gain and noise figure for the amplifier. Considering a single MOS transistor in common-source configuration, a degeneration of the source by an inductance Ls produces a desirable real part on the input impedance. Unfortunately, due to some technology restrains the designer must work with restrained options for Ls values limiting the capability to achieve a desirable impedance. In addition, source degeneration introduces transconductance reduction due to the Ls voltage drop, but also increases stability of the amplifier. A solution to compensate this drawback is the use of partial source degeneration technique. II. LNA-PSD D ESIGN The LNA-PSD technique consists on braking the common source transistor amplifier into two parts. The first transistor This work was partially supported by PNPD-CAPES/CNPq. L. C. Kretly, C. E. Capovilla, and A. Tavora A. S. are with the Department of Microwave and Optics, School of Electrical and Computer Engineering, University of Campinas, UNICAMP, Brazil. E-mails:
[email protected],
[email protected], and
[email protected]
978-1-4244-5357-3/09/$26.00©2009IEEE
has no inductance degeneration while the other parallel transistor has the Ls degeneration. In so doing, the designer is able to impose two different bias currents leading to a more refined adjustment of input impedance matching. Another advantage is to obtain a larger gain due to the non-degenerated parcel. The same design strategy can be used with cascode connected LNAs using the same parallel transistors in the CS configuration. In Fig. 1 is shown the LNA-PSD topology and its input impedance equivalent model. VDD Lg
Lchoke
VG
Vout Cgs2
Lg
MN1
MN2
Zin
Zeq Cgs1
Ls
Zin
Fig. 1.
Ls Rx
LNA-PSD circuit topology.
The impedance seen after the gate inductor Lg , is given by a capacitor Cgs1 of the non-degenerated part in parallel with the impedance of the degenerated part, that is, the impedance of a degenerated CS amplifier is: Zeq = ZCgs1 //(ZCgs2 + ZLs + gm2 ZCgs2 ZLs )
(1)
So, the equivalent input impedance assumes the form:
Zeq
Rx ωLs − ωC1gs2 − j ωC gs1 = 1 1 Rx + j ωLs − ωCgs1 − ωCgs2 1 ωCgs1
(2)
m2 Ls = ωT Ls is a real parcel introduced Note that Rx = gC gs2 and controlled by the degenerated transistor. In this way, both imaginary and real part of Zeq become dependent of gm2 . That means an extra capability to fine adjust the circuit input impedance, with more parameters to control, besides the improvement in the amplifier gain. There is a compromise between noise figure and gain of the amplifier. As the gain increases, the noise figure decreases [6], so any improvement in gain means a better noise figure parameter. When designing this kind of amplifier a good starting point is to set the length of the transistor to the minimum of the technology and than use the equation 3 for optimized noise to choose a value for width [7]. 30
III. E XPERIMENTAL R ESULTS The LNA-PSD shown in Fig. 2 was designed for AMS (AustriaMicroSystems) 0.35µm CMOS technology. The design includes a CMOS voltage divider to generate bias voltage to the gate of the amplifier, a choke inductor(Ld ) in parallel with a capacitor (Ctank ) to form a resonant tank, thus increasing the choke isolation. The DC block capacitor (CB2 ), and an matching inductor at the output of the amplifier (Lout ) form a matching network together with the parasitic elements of the RF PAD (Rpad and Cpad ) and the wirebonding inductance (Lwirebond ). Described in tables I and II are the components parameters involved in this design.
The circuit presents better input impedance matching and gain at 1.9GHz. The circuit drowns less current and consequently gives less gain to the signal, when compared to the simulation. This occurs mainly due to process variation. At 1.9GHz it consumes 6mA from 1.8V supply source and produces 11dB of gain, as shown in Fig. 3. The measured input impedance is 51+4jΩ and stability factor Mu is 2.2. For unconditional stability, the stability Mu-factor must be above 1 [8]. The measured noise figure is 3.4dB and isolation between output and input is -26dB. LNA-PSD Gain 15
gain @ 1.9 GHz = 11 dB 10
5
Gain (dB)
1 (3) 3ωLCox Rs Where, ω = 2πf , L = channel length, Cox = oxide capacitance and Rs = generator resistance. Once the total width is determined, the inductors must be chosen to better fit the impedance matching, as done for a single CS LNA. So, the transistor width value must be split in the half, and gradually changed until a good relation between input impedance, noise figure, stability, and power consumption is achieved. Wopt ≈
0
-5
-10 1,0
1,5
VDD MP1
Fig. 3.
RG
Ld
Lwirebond
CB1
Lout
CB2
Lwirebond
RF out
50 Ω
Lg
MN1
Cpad
MN2
50 Ω
Rpad Cpad Ls Rpad
Fig. 2.
2,5
3,0
Measured gain from designed LNA-PSD.
Ctank
MN3
RF in
2,0
Frequency (GHz)
As can be seen in Fig. 4, from the intersection between the third harmonic intermodulation curve (IM3) and the output power curve, are obtained the measured IIP3=-0.13dBm (Third Harmonic Input Intercept Point) and OIP3=8.3dBm (Third Harmonic Output Intercept Point). This measure was taken, by using the two tone technique, where the fundamental frequency is 1.9GHz, and the tones are 5MHz displaced from the fundamental.
LNA-PSD schematic for simulation.
20 10
TABLE I
OIP3= 8.3 dBm
T RANSISTORS PARAMETERS . Circuit
Device
W (µm)
L (µm)
N. of Fingers
LNA-PSD
MN1 MN2
CMOS divider
MP1 MN3
85 170 30 5
0.35 0.35 0.35 0.35
17 17 6 1
Output Power (dBm)
0 -10 -20 -30
Pout (f0) IM3 (2f1-f2) Projected Pout Projected IM3
-40 -50
IIP3= -0.13 dBm
-60 -20
TABLE II RLC Ls
-10
-5
0
Input Power (dBm)
PARAMETERS .
Fig. 4. Lg , Ld , Lout
-15
CB1 , CB2
Cpad
Rpad
Measured output power and IM3 plots.
RG
The fabricated LNA-PSD is shown in Fig.5, including ESD protection. The circuit layout was designed in such way that it is possible to introduce bias voltage directly to the gate, All measurements were made by means of a JIG of test, without using the CMOS divider. This was done for further composed by a 50 Ω transmission line over PCB, connected adjustment of the operating frequency, but we think that it through SMA connectors and wirebonding. is more interesting to show the circuit operation as it was 2009 SBMO/IEEE MTT-S International Microwave & Optoelectronics Conference (IMOC 2009) 31 13.3nH
2.42nH
4.48pF
340f F
500Ω
1.63kΩ
originally designed, without compensating the operating point due through variations on bias parameters.
Fig. 5.
[7] B. Pham, “A 1.9ghz gilbert mixer in 0.18u cmos for a cable tuner,” Department of Electronics, Carleton University, Canada, 2003. [8] M. L. Edwards and J. H. Sinsky, “A new criterion for linear 2-port stability using geometrically derived parameters,” IEEE Transactions on Microwave Theory and Techniques, vol. 40, pp. 2303–2311, December 1992.
LNA-PSD Die (1600 x 1600µm).
IV. C ONCLUSIONS In this work was presented a fully integrated LNA-PSD operating at 1.9GHz. Besides the shift in the operating frequency, caused by process variation, the LNA presented good experimental results, proving the functionality of the partial source degeneration technique. It was fabricated using a 0.35µm CMOS technology from AMS. The main measurements were also presented demonstrating a good performance in producing compatible gain for the consumed power, small increase in noise figure, 2.9dB simulated against 3.4dB measured. The circuit operates unconditionally stable and is linear for small power at the input, almost 0dBm according to the IIP3 and OIP3 results. LNA-PSD topology can be extended to multiple transistors, not only two, and a cascode configuration is also applicable, as any other technique that uses CS amplifier. V. ACKNOWLEDGMENTS The authors would like to thank PMU-FAPESP for providing grants for the fabrication of the prototypes and CTI for the wirebonding work. R EFERENCES [1] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998. [2] S. P. Voinigescu, M. C. Maliepaard, J. L. Showell, G. E. Babcock, D. Marchesan, M. Schroter, P. Schvan, and D. L. Harame, “A scalable high-frequency noise model for bipolar transistors with application optimal transistor sizing for low-noise amplifier design,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 1430–1439, September 1997. [3] H. A. Haus, “Representation of noise in linear two ports,” Proc. IRE, vol. 48, pp. 69–74, January 1960. [4] D. K. Shaeffer and T. H. Lee, “A 1.5 v, 1.5 ghz cmos low noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 745–758, May 1997. [5] P. Andreani and H. Sjoland, “Noise optimization of an inductively degenerated cmos low noise amplifier,” IEEE Transactions on Circuits and Systems, vol. 48, pp. 835–841, September 2001. [6] S. Andersson, C. Svenson, and O. Drugge, “Wideband lna for a multistandard wireless receiver in 0.18 m cmos,” Europpean Solid-State Circuits Conference - ESSCIRC 2003, pp. 655–658, September 2003.
2009 SBMO/IEEE MTT-S International Microwave & Optoelectronics Conference (IMOC 2009)
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