A 32*32-bit multiplier using multiple-valued MOS ...

124

IEEE JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

23, NO. 1, FEBRUARY

1988

A 32 X 32-bit Multiplier Using Multiple-Valued MOS Current-Mode Circuits SHOJI

KAWAHITO, TATSUO

Abstract circuits

— A 32x 32-bit

multiplier

has been fabricated

based on the radix-4 complement

adders (SDFA’S)

using

in 2-pm

signed-digit

multiplication

(SD)

technology.

number

can be performed

about 23600

MEMBER, SENIOR

For the multiplier

system, 32X32-bit

two’s

with only three-stage

addition

SD full

scheme.

transistors

and the effective

multiplier

size is about 3.2X 5.2 mmz, which is half that of the corresponding CMOS

multiplier.

is comparable

The multiply

IEEE,

MEMBER,

binary

time is less than 59 ns. The performance

to that of the fastest binary

multiplier

MICHITAKA

reported.

A 32x 32-bit

realized

I

logic (MVL)

is a

LSI with binary

array

structure

input

using

scheme [8], [9]. New hardware generation

and out-

It is confirmed

based

on

the

SD

to the fastest binary

speed, power

dissipation,

a three-stage

algorithms

and an SD-to-binary

have also been developed

multiplier.

multiplier

that multiple-valued

multiplier

partial-product

superior T IS well known

IEEE,

YAMADA

by a regular

binary-tree technique

INTRODUCTION

MEMBER,

HARUYASU

put has been designed using multiple-valued current-mode circuits and implemented in 2-pm CMOS technology. The multiplier, based on the radix-4 SD number system, is

pact I.

KAMEYAMA,

IEEE, AND

curreut-mode

multiple-valued

CMOS

using a binary-tree

The chip contains

STUDENT HIGUCHI,

for a

conversion

for a high-speed

that

com-

the multiple-valued

number

system

multiplier

is totally

[10] in terms

of

and chip area.

very attractive approach for ULSI or wafer-scale integration (WSI) because of the reduction of interconnec-

tion

complexity

Recently, various

and

the number

the advantage applications

arithmetic

circuits, new

rent-mode

[1]. in

and so on [2]–[5].

active

However,

multiple-valued

and the practical

very few This paper

CMOS

implementation

not

only

for

Since multiple-valued tion

of

the

implemented circuits

signed

addition coding digit,

is direct

circuits

et al.

with

of a

can be

by the use of multiple-valued

the multiple-valued

Dao

bidirectional

multiple-valued

always

for

injection

by logic

current-mode

cir-

the implementation

of

tional current-mode circuits proposed here are essentially suitable for the implementation of SD arithmetic and facilitate wired summation including polarity. Fig. 1 illustrates From

the principle

Kirchhoff’s

of bidirectional

current

sum of the two currents to

successive

polarity

and

current

value of the drain

current-mode

Fig.

3(a)

depletion-mode

written

current-mode

levels

summary

are detected

and

where

arithmetic

using several basic circuits. of

available

basic

Fig.

bidirectional

circuits.

current

Id used as a constant

current

is

as K(W/L)(V~)2

(1)

where K, W, L, and VT are, respectively,

/0200-0124$01

z is applied

circuits,

shows a current source using a p-channel MOSFET. In the ideal case, the saturation

Id=

tance

summation.

z is equal to the

x and y. The current

are performed a

wired

law, the current

bidirectional

LSI circuits

0018 -9200/88

integrated

suitable

current-

as introduced

arithmetic circuits based on a sign-symmetrical number representation such as the SD number system. The bidirec-

operations 2 provides

Manuscript received July 3, 1987; revised September 10, 1987. S. Kawahito, M. Karneyama, and T. Higuchi are with the Department of Electronic Engmeenng, Tohoku University, Aoba, Aramaki, Sendai 980, Japan. H. Yamada is with the Semiconductor Research Center, Matsushita Electric Industrial Company, Ltd., Monguchi, Osaka 570, Japan IEEE Log Number 8718226,

of multiple-valued

such “single-directional”

are not

current-mode circuits proposed here are quite suitable for the implementation of SD arithmetic because the linear summation including polarity can be performed by simple wiring [5]. This property enables the interconnection complexity to be greatly reduced and the resulting arithmetic to be very compact.

concept

CIRCUITS

is that of wired summation

cuits

for the representa-

CURRENT-MODE

The most important mode circuits [11]. However,

also for multiplication.

the arithmetic

very compactly

[7]. In particular,

but

BIDIRECTIONAL

cur-

32x 32-bit multiple-valued multiplier chip based on the radix-4 signed-digit (SD) number system [6]. In the SD number representation, carry propagation during addition and subtraction is always limited to one position to the left. This property of the number system is useful

II.

image processors,

have been fabricated.

LSI-oriented

circuits

devices

has been confirmed

such as memories,

LSI chips based on MVL describes

of

of MVL

parameter,

the channel

.00 01988 IEEE

width,

the transconduc-

the channel

length,

et al.: 32X32-BIT

KAWAHITO

MULTIPLIER

USING

CURRENT-MODE

125

CIRCUITS

>+--,”, Z=x+y

Fig.

1.

Bidirectional

wired summation. (a)

\ .--—. o

~uNcTloN Y=o {

If %i

y=m

if~;i

Fig.

2.

y=() If XST 1=1, ,n FACTOR [ Y=m If x>T

Y,=-aix foi al,~cALE

Basic bidirectional

current-mode

X2X

Fig.

If X20

x%)

x~ox%xIf

!

i-i

(a) Fig.

3.

i

Y

(b)

4.

Bidirectional characteristics

x-o

while

if x is less than Iy 1, z is negative.

Y

respectively,

(c)

value

using

quite

insensitive

unit

current

dose control.

of BDCI

V~~, and requires

of the supply

no bias source or connection

voltage

other than

A voltage-switched current source can easily be implemented using a p-channel enhancement-mode MOSFET Using

with

the current

these current

constructed

source as shown

sources, a threshold

in Fig.

detector

3(b).

can be

as shown in Fig. 3(c) [11], [12]. The function

is

given by

where

TIa

currents, threshold In

and

current input current.

ifx>T

mI~

are the

bidirectional

is used

for

direction, current, There

and

When

1-=()

(),

I-=

():

if V= V~D/2

I+=

(),

I-=

I,

if V < V~D /2 1

obvious to 1+ obtained

points points 1-,

and negative

respectively.

at the output

.

(3)

the

z values are equal

Replicas

of BDCI

a bidirectional

replicas

is the scaling

of

the an

of the input

mirrors:

HI. The

a current

One is to invert

are two types of current

of 1+

through

current

currents

SIGNED-DIGIT

and 1-

current

are

mirrors.

can be decomposed

by using BDCI.

radix-4

SD

negative.

ARITHMETIC

arithmetic

because of easy compatibility

CIRCUITS

is used with

in

the

the binary

multiplier system and

compactness of the implemented chip. The radix-4 SD number is represented by the following symmetrical digit set of seven values:

NMOS .L=

y be defined

if V > VD~/2

two single-directional

This

The polarity of the bidirectional current can be detected by a bidirectional current input circuit (BDCI) shown in Fig. 4(a). Let the current injected from V~~ through the current source x be defined positive, while the current flowing into the ground through the output of the NMOS mirror

of

A and B will be determined as the for z >0 and z

+4,

=1,

ifz1>2

o,

Ct=–l,

if–l