A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 2, FEBRUARY 2006

A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage Applications Ming-Feng Huang, Chung J. Kuo, Senior Member, IEEE, and Shuenn-Yuh Lee, Member, IEEE

Abstract—This paper presents a 5.25-GHz folded-cascode evenharmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP3 ) of 0.03 dBm, and second-order input intercept point (IIP2 ) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz. Index Terms—Current reuse, even-harmonic mixer (EHM), folded cascode, low power.

I. INTRODUCTION

T

HE low-voltage RF integrated-circuit (RFIC) development for portable communication equipments has been a focus due to the advances in device technology for high-speed applications. More and more designers have proposed RFIC for high-speed and low-voltage applications, such as low-noise amplifiers (LNAs), mixers, and voltage-controlled oscillators (VCOs) [1]–[8]. Moreover, due to the potential in reducing the operational frequency of the synthesizer and in decreasing the dc offset, the even-harmonic mixer (EHM) become an attractive topology when being applied to wireless communication systems. Therefore, the low-voltage EHM would be a novel challenge for portable communication equipments. The simplified direct conversion receiver is shown in Fig. 1. As , the local oscillator (LO) leakage is fed through to the mixer input, while the reflection factors such as LNA and the antenna can strengthen this leakage, resulting in a self-mixing behavior by the mixer [9]–[13]. This causes a time-varying dc offset and reduces the dynamic range of the baseband circuit. On the contrary, the self-mixing mechanism can be overcome using the EHM. For , the RF signal is mixed with the second harmonic of the LO Manuscript received June 11, 2005; revised August 29, 2005 and November 2, 2005. This work was supported in part by the Chip Implementation Center, by National Nano Device Laboratories, by the Wireless Communication Laboratories, and by National Science Council, Taiwan, R.O.C., under Grant NSC 93-2220-E- 194-013. M.-F. Huang and S.-Y. Lee are with the Department of Electrical Engineering, National Chung Cheng University, Chia-Yi 62107, Taiwan, R.O.C. (e-mail: [email protected]; [email protected]). C. J. Kuo is with the Magnetics and Microwave Business Unit, Components Business Group, Delta Electronics Inc., Taoyuan 333, Taiwan, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2005.862665

Fig. 1. Simplified direct conversion receiver: n = 1 with time-varying dc offset and n = 2 without the time-varying dc offset.

signal and modulated as the desired output frequency. Since the LO frequency is equal to one half of the RF frequency, no dc component is generated by LO leakage, achieving the time-varying self-mixing-free result. Moreover, the LO fundamental leakage can be effectively cancelled by a low-pass filter (LPF) and cannot influence the baseband circuit [9]–[13]. Therefore, if the EHM is employed in direct conversion receivers, the dc offset resulted from self-mixing can be significantly improved and the desired operational frequency of the synthesizer can be relaxed. In recent years, active EHMs [10]–[19] suffer from either high power consumption, complex architecture with quadrature, high supply voltage, or low operational frequency. In this paper, the proposed folded-cascode EHM (FEHM) can reduce the required supply voltage using the folded technique, achieve the acceptable conversion gain and linearity using the current reuse structure, obtain low power consumption, and possess a simple architecture using the frequency-doubling circuit. In addition, theoretical studies of linearity, conversion gain, and noise figure are presented in this paper to facilitate the optimal design. The benefits of this proposed FEHM have also been demonstrated by the measured and simulated results. The remainder of this paper is organized as follows. Section II presents the mathematical analysis of the mixer architecture. In addition, the measured and simulated results are described in Section III, which demonstrate the theoretical analyses. Finally, Section IV briefly concludes this paper.

0018-9480/$20.00 © 2006 IEEE

HUANG et al.: 5.25-GHz CMOS FEHM FOR LOW-VOLTAGE APPLICATIONS

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Fig. 3.

Fig. 2. Original topologies of the CMOS EHM: (a) without and (b) with complementary frequency-doubling circuits.

II. MIXER ARCHITECTURE A. Circuit Principle The origination of an EHM topology [17]–[19] is constructed as shown in Fig. 2(a). This topology consisting of a frequency-doubling circuit – , a current reuse pair and ), and the output load is built. ( When the LO signal is injected, the frequency-doubling circuit – ) provides a double-frequency signal mixed with the RF input signal from the current reuse circuit, thus achieving . However, a demanded IF frequency because of the asymmetric structure shown in Fig. 2(a), when the RF input signal is sufficiently large for push–pull operation, the equivalent -channel common-source amplifier has a larger enhanced gain (described Section II-B) than the -channel must be small to improve the linearity, thus one. Hence, causing a degrading conversion gain. Moreover, when the input signal is small, the second-order distortion from the current reuse circuit increases to degrade the second-order ) performance under a poor balanced IF intercept point ( port caused by the process variation. Therefore, the EHM with the frequency-doubling circuit pair is reconstructed with complementary property, as shown in Fig. 2(b). This topology consisting of a frequency-doubling circuit pair ( – and ), a current reuse pair ( and – – ), and – is built. However, the headroom voltage the output load is too large for low-voltage applications. In this paper, a modified FEHM is proposed in Fig. 3. This topology consisting of a current reuse pair ( – and ), a frequency-doubling circuit with the – – , and two high impedance current sources output load

Proposed CMOS FEHM.

( and ) is modified from the original topology shown in Fig. 2(b) using the folded technique. When LO signal is injected, the LO fundamental frequency and its all-odd harmonics can be cancelled and its even harmonic signals can be produced (in Fig. 3). Because the at the virtual-ground nodes and and ) possess high impedances, the current sources ( LO even harmonic signals are reflected and further injected into the current reuse circuit to be a time-vary mixing source. Moreover, since the overdrive voltages of the current reuse circuit function of the LO even harmonic signals, a mixing behavior is achieved. As mentioned, the current sources ( and ) provide high impedances; hence, the current reuse circuit at the push–pull operation can similarly possess the positive and negative enhanced gains to improve the circuit linearity. Furthermore, because of a near complementary structure in the FEHM, the second-order distortion from the current reuse circuit can be reduced. On the other hand, if those current and ) are implemented by LC tanks with the sources ( almost zero headroom voltage, the mixing frequency from the frequency-doubling circuit can be selected and the fourth harmonic and higher order ones of the LO signal can be filtered out. Therefore, the FEHM possesses similar performance as that of the original topology shown in Fig. 2(b) under the lower supply voltage. The subcircuits such as the frequency-doubling circuit and the current reuse circuit are also described in details in the next section. B. Circuit Analysis To analyze the circuit behavior, the inherent square-law current model is used. The inherent square-law current model is suitable for the circuit tendency analysis. Owing to the short-channel effects [17]–[19], the second-order term of the overdrive voltage affects the circuit trend larger than the higher order terms. Therefore, the inherent square-law model with the channel length modulation can be described as

(1) where

is the transconductance parameter, and are, respectively, defined as the input signal and the

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Fig. 4. Operation of frequency-doubling circuit.

overdrive voltage, is the channel-length modulation coeffi. cient, is the threshold voltage, and The LO stage is built using the frequency-doubling circuit and as presented in Fig. 4. From (1), the drain currents ( ) of the transistors – can be written as

(2) where is the and LO sinusoidal input signal with amplitude is the overdrive voltage of – . According to (2), the total current of the frequency-doubling circuit is equal , i.e., to

(3) where (4) In view of (3), the fundamental frequency of the LO signal is cancelled and the LO double-frequency signal is and . Therefore, the produced at the nodes frequency-doubling circuit provides a double frequency and reduces the LO-RF leakage to improve the time-varying dc offset. and The RF stage is built using current reuse circuit ( ) as shown in Fig. 5(a). In this structure, both transistors and ) provide the transconductances to acquire ( high conversion gain under the same bias current [20], [21]. The proof is straightforward. For example, according to (1), can be obtained as

Fig. 5. Current reuse circuit is used to improve circuit linearity: (a) when V is a small signal with small signal gain, (b) when V is a positive large signal with negative enhanced gain, and (c) when V is a negative large signal with positive enhanced gain.

signal is large enough or around the input 1-dB compression , the input signal is like a large input signal and, point hence, the current reuse topology is just like a push–pull circuit possessing the ability of gain enhancement to increase its dynamic range. The phenomenon can also be interpreted as shown in Fig. 5(b) and (c) [17]–[19], where the positive and negative enhanced gains combine as a full waveform, resulted in an expansion of the circuit dynamic range. Therefore, the current reuse circuit improves linearity and reduces the influence of second-order distortion. In Fig. 3, the full FEHM is built using a current reuse pair, a frequency-doubling circuit, and two high impedance current is replaced by a buffer with high input sources. In general, and ) are impedance, and, thus, the current sources ( . According assumed to be of the same constant value to Kirchhoff’s current law, the sum of the drain currents ( – and – ) equals , i.e., (6) Hence, according to (1) and (6), the relationship between and is obtained as

(7) Similarly, the relationship between tained as

and

is ob-

(5) where

and are the dc currents of and , respectively. From (5), both transistors contribute the transconductance to increase the conversion gain, which coincides with [20]. At the same time, the second harmonic is elimfrom asyminated mutually to avoid the more degraded metry caused by process variation. Moreover, when the input

(8) On the other hand, from (5), the time-varying transconductance related to the overdrive voltage can be written as (9)


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where and are the transconductances of the - and -transistors of the current reuse pair, respectively, and the subscript CR denotes the overall transconductance using the current reuse technique. Furthermore, according to [17]-[19], and using the Taylor’s series by assuming of the expansion, the resulting differential output voltage proposed FEHM becomes

TABLE I SUMMARY OF DESIGN RULE

(10) where

(11) and

input 1-dB compression point assuming the input impedance and thus can be described as dBm

(12) are the fundamental coefficients of the RF signal from - and -transistors, respectively, which are important for the noise figure, and

(13) is related to the conversion gain information at the up/down converter, and (14)

expressed in dBm and of 50 is defined in [22] (17)

where (18) In terms of the noise figure analysis, the drains of transistors are virtual ground, and the proposed FEHM is designed and fabricated at the IF frequency with 500 kHz (described in the next section). The RF stage flicker noise by RF feed-through signal dominates the noise contribution, and the noise figure (NF) can be approximated by the following expression [23]: (19)

is the major third nonlinear coefficient affecting the linearity. Hence, the RF input feed-through gain is shown as

where

(20) (15) To mention that is proportional to thermal noise and must be small to reduce the input-referred noise of the RF stage applied specially to the super heterodyne receivers. Also, from the according to (13), the conversion gain RF stage to IF output is

(21) with the definition (22) The subscripts and denote the channel types of transistors, and are the process-dependent constants, and are the oxide-silicon interface area, is Boltzmann’s constant, and is the absolute temperature. C. Design Considerations

(16) because is where the conversion gain is one-half of assumed to be the sinusoid functions. Furthermore, the desired

According to (7), (8), and (16)–(22), we have several rules of thumb (shown in Table I) for the circuit design of the proposed FEHM. From the conversion gain consideration,

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Fig. 6. Operational limitation of the current reuse circuit as the injected larger ). signal (i

, and must be large. When and are sufficiently large, and move toward the weak inversion region and the flicker noise is reduced and simultaneously. On the other hand, if both are located in the weak inversion region, the linearity is deincreases the conversion gain, graded. Moreover, a large but the linearity will be degraded. As a result, the embraceable and are necessary, and the tradeoff must be made between the transistor sizes and biases of the current reuse pair. D. Operational Limitations In the above theoretical studies, all of the transistors are assumed to work normally and are arranged at the saturation and region. However, when some parameters (such as ) increase or decrease gradually over a certain value, the transistor may be separated from the saturation region or be triggered by other parameters, resulting in a degraded performance (such as conversion gain). Therefore, the operational limitation is discussed as below. is injected, and (shown When LO power in Fig. 6) will modulate the LO double-frequency signal. Owing to the property of transistor current related to the square overdrive voltage, the current reuse circuit is induced a dc voltage from the LO double frequency signal, resulting in an increasing equivalent overdrive voltage. Therefore, the conversion gain will be degraded and the LO power property in Table I will be violated. For example, according to (4), the overdrive voltage of -transistor can be written as

(23) where is the original overdrive voltage without the injected signal from transistor source. is the equivalent load . Since the transistor current is proportional to from node is the square overdrive voltage, the squared

(24) and thus the induced dc level

is (25)

Fig. 7. Operational limitation of the frequency-doubling (a) Frequency-doubling circuit with the constant current = constant and v = constant. (c) When V (b) V and v = constant. (d) When V V and v v

circuit. source.

V

Identically, the induced dc level at -transistor is similar to (25). As a result, by referring to Table I, we will have a peak on the curve of LO power tendency. and LO power are Similarly, we assume that a proper employed as shown in Fig. 7(a) and (b). Since the swing of is larger than the boundary under a dc level LO signal , the frequency-doubling circuit works normally. Thus, is increased with the LO swing being larger than the when boundary, the tendency will follow the theoretical studies shown increases gradually up to , the in Table I. However, if becomes smaller than the boundary swing of LO signal as shown in Fig. 7(c), and the frequency-doubling circuit could not be a switch, thus degrading the conversion gain. Therefore, tendency. In other words, as we have a peak on the curve of shown in Fig. 7(d), we can increase the LO power up to to let the frequency-doubling circuit work normally under the acceptable induced dc level from (25). Consequently, the pawill be a tradeoff in rameters between the LO power and system design. III. CHIP IMPLEMENTATION AND MEASUREMENTS The TSMC 0.18- m CMOS process with all required device models is adopted. To validate the theoretical tendency and operational limitation, the proposed FEHM is implemented as shown in Fig. 8, where the frequency-doubling circuit – , the current reuse pair – and – ), ) without the resistor-tuning and a unit gain buffer (instead of network are employed as the main EHM circuit. Moreover, instead of the high-impedance current source (shown in Fig. 3), and ) are also adopted to reduce the two LC-tanks ( the voltage headroom and select the LO double-frequency signal. To make sure that the input signal can be injected into the proposed FEHM and reduce the signal distortion, the RF and ) and LO matching network matching network ( and ) are constructed. The capacitors ( serving as the bias buffer are also adopted to reduce the impact on the parasitic inductance from dc power supply. Finally, the characteristics of the mixer are simulated and measured at an RF frequency of 5.25 GHz (port 1) and an LO frequency


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Fig. 8. Schematic of the proposed full monolithic FEHM. Fig. 10. Simulation of the transistor size property on the frequency-doubling circuit, where the unit finger M has 7.5-m transistor width.

Fig. 9.

Measurement setup.

2.625 GHz (port2) with an IF frequency 500 kHz (IF port), whose setup is illustrated in Fig. 9. A. Decision of Main Circuit Parameters The simulation of the conversion gain versus the transistor size of the frequency-doubling circuit, under the minimum length of 0.18 m, is shown in Fig. 10. Apparently, a larger transistor size or LO power can increase the conversion gain, which verify our theoretical studies. Moreover, to maintain the Line S (shown in Fig. 10) under a constant conversion gain, either a small transistor size with a large LO power or a large transistor size with a small LO power is required. Therefore, a tradeoff between the transistor size and LO power is necessary, and thus the 240- m transistor width is chosen owing to the reduction of the required LO power. Simulation results of the conversion gain, LO power, and are shown in Fig. 11. An extreme occurs on the conversion gain plot that is matched to the operational limitation versus of property. Further, using the efficiency between the dc power consumption and required LO power, we consider the only plot before reaching Line X. Hence, to maintain Line Y under a constant conversion gain, we can increase LO power at the weak inversion region to reduce the and bias the to decrease the dc power consumption or can use a larger required LO power. Therefore, for low LO power requirement, and 3.6-dBm LO power are chosen for chip the 0.57-V implementation.

Fig. 11. Simulation of the transistor bias and LO power on the frequencydoubling circuit.

For the transistor size of current reuse circuit, we find that the about 3/2 is available under transistor size ratio with one half , and hence 0.45 V at the weak inversion region is chosen. The simulation for transistor size versus the fundamental performances is also shown in Fig. 12. Apparently, we can get the extreme on the fundamental performance curves, which are matched to the theoretical tendency and operational limitation as (24)–(25). Moreover, for FEHM to work well, a larger transistor size biased at the weak inversion region is shown. In addition, the maximum conversion gain is obtained and, thus, 240- m at – and 160- m – at of 0.45 V are chosen for chip implementation. B. Measurement for Characteristics of the FEHM from RF to IF ports are The conversion gain, NF, and at the LO port, measured by sweeping the LO power and as shown in Fig. 13. Their tendencies are all consistent with our theoretical studies. That is to say, increasing LO power or inaway from the weak inversion region can enhance creasing the conversion gain and improve the noise figure. Moreover, linearity can be improved by reducing the LO power or biasing

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Fig. 12. Simulation of the transistor size property on current reuse circuit, where the unit fingers of - and -transistors are, respectively, with 7.5 (in micrometers) and 5 (in micrometers) transistor widths, and the solid arrow signifies the theoretical trend and the dotted arrow indicates the limited theoretical trend.

p 2N

n

2N

Fig. 14.

Measured results of the IIP and IIP performances.

limited. As shown in Fig. 13(a), owing to the induced dc voltage from the LO double-frequency signal at the current reuse circuit, when the LO power exceeds 2.5 dBm, the conversion gain and noise figure are worsened. Furthermore, when the LO power exceeds 0.5 dBm, the linearity is improved. As shown limits the switch operation of in Fig. 13(b), an excessive is larger the frequency-doubling circuit. Therefore, when than 0.625 V, the conversion gain and noise figure are worsened. is greater than 0.675 V, the linearity is Moreover, when improved. Overall, the tendencies of the measurement all agree with our studies. That is, the conversion gain, linearity, and noise figure can be optimized by choosing proper LO power and parameters. From the experimental data, we obtain 8.89-dB conunder version gain, 24-dB noise figure, and 16.7-dBm , and 6.57-mW power the 3.6-dBm LO power, 0.62-V consumption. and Further, the input second and third intercept point ( ) are measured by two-tone test using a down-converted center frequency of 500 kHz with 100-kHz space as plotted (desired in Fig. 14. Apparently, after getting 25.07 dBm , and 69.88 dBm , signal amplitude), 76.35 dBm and 2.665 dBm are obtained using 26.21 dBm

(26) (27)

Fig. 13. Measurement of the fundamental performance (such as conversion , and NF), where the solid arrow signifies the theoretical trend and gain, IP the dotted arrow indicates the limited theoretical trend. (a) LO power property. (b) property.

V

toward the weak inversion region. Moreover, since the ex) may cessive parameter’s value (such as LO power and happen in the practical design, the theoretical trend could be

and are the second- and third-order intermodwhere and ulation products, respectively. Hence, 17.32 dBm 11.555 dBm are measured at the 8.89-dB conversion gain. The isolation from LO to IF ports is measured by scanning the LO power from 6.6 to 4.4 dBm, as shown in Fig. 15. Apparently, the 2LO-IF isolation is larger than the LO-IF isolation by at least 20 dB, whose property (compared with the conventional mixer under the same leaked frequency) is very suitable for super heterodyne receivers to reduce the impact on LO leakage. Moreover, even though the proposed FEHM is adopted in direct conversion receivers, the LO leakage can be well cancelled by an LPF and will not influence the baseband circuit. Therefore,


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Fig. 16. Measured results of the down-converted IF frequency versus the conversion gain and NF. Fig. 15.

Measurement of the isolation.

Fig. 15 shows that 2LO-IF isolation with 50.2 dB and LO-IF isolation with 18.87 dB are obtained under the 3.6-dBm LO power. The differential isolations from LO port to port 1 are also measured by scanning the LO power and shown in Fig. 15. As the LO power of 3.6 dBm is used, the 2LO-RF isolation with 64.7 dB and LO-RF isolation with 32.8 dB are obtained. Over the sweep, the proposed FEHM can get 2LO-RF isolation better than LO-RF isolation by at least 26 dB. In other words, even though all double-frequency leaked signals are all reflected by previous LNA, the proposed FEHM could still improve the dc offset by at least 26 dB. In order to quantify the influence of the time-varying dc offset, the equivalent RF input signal voltage can be employed as a measure of self-mixing as [10] (28) is the leaked LO signal voltage, is the rewhere and flection factor at the LNA output port, and both are the conversion gains of the mixer from RF and LO signal frequency to baseband, respectively. If the LO input of 36.4 dBm and the general power of 3.6 dBm with 14 dB are used [10], of 89.29 dBm is meacase of 30 dB. Therefore, from sured by the worst port 1 to IF port (as shown in Fig. 9) can be isolated by the proposed FEHM to reduce the impact on the time-varying dc offset. After sweeping the RF frequency, the IF frequency versus conversion gain and noise figure are shown in Fig. 16. Apparently, there will be an acceptable flicker noise corner around 500 kHz. For noise figure property, there will be an optimal value at an IF frequency of 5 MHz. As for conversion gain, it reaches a maximum value at an IF frequency of 500 kHz, which is very useful for direct conversion receivers for high-gain applications. Therefore, both conversion gain and noise figure are tradeoffs and are functions of the chosen IF output frequency. In conclusion, the measured results agreed with our theoretical studies. The only drawback of the proposed FEHM is the sensitivity of noise figure to the chosen IF output frequency. However, this problem can be solved either by shifting the IF output frequency to several megahertz or by employing a highgain LNA before the proposed FEHM.

Fig. 17. Measurement of RF power versus conversion gain, where the simulated result is the same configuration as before and uses the resistor-tuning network.

C. Measurement for Linear Improvement of the FEHM Owing to process variations and unmatched bonding-wire is obtained. In order to length, the small 17.32-dBm solve this problem, the resistor-tuning network is adopted from the outside to improve the linearity, as shown in Fig. 8. The and cannot be resistor-tuning network using too small, otherwise the conversion gain will be degraded seriously. Moreover, the resistor-tuning network can improve the circuit asymmetry by adjusting the output load of the current reuse circuit pair with the appropriate values to overcome the process variation. Hence, an off-chip 10-k variable resistor ) and an off-chip 1-k resistor (instead (instead of ) are employed. On the other hand, to optimize of the linear performance, we tune the bias to 0.424 V and to 0.453 V with 5.5-dBm LO power under 0.9-V supply voltage. We achieve 8.3-dB conversion gain with 15 dBm (shown in Fig. 17), 24.5-dB noise figure (with the flicker corner around 500 kHz), and 4.95-mW power consumption. and measurements at a down-converted center For frequency of 500 kHz with 100-kHz spacing shown in Fig. 18, with 18.07 dBm, with 75.64 dBm, and we obtain with 70.87 dBm. Hence, 31.2-dBm and 0.03-dBm are measured at the 8.3-dB conversion gain. As for isolation, 2LO-IF isolation with 43 dB, LO-IF isolation with 19 dB, 2LO-RF isolation with 58 dB, and LO-RF isolation with 33 dB are also measured.

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our design with pure CMOS process exhibits low power consumption, higher operational frequency, acceptable power con, and linearity ( , and ). Note version gain that the lower conversion gain is resulted from the operation frequency of the RF input signal [25]. Therefore, the proposed FEHM is suitable for low-voltage 5.25-GHz applications. IV. CONCLUSION

Fig. 18. Measured results of the resistor-tuning network.

IIP

and

IIP

performances with

TABLE II SUMMARY OF THE COMPARISON

In this paper, we proposed an FEHM with folded technique for low-voltage applications. The mathematical expressions for linearity, conversion gain, and noise figure using Taylor’s series expansion are described and verified by experimental data. Measured results show that the proposed FEHM achieves the goals of low supply voltage, large conversion gain, low complexity, and high operational frequency. Hence, the proposed even harmonic mixer with folded technique is suitable for low-voltage and high-frequency applications such as heterodyne receivers and direct conversion receivers. ACKNOWLEDGMENT The authors thank the anonymous reviewers for the valuable comments in improving the quality of this study. REFERENCES

Fig. 19.

Photomicrograph of the proposed FEHM chip.

Finally, comparisons with other recently published results are shown in Table II, and the chip photomicrograph is shown in Fig. 19. Apparently, under the lowest supply voltage of 0.9 V,

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Ming-Feng Huang was born in Kaohsiung, Taiwan, R.O.C., in 1977. He received the B.S. degree from the Yunlin University of Science and Technology, Yunlin, Taiwan, R.O.C., in 2001, the M.S. degree from the Institute of Electrical Engineering, National Chung-Cheng University, Chia-Yi, Taiwan, R.O.C., in 2002, and is currently working toward the Ph.D. degree at the Institute of Electrical Engineering, National Chung-Cheng University. He is currently involved with RF front-end transceiver design for low-power applications. His research interest is the low-power design for active RFICs.

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Chung J. Kuo (S’88–M’90–SM’00) received the B.S. and M.S. degrees in power mechanical engineering from National Tsing Hua University, Tsing Hua, Taiwan, R.O.C., in 1982 and 1984, respectively, and the Ph.D. degree in electrical engineering from Michigan State University (MSU), East Lansing, in 1990. In 1990, he joined the Electrical Engineering Department, National Chung-Cheng University (NCCU), Chia-Yi, Taiwan, R.O.C., as an Associate Professor and then became a Full Professor in 1996. From 1999 to 2002, he was the Chairman of the Graduate Institute of Communications Engineering, NCCU. In 1991, he was a Visiting Scientist with the Opto-Electronics and System Laboratory, Industrial Technology Research Institute. From 1997 to 1998, he was with the IBM T. J. Watson Research Center and a consultant to several international/local companies. From 2003 to 2004, he was the Director of the Research and Development Center of Components Business Group (CPBG), Delta Electronics Inc. In 2004, he became the Senior Director of Magnetics and Microwave Business Unit, CPBG, Delta Electronics Inc. He is the Codirector of the Signal and Media (SAM) Laboratories, NCCU. His interests are image/video signal processing, very large scale integration (VLSI) signal processing, and photonics. He was a Guest Editor for three special sections of Optical Engineering and 3D Holographic Imaging (to be published by Wiley). He is listed in Who’s Who in the World. Dr. Kuo is a member of the Optical Society of America, The International Society for Optical Engineers (SPIE), Phi Kappa Phi, and Phi Beta Delta. He was an invited speaker and Program Committee chairman/member for several international/local conferences. He serves as an associate editor for the IEEE Signal Processing Magazine. He was president of SPIE Taiwan Chapter (1998–2000). He was the recipient of the 1998 Distinguished Research Award presented by the National Chung-Cheng University, the 1997 Overseas Research Fellowship presented by the National Science Council (NSC), the 1997 Outstanding Research Award presented by the College of Engineering, NCCU, the 1995 Medal of Honor presented by NCCU, the Research Award presented by NSC for a consecutive 11 times, the 1989 Electrical Engineering Fellowship presented by MSU, and the 1987 Outstanding Academic Achievement Award presented by MSU.

Shuenn-Yuh Lee (M’98) was born in Taichung, Taiwan, R.O.C., in 1966. He received the B.S. degree from National Taiwan Ocean University, Chilung, Taiwan, R.O.C., in 1988, and the M.S. and Ph.D. degrees from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1994 and 1999, respectively. Since 2002, he has been an Assistant Professor with the Institute of Electrical Engineering, National Chung-Cheng University, Chia-Yi, Taiwan, R.O.C. His current research activities involve the design of analog- and mixed-signal integrated circuits including filters, high-speed ADCs/DACs, and sigma–delta ADCs/DACs, biomedical circuits and systems, low-power and low-voltage analog circuits, and RF front-end integrated circuits for wireless communications. Dr. Lee is a member of the IEEE Circuits and Systems Society and the IEEE Solid-State Circuits Society.