A 5.8-GHz ETC Transceiver Using SiGe-BiCMOS

IEICE TRANS. ELECTRON., VOL.E90–C, NO.9 SEPTEMBER 2007

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PAPER

Special Section on Microwave and Millimeter-Wave Technology

A 5.8-GHz ETC Transceiver Using SiGe-BiCMOS Minoru NAGATA†a) , Hideaki MASUOKA† , Shin-ichi FUKASE† , Makoto KIKUTA†† , Makoto MORITA†† , Nonmembers, and Nobuyuki ITOH† , Member

SUMMARY A fully integrated 5.8 GHz ETC transceiver LSI has been developed. The transceiver consists of LNA, down-conversion MIX, ASK detector, ASK modulator, DA VCO, and ∆Σ-fractional-N PLL. The features of the transceiver are integrated matching circuitry for LNA input and for DA output, ASK modulator with VGA for local signal control to avoid local leakage and to keep suitable modulation index, and LO circuitry consisting of ∆Σ-fractional-N PLL and interference-robust ∞-shape inductor VCO to diminish magnetic coupling from any other circuitry. Use of these techniques enabled realization of the input and output VSWR of less than 1.25, modulation index of over 95%, and enough qualified TX signals. This transceiver was manufactured by 1P3M SiGe-BiCMOS process with 47 GHz cut-off frequency. key words: ETC transceiver, internal matching circuits, ASK modulator, ∞-shape inductor VCO

1.

Fig. 1

Introduction

Recently, vehicle-related radio communication, such as communication inside a vehicle, between vehicles, and between a vehicle and a road, has been gaining popularity. In particular, dedicated short range communication (DSRC) systems have been gradually entering service in Japan and similar IEEE 802.11p radio systems are expected to be widely implemented worldwide in the near future. Among the various DSRC systems, electronic toll collection (ETC) systems, using 5.8 GHz DSRC band and ASK modulation, have been widely introduced in Japan [1], and since electronic account settlement using ETC systems is available for many toll roads, many cars are being equipped with ETC terminals. Given that downsizing and cost-effectiveness are important requirements for ETC terminals, a fully integrated RF transceiver LSI has been required in order to minimize the number of external components and ensure ease of use. It is in this context that an RF LSI is presented in this paper. The block diagram of the developed LSI is shown in Fig. 1. The reception part of the LSI consists of a low noise amplifier (LNA), a down-conversion mixer (MIX) and an ASK detector. Input 5.8 GHz signal is amplified by LNA and down-converted to 40 MHz IF signal by the following down-conversion mixer, and then the down-converted signal is amplified by the IF amplifier and its signal level is deManuscript received February 5, 2007. Manuscript revised April 13, 2007. † The authors are with Semiconductor Company, Toshiba Corp., Yokohama-shi, 247-8585 Japan. †† The authors are with Toshiba Microelectronics Corp., Kawasaki-shi, 210-8538 Japan. a) E-mail: [email protected] DOI: 10.1093/ietele/e90–c.9.1721

Block diagram of ETC transceiver.

tected by RSSI (Radio Signal Strength Indicator) and is demodulated to 1024 kbps bitstream signal by the ASK detector. The transmitter part consists of a roll-off filter, the ASK modulator and a driver amplifier (DA). The input bitstream data from baseband LSI is directly modulated to 5.8 GHz RF signal by the ASK modulator. The local part consists of a fully integrated voltage controlled oscillator (VCO), a frequency doubler and ∆Σ-Fractional-N PLL to generate 5.8 GHz local signal. To avoid injection pulling, VCO oscillates at half of carrier frequency, 2.9 GHz, and 5.8 GHz local signal is generated by the frequency doubler. In order to realize an easy-to-use high-frequency RFLSI, RF-LSI has to be designed with certain features. The features of our transceiver include integrated matching circuitry for LNA input and for DA output, ASK modulator with VGA for local signal control to avoid local leakage and to keep suitable modulation index, and LO circuitry consisting of ∆Σ-fractional-N PLL and interference-robust ∞-shape inductor VCO to diminish magnetic coupling from any other circuitry. 2.

Building Blocks

2.1 Integrated Input Matching Circuitry In many cases, integrated RF LSIs are mounted on generalpurpose packages. However, in the case of LSI operating in the frequency range up to 5.8 GHz band, it is difficult to adjust on-board matching conditions of RF terminals since the effects of parasitic capacitances and parasitic inductances both inside of chip and outside of chip become

c 2007 The Institute of Electronics, Information and Communication Engineers Copyright


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significant. For ease of use, on-board matching free RF-LSI is required. In order to realize on-board matching free RFLSI, we adopted integrated matching circuitry for inside of chip and pseudo-coplanar ground-signal-ground (GSG) line for outside of chip. The equivalent circuit of LNA with external matching circuitry is shown in Fig. 2(a). In the case of off-chip matching, the base terminal and the emitter terminal of the transistor are connected directly to the terminal of the LSI chip. Hence, these terminals are very sensitive to the effect of parasitic elements such as the internal and the external parasitic capacitances, Cpi and Cpx , and the internal and the external parasitic inductances, Lpi and Lpx . In this case, Cpi and Cpx are connected to the base terminal of Q1 , and Lpi and Lpx are connected to the emitter terminal of Q1 . Figure 2(b) shows simulation results for the effect of total parasitic ca-

(a)

(b)

pacitance, Cpx +Cpi , and total parasitic inductance, Lpx + Lpi . Input impedance matching is strongly influenced by values of parasitic components, Cpx + Cpi and Lpx + Lpi . Generally, the values of the internal parasitic elements are obviously smaller than that of external parasitic elements due to their smaller dimensions. Moreover, it is possible to reduce the values of the internal parasitic elements by layout design efforts. On the other hand, it is difficult to reduce the values of the external parasitic elements. As a result, the dominant part of parasitic elements is the external one and it is difficult to adjust proper impedance matching. To avoid these difficulties, we integrated the on-chip matching circuits in order to dispense with matching devices on the RF module board. The equivalent circuits of LNA including on-chip matching circuit of RX input terminal is shown in Fig. 2(c). In this case, there are process variations of internal matching components. But they affect the matching condition slightly, because the tolerances of the matching components, C and L, are varied within 10% and 1%, respectively, and frequency response of the matching circuits is approximately proportional to the square root of each component’s tolerance. Although the internal matching seems complete using this matching methodology, it is imperfect because bond wires and lead frame of LSI package exist between the RF terminal of LSI chip (matching to 50 Ω) and on-board transmission line (also matching to 50 Ω). Ideally the characteristic impedances of the bond wires part as a transmission line and the lead frame part as a transmission line would be 50 Ω, but this is impossible using general-purpose packages or the conventional mounting methods. A GSG (ground-signalground) structure of the RF signal transmutation line shown in Fig. 3 was adopted so that the characteristic impedance of connecting parts would approach 50 Ω. Existing unclear characteristic impedance parts were the bond wire part and the frame of the package part. Estimated characteristic impedance of the bond wire part was approximately 200 Ω, and that of the lead frame part was approximately 50 to 70 Ω. But their electronic length was about 3 mm

(c)

Fig. 2 (a) Equivalent circuits of LNA input with external matching circuits. (b) Simulated input matching depends on parasitic capacitances and parasitic inductances. (c) Equivalent circuits of LNA input with integrated matching circuits.

Fig. 3

RF signal input/output interface between board and LSI chip.

NAGATA et al.: A 5.8-GHz ETC TRANSCEIVER USING SiGe-BiCMOS

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(a) (a)

(b)

(c)

(b) Fig. 4 (a) Equivalent circuits of on-chip DA with external output matching circuits. (b) Simulated output matching influenced by parasitic capacitances. (c) Equivalent circuits of DA with integrated matching circuits.

(about λ/16 at 5.8 GHz). So, the influence of those parts is slight in terms of overall matching conditions. Therefore, stable matching characteristics can be obtained and external matching elements can be eliminated. 2.2 Integrated Output Matching Circuitry The integrated output matching circuits are also adopted in the same manner as LNA input matching. Figure 4(a) shows equivalent circuit of the DA output part with external matching circuits. The internal parasitic capacitance is Cpi , and the external one is Cpx . Also, the matching circuits consisted of C2 , L2 , and L3 . The influence of total parasitic capacitance, Cpx + Cpi , was large for output matching as shown in Fig. 4(b), and also Cpi is generally smaller and more controllable than Cpx . Hence we adopted integrated matching circuitry as shown in Fig. 4(c). 2.3 ASK Modulator For the transmitter part, we selected a direct modulation system that modulates using 5.8 GHz local signals directly. In the case of direct modulator, the frequencies of local and transmit signals are identical and sometimes local leakage

Fig. 5 (a) Equivalent circuit of double balanced mixer for ASK modulator. (b) Simulated output wave form of double balanced mixer.

is a problem at higher operating frequency such as 5.8 GHz. There are two candidates for modulator topology, double balanced mixers (DBM) and single balanced mixers (SBM). Equivalent circuit of DBM and simulated results of ASK modulation using DBM, in the case of 100 MHz and 5.8 GHz local frequencies, are shown in Figs. 5(a) and 5(b), respectively. From the result in Fig. 5(b), it is clear that when RF frequency is lower, such as 100 MHz, modulated RF output signal is translated exactly. On the other hand, when RF frequency is 5.8 GHz, local leakage to modulated signal output is remarkable. As a result of this local leakage, modulation index is significantly lower. The local leakage as shown in Fig. 5(a) originates from the base-collector parasitic capacitance of the differential pair. This parasitic capacitance behaves like a local signal leak path. Moreover, since the output level is minimized using DBM, RF signal should be canceled between the left differential pair “A” and the right differential pair “B” in Fig. 5(a). Therefore, differential pair balance between “A” and “B” is very important for minimizing local leakage; however, it is rather difficult to maintain a balance for 5.8 GHz signal. Therefore, we chose a modulator structure based on a single balanced mixer (SBM). As output level is minimized, the current of the SBM


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differential pair is also minimized. Then SBM ensures no balance problem arises. Hence, it is supposed that local leakage is reduced by using SBM. However, in the case of using SBM topology for ASK modulator, the collector current, IC , of the differential pair of SBM is proportional to amplitude of modulation signal even if local signal amplitude is constant. It indicates equivalent input capacitance, Cπ , of the differential pair is also proportional to amplitude of modulation signal since input capacitance of bipolar transistor, Cπ , is generally proportional to its collector current as expressed in Eq. (1). C π = τF

qIC qIC + Cje ≈ τF kT kT

(a)

(1)

Practically, in the case that the modulation signal is large, input capacitance Cπ of local signal input terminal of SBM increases and its input impedance becomes low. As a result, the local signal amplitude becomes small; hence modulation linearity becomes worse. On the other hand, in the case that the modulation signal is small, Cπ of local signal input terminal of SBM decreases and its input impedance becomes high. As a result, local signal amplitude becomes too large; hence the local leakage may increase. These considerations indicate the balance between the modulation signal and the local signal is very important for realizing fine ASK modulator. In order to keep modulation linearity and decrease local leakage, we adopted variable gain amplifier (VGA) for the previous stage of the modulator’s local input terminal and its gain is controlled by the modulation data as shown in Fig. 6(a). The simulated local signal pre-amplifier gain difference between fixed-gain amplifier and variable gain amplifier as dependence on modulation signal amplitude is shown in Fig. 6(b). In the case of using fixed-gain amplifier, amplifier gain decreases as modulation signal amplitude increases. On the other hand, in the case of using VGA, amplifier gain is proportional to modulation signal amplitude. And that is also proportional to the ASK-Modulator gain.

(b) Fig. 6 (a) Equivalent circuits of ASK modulator. (b) Simulated preamplifier gain difference between fixed-gain amplifier and variable gain amplifier as dependence on modulation signal amplitude.

2.4 ∞-Shape VCO and ∆Σ-PLL For generating RF local signals for ASK modulator and for down-converter, 5.8 GHz band VCO and PLL are also integrated. VCO oscillates at half of carrier frequency, 2.9 GHz, and 5.8 GHz local signal is generated by the following frequency doubler. As VCO block is very sensitive to the outer noises, power supply and ground terminals of VCO were completely separated from those terminals of other circuit blocks and oscillator’s core parts were completely enclosed by guard ring. Of course, these measures were effective for reducing electrical and capacitive coupling to other circuits but ineffective in terms of reducing the influence of magnetic coupling on the resonant coil. In particular, during transmission of ASK signal, output stages of transmit blocks were switched on and were switched off by modulation signal. Hence, matching inductor placed at the transmit

Fig. 7

VCO structure.

output section scatters the magnetic fields. Also, if resonant inductor of VCO were affected by this magnetic field, self-modulation would occur, causing spur characteristics of transmit signal to deteriorate. In view of this background, we selected the ∞-shape resonant inductor to diminish magnetic coupling between VCO resonant inductor and others. The structure of VCO is shown in Fig. 7. The magnetic field generated by the outer noise sources passes through all loops


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of the ∞-shape coil in the same direction. Voltages at loops caused by these magnetic fields are generated in opposite directions in the ∞-shape coil, thereby canceling each other. Therefore, use of the ∞-shape coil reduces the influence of magnetic interferences. In the Japanese DSRC band standard used by ETC systems, frequencies of RF channels are set at integer times multiple as large as 5 MHz. On the other hand, since symbol rate of modulation signal is set to 1.024 Mbps, the clock frequency of almost all baseband processors is set to the integer times multiple as large as 1.024 MHz, for instance 16.384 MHz. In order to operate the ETC terminal with only one reference frequency, this reference clock must be used as a reference frequency of PLL. However, to generate RF carrier whose frequency is integer times multiple as large as 5 MHz, reference frequency of PLL is reduced to their greatest common divisor, such as 8 kHz. However, RF channel switching time of less than 100 µsec is required. It is difficult to achieve such a short switching time by such a low reference frequency using integer PLL. In view of these considerations, we chose ∆Σ-fractional N PLL to achieve both requirements. 3.

Fabrication and Measurements

The manufacturing process was SiGe-BiCMOS process including SiGe npn transistors, Si npn transistors, L-pnp transistors, CMOS with two types of threshold voltages for both NMOS and PMOS, two types of resistors, MIM capacitor, and 3-µm-thick top metal layer for high-Q on-chip spiral inductor. fT max of SiGe npn transistor was 47 GHz. Almost all electronic characteristics were measured for a packaged sample under 3.0 V supply voltage. A photograph of the RF transceiver LSI on the evaluation board is shown in Fig. 8. The signal line of the board was a coplanar line as shown in Fig. 8. The signal line of RX input is a single line and that of TX output is a differential line. No matching devices are required on the board.

Fig. 8 ETC LSI on the evaluation board. No matching devices are required.

3.1 Integrated Input Matching Circuitry The final layout photograph of the LNA input part is shown in Fig. 9(a). The number of elements in Fig. 9(a) corresponds to that of the equivalent circuits in Fig. 2(c). In this case, L1 = 2.3 nH, L2 = 1.5 nH, L3 = 2.1 nH, and C1 = 1.2 pF, respectively. In order to minimize parasitic capacitance, Cp , and parasitic inductance, Lp , the distance between emitter terminal of Q1 and ground and that between base terminal of Q1 and L2 were controlled to be as small as possible. Measured reflection coefficient, s11 , of the LNA input terminal on this evaluation board is shown in Fig. 9(b). The voltage standing wave ratio (VSWR) is below 1.25 at 5.8 GHz band without any external matching elements. This result indicates on-chip matching circuitry of LNA input works correctly. 3.2 Integrated Output Matching Circuitry The final layout photograph of the DA output part is shown in Fig. 10(a). The number of elements in Fig. 10(a) corresponds to that of equivalent circuits in Fig. 4(c). In this case, L1 = 4.5 nH, L2 = 1.35 nH, L3 = 2.7 nH, C1 = 4.0 pF, and C2 = 0.38 pF, respectively. In order to minimize parasitic capacitance, Cp , the distance between collector terminal of npn transistor and L2 was controlled to be as small as possible. Measured reflection coefficient, s22 , of the DA output terminal on this evaluation board is shown in Fig. 10(b). The VSWR is below 1.25 at 5.8 GHz band without any external matching elements. This result indicates on-chip matching circuitry of DA output works correctly.

Fig. 9 (a) Layout photograph of LNA input part. (b) Measured reflection coefficient of LNA input terminal.


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Fig. 12 (a) Layout photograph of VCO. (b) Measured phase noise as a function of offset frequency from carrier.

Fig. 10 (a) Layout photograph of DA output part. (b) Measured reflection coefficient of DA output terminal.

Fig. 11

Fig. 13

Measured eye-diagram of ASK modulated TX signal.

The CW spectrum of VCO controlled by ∆Σ fractional-N PLL.

3.3 ASK Modulator

3.4 ∞-Shape VCO and ∆Σ-PLL

Figure 11 shows the measured eye diagram of ASK modulated RF output’s signal level. Observed local leakage level, which is carried out from Vmin value, is very small. It is determined that the modulation index, M, as defined in Eq. (2) is over 95%. This result is a very high index value for an on-chip modulator.

The final layout of VCO circuit is shown in Fig. 12(a). Care was taken to ensure the symmetry of the layout. Inductor was completely stacked as shown in Fig. 7 and the magnetic connection was available between the third-layer metal and the second-layer metal. The measurement data of phase noise of VCO is shown in Fig. 12(b). The phase noise at 1 MHz offset from carrier was −121 dBc/Hz. The CW spectrum of VCO controlled by ∆Σ fractionalN PLL is shown in Fig. 13. No conspicuous fractional noise

M=

Vmax − Vmin Vmax + Vmin

(2)


1727 Table 1

Fig. 14

The microphotograph of the RF transceiver LSI chip.

is observed and no spur is observed, either. 3.5 Transceiver Performances Typical electronic characteristics of the developed LSI are shown in Table 1. TX output level was −5 dBm in typical conditions, modulation index is over 95%, ACPR was 40 dBc in the case of 5 MHz offset from carrier, RX sensitivity was −80 dBm with BER of less than 0.001%, and current consumption of both TX and RX were 40 mA, respectively, under 3.0 V power supply. The operating temperature range was −40 to 85 degrees centigrade, and the operating temperature range required for automobile applications was achieved. The package was standard 48-pin QFP package. The microphotograph of the RF transceiver LSI chip is shown in Fig. 14. 4.

Table 2

Electronic characteristic.

Conclusion

A fully integrated 5.8 GHz ETC transceiver LSI was developed. The transceiver consists of LNA, down-conversion MIX, and ASK detector for RX chain; ASK modulator and DA for TX chain; and VCO and ∆Σ-fractional-N PLL for LO chain. This transceiver realized on-chip fully integrated matching circuits for LNA input and DA output and their measured VSWR was less than 1.25 for both terminals. The

Comparison with other works.

ASK modulator realized SBM with LO signal controlled by VGA to avoid local leakage and to keep suitable modulation index. The measured modulation index was over 95%. LO circuits were also realized with ∞-shape inductor VCO and ∆Σ-fractional-N PLL. No conspicuous fractional noise and no spurious were observed. The RX sensitivity was −80 dBm under BER of less than 0.001% and current consumption of TX and RX was 40 mA under 3.0 V power supply. Data from previous works on ETC transceiver are compared in Table 2. Acknowledgments The authors would like to thank Mr. H. Aoki and Mr. H. Saito for encouragement in this work. References [1] Japanese Ministry of Land, Infrastructure, and Transport, Road Burreau. Introduction about Japanese elecrtonic toll collection system. Online at: http://www.mlit.go.jp/road/ITS/ [2] T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanha, Y. Takeuchi, H. Shimamoto, T. Nagashima, and K. Washio, “Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS,” Digest of Technical Papers of ISSCC, pp.96–97, Feb. 2002. [3] S. Shinjo, K. Tsutsumi, K. Nakajima, H. Ueda, K. Mori, M. Hieda, J. Koide, M. Inoue, and N. Suematsu, “5.8 GHz ETC SiGe-MMIC transceiver having improved PA-VCO isolation with thin silicon substrate,” Digest of IEEE MTT-S International Microwave Symposium 2006 (IMS-2006), pp.2039–2042, June 2006. [4] M. Nagata, H. Masuoka, S. Fukase, M. Kikuta, M. Morita, and N. Itoh, “5.8 GHz RF transceiver LSI including on-chip matching circuits,” Proc. 2006 IEEE Bipolar Circuit and Technology Meeting, pp.263–266, Maastricht, The Netherland, Oct. 2006.


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Minoru Nagata was born in Fukuoka, Japan in 1957. He received B.E. and M.E. degrees in electrical engineering from Kyushu University, Fukuoka, Japan, in 1980 and 1982, respectively. In 1982, he joined the Audio and Video Engineering Laboratory, Toshiba Corporation, Yokohama, Japan, where he was engaged in the circuit designing for bipolar LSI’s especially for high speed signal processing LSI’s for DBS receiver and UHF TV tuners. Since 1999, he has been engaged in the development of the highspeed signal processing circuits for wireless telecommunication systems at Semiconductor Company of Toshiba Corporation, Yokohama, Japan. His current interests are high-frequency analog circuits design.

Hideaki Masuoka received B.E. and M.E. degrees in electronics from Nagoya Institute of Technology, Nagoya, Japan, in 1983 and 1985, respectively. In 1985, he joined Semiconductor Division, Toshiba Corporation, Kawasaki, Japan, where he was engaged in the circuit designing for high-frequency circuits. His current interests are PLL design for telecommunication LSIs.

Shin-ichi Fukase was born in Hokkaido, Japan, in 1962. He received B.E. and M.E. degrees in electrical engineering from Shinshu University, Nagano, Japan, in 1985 and 1987, respectively. In 1987, he joined the Fukaya factory, Toshiba Corporation, Fukaya, Japan, where he was engaged in the circuit designing for CMOS LSIs especially for servo driver. Since 1995, he has been engaged in the development of the high-frequency and high-speed integrated circuits for wireless telecommunication systems at Semiconductor Company of Toshiba Corporation, Yokohama, Japan. His current interests are high-frequency and low-noise PLL synthesizer design for telecommunication systems.

Makoto Kikuta was born in Kita-Kyushu, Japan, in 1971. He received B.E. in mechanical engineering from College of Technology, Daiichi University, Kagoshima, Japan, in 1993. He joined Toshiba Microelectronics Corporation in 1993, Kawasaki, Japan, where he was engaged in the development of analog communication LSIs. His current interests are RF analog integrated circuits for telecommunications.

Makoto Morita was born in Yokohama, Japan, in 1968. He received B.E. in electrical engineering from College of Technology, Nihon University, Koriyama, Japan. He joined Toshiba AVE Corporation in 1992, Yokohama, Japan, where he was engaged in the circuit designing for bipolar LSI’s for audio and visual applications. Since 2000, he has been engaged in the high-frequency analog circuits design in Toshiba Microelectronics Corporation, Kawasaki, Japan. His current interests are high-frequency analog circuits design.

Nobuyuki Itoh was born in Tokyo, Japan, in 1960. He received B.S. and M.S. degrees in chemistry from Tokyo University of Science, Tokyo, Japan, in 1983 and 1985 respectively, and he received Ph.D. degree in physical electronics from Tokyo Institute of Technology, Tokyo, Japan, in 2006. In 1985, he joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan, where he was engaged in the research and development of CMOS device technologies for advanced CMOS gate arrays, bipolar device technologies and bipolar circuit design for ECL gate arrays and high-frequency analog circuits, and RFCMOS circuit design. He had been visiting scientist at Katholieke Universiteit Leuven, ESAT-MICAS, Leuven, Belgium, from March of 1996 to April of 1998 where he had worked on design of fully integrated VCOs and PLLs using RF-CMOS. He has been engaged in the research and development of high-frequency analog circuit at Semiconductor Company of Toshiba Corporation since 1998. His current research interests are highfrequency integrated circuit for telecommunications. Dr. Itoh is a member of the Institute of Electrical and Electronics Engineers, Inc (IEEE), and currently he is a member of the officers of Japan Chapter of IEEE MTT-S. He is also a member of program committee of Custom Integrated Circuit Conference (CICC), Bipolar/BiCMOS Circuit and Technology Meeting (BCTM) and European Solid-State Circuits Research Conference (ESSCIRC).