A 60GHz, Linear, Direct Down-Conversion Mixer with mm-Wave Tunability in 32nm CMOS SOI M. A. T. Sanduleanu1, A. Valdes-Garcia1, Y. Liu1, B. Parker1, Shlomo Shlafman2, Benny Sheinman2, Danny Elad2, Scott Reynolds1 and Daniel Friedman1 1 IBM T. J. Watson Research Center, Yorktown Heights, NY, USA email:
[email protected] 2 IBM Haifa R&D, Mount Carmel, Haifa, Israel Abstract- The gain/linearity trade-off is exploited to achieve the best linearity performance of a mm-Wave down-conversion system. The achieved linearity (IIP3) for the whole downconversion chain is better than 11.06dBm for 5.8dB gain at 60GHz. Gain can be adjusted from -15dB to 11dB in 1dB steps depending on the signal level. By adjusting phase matching at RF input and the common-mode impedance of the mixer with a variable transmission line, the input phase imbalance can be corrected and the second-order distortion (HD2) can be reduced. The LO/RF isolation is 43dB and the LO/IF isolation is better than 82dB. The down-converter occupies 1.38mm2 in 32nm CMOS SOI and consumes 19.2mW from 1V supply. The power consumption of the mixer itself is 4mW @ 1V supply.
I. INTRODUCTION For phased-array receivers, in addition to the beamsteering capability, one well known advantage over individual single-channel receivers is the improvement of the SNR [1]. Whether it adopts a power combiner or an amplitude combiner, a phased-array receiver does not improve the noise factor (or noise figure) from an individual array channel, but shows the same noise factor (or noise figure). Although the noise figure remains unchanged, the output SNR (SNRN) increases by a factor of N (array size) in the array receiver SNRN=N*SNR1. In a homodyne or a super-heterodyne phased-array receiver with many elements (N), after RF power combining, the mixer has to handle very large signals at its input. This then, requires extremely high values for the IIP3 and 1-dB compression of the total down-conversion chain. As the combined signal for a phased-array system with many elements is already large, one can trade off the noise figure of the mixer function for better linearity. The paper presents a linear direct down-conversion system with integrated sensors and digital infrastructure. The high linearity of the mixer cell is facilitated by a novel linearization method without penalty on extra voltage headroom. As the linearity and the input impedance are virtually decoupled from each other, the differential impedance can be optimized to match a large range of different signal sources. The LO is applied single-ended and switches on and off the transconductor pair. It allows low voltage operation and large swing at the output nodes. Key for operation is the gain/linearity trade-off. The load of the mixer, as well the following VGA stage, have variable gain. For a given signal level, gain is adjusted for best linearity. The price paid for linearity is the worsening of the NF compared to a double balanced Gilbert cell.
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Fig. 1. Mixer architecture with digital infrastructure and tunable T-Line.
II. Down-Conversion Mixer Architecture Fig. 1 shows a block diagram for the implemented 60 GHz down-conversion system. At the input, the matching circuits use a variable transmission line (T-line) as an adjustable stub. In order to reduce the input common-mode, the phase difference between the two differential inputs ( ideally 180°) can be adjusted, thus maximizing the fundamental component. The T-Line has fixed side shields, a ground plane and a switchable capacitance layer in form of a grating structure connected either to ground or left floating [2]. The grating layer is divided in sections, individually controlled using MOS switches. The common-mode impedance of the mixer is tunable as well, by using the same variable T-Line structure. The mixer is followed by a VGA and a buffer with 50Ω output impedance. The power gain of the mixer/VGA tandem is adjustable from -15dB to +11dB in small steps of 1dB. The gain of the VGA is distributed over two stages and for the same power gain, the gain distribution setting can be found for the best linearity performance. A peak detector incorporated in the mixer itself, correlates the signal level with linearity performance and is used as a linearity sensor. The offset adjustment, nulls the dc difference between the two differential outputs of the mixer mitigating the effect of even order distortion components. It prevents, as well, saturation of the VGA stages in high gain mode. An 8-bit microcontroller and a 6-bit SAR ADC are integrated in the system. These components were not employed for the measurements presented in this work but could be employed for closed-loop, on-chip calibration. For measurement purposes the internal registers of the actuators (gain, bias controls, and tunable t-lines) are programmed from an on-chip serial interface.
Fig. 3. VGA2 circuit diagram.
Fig. 2. Circuit diagram: mixer, amp-sensor and VGA.
III. Circuit Implementation Fig.2 shows the circuit diagram of the mixer and the first stage of the VGA (VGA1). The input stage including M1...M4 together with the impedance Z1 provides simultaneous input matching and linearization. For small input differential signals, the gates of M3/M4 and their source are virtual ground and no signal flows at their drains. At large signal levels, the source of M1...M4 is not anymore virtual ground and the distortion components will flow in M3/M4 transistors. The impedance Z1 consists of a transmission line in series with a 10Ω resistor. The crux of the linearization technique is the decoupling between input matching and linearity (the linear range does not depend on the choice of Z1). Moreover, this technique does not require extra voltage headroom when compared to a simple differential pair. Hence, the drain of the input pair could have larger voltage swing. The commonmode impedance is realized with a resistor, two fixed transmission lines and a variable T-Line acting as an adjustable capacitance stub. The common-mode current of the linearized pair, flows in M7...M10. The LO transistor M11 switches ON/OFF the linearized pair without the need of extra voltage headroom like in a Gilbert mixer. The differential current flows through two adjustable resistors R1 connected in series. This then, generates an input voltage for the first VGA stage (VGA1) with M5, M12, M13 and M6. The output load of VGA1 is adjustable as well. The IF output is applied to a second gain stage (VGA2) with a gain control range from -6dB to +6dB in 1dB fine steps. VGA1 provides an extra 10dB of gain for the IF chain. The gate of M10 is connected to an offset control signal (OFFSET) generated after measuring the offset at the output of VGA2. The drain current of the middle transistors in VGA1 is lowpass filtered with R3, C3 and the resulting voltage is a measure of the input amplitude applied to VGA1. The second VGA is shown in Fig.3. It consists of a super source follower stage M1...M6, a peaking load R1, C1 and an output stage M9...M12 with extra gain adjustment. The current IBIAS is forced in the transistors M1 and M2, facilitated by a local feedback loop with M5, R2, M3 and M6, R2, M4. As the gate-source voltages of M1 and M2 are constant the input
differential voltage applied between IN+ and IN- will be amplified with a voltage gain of 1 at the gain peaking load R1||C1. A tunable capacitor C1, realized as a switching network of capacitors, provides high frequency peaking for the V/I converter bandwidth control. The PMOS transistors M5 and M6 are dc level shifters and are bypassed by capacitors C2 at higher frequencies. The current in M7, M8 is an amplified replica (factor M) of the current flowing in M3, M4 and R1||C1. The DAC controls the amount of current flowing to the OUT+ and OUT- nodes in the differential pair M9, M11 and M12, M10. For low gain, most of the current is dumped to VDD (M9 and M10 are completely open). IV. Measurements Results The down-converter implemented in a 32nm CMOS SOI process from IBM consumes 19.2mW (RF+analog+digital) from a 1V power supply. The mixer part consumes only 4mW. For one-tone measurements (Fig.4) a Magic Tee and an external amplifier are used to compensate the losses of cables and phase shifters. The same construction is used in the LO path. Although, the LO is applied single-ended to the mixer, an on-chip differential transmission line is used for LO distribution with one end terminated on a dummy load. This minimizes the LO coupling to RF input. For two-tone measurements (Fig.5), a power combiner generates the two required tones from two external generators. Three signal generators locked to an external 10MHz reference provide the LO signal and the two RF tones.
Fig. 4. One-tone measurement setup.
Fig. 5. Two-tone measurement setup.
The power gain of the mixer/VGA tandem is adjustable from -15dB to +11dB (Fig.5) in small steps of 1dB. The IF bandwidth varies from 3.5GHz to 7GHz (Fig.5). The LO is at 59GHz.
Fig. 8. One-tone measurement for two intermediate gain settings
As gain can be distributed in different ways, for the same gain (5.8dB) the best measured linearity is IIP3=11dBm (Fig.10) but can be as low as 5dBm for different gain distribution.
Fig. 6. Mixer+VGA tandem power gain
The gain-linearity trade-off is shown in Fig.7 and Fig.8. P1 represents the power of the fundamental and P3 is the power of the third harmonic. At maximum gain, the P3OI is -3.4dBm and at minimum gain P3OI is 8.4dBm. For intermediate gain levels, (the same total power gain), gain can be distributed differently between the mixer output, VGA1 and VGA2. As shown in Fig.8, for more gain in the last IF stages, the P3OI is 13.4dBm. When the mixer output has more gain, the P3OI is 0.32dBm. The two-tone measurement from Fig.9 shows consistent results with the one-tone behavior. Close to the maximum gain (10.6dB) the IIP3 is 1.49dBm whilst, at minimum gain (-14.5dB), the IIP3 is 13.3dBm (fIF=1GHz).
Fig. 7. One-tone measurement for maximum and minimum gain
Fig. 9. Two-tone measurement for maximum and minimum gain.
In order to test the on-chip, tunable match circuit at the input of the mixer, the off-chip phase shifters are tuned to maximum imbalance. This introduces a common-mode component at the differential input and the result is the reduction of the fundamental at the input and output. Adjusting the phase imbalance in the matching circuit, the fundamental (HD1) is improved by almost 4dB (Fig.11). By adjusting the common-mode impedance of the mixer, HD2 is reduced by 3dB.
Fig. 10. Two-tone measurement (GDUT=5.8dB @ best IIP3).
Fig. 11. HD1(Common-mode) and HD2(IIP2) healing.
The down-converter implemented in a 32nm CMOS SOI process from IBM occupies 2.3x0.6mm2 real estate. The chip photomicrograph is presented in Fig.12. Table I shows the performance summary of the circuit.
Fig. 12. Chip photo.
Based on our search, the presented down-converter has the highest ever reported IIP3 @ mm-Waves (f>30GHz) in a CMOS technology. The IIP3 value of 11dB reported in [4] is realized at a lower frequency (40GHz) and at 3V power supply. V. CONCLUSION
Table I. Measurements Summary The LO applied at the input of the mixer is -2dBm. The LO/RF isolation is 43dB and the LO/IF isolation is >82dB. The simulated noise figure of the mixer/VGA tandem is 17dB for GDUT=5.8dB. Table II shows a benchmark with other CMOS mm-Wave down-converters found in literature.
A 60GHz direct down-conversion mixer with integrated sensors and digital infrastructure was presented. It was realized in a 32nm CMOS SOI process (IBM). Applied to large phased-array systems with RF power combining, the gain/linearity trade-off is exploited to achieve the best linearity performance. The high linearity of the mixer cell is facilitated by a novel linearization method without the need of extra voltage headroom. The LO is applied single-ended and switches on and off a linearized transconductor pair. The down-converter occupies 1.38mm2 in 32nm CMOS SOI and consumes 19.2mW from 1V supply. The mixer alone consumes only 4mA. The measured linearity (IIP3) for the whole down-conversion chain is better than 11.06dBm for 5.8dB gain at 60GHz. Gain can be adjusted from -15dB to 11dB in 1dB steps depending on the signal level. The LO/RF isolation is 43dB and the LO/IF isolation is better than 82dB. By adjusting phase matching at RF input and the commonmode impedance of the mixer with a variable transmission line, the input phase imbalance can be corrected and the second-order distortion (HD2) can be reduced. ACKNOWLEDGMENTS This work was conducted under the DARPA HEALICs program and was partially funded by DARPA under AFRL contract # FA8650-09-C-7924. The views expressed are those of the author and do not reflect the official policy or position of the Department of Defense or the U.S. Government. REFERENCES
Table II. Performance comparison
[1] J. Kim, et al., “Improvement of Noise Performance in Phased-Array Receivers,” in ETRI Journal, Vol.33, Number 2, April 2011, pp.176182. [2] Shlomo Shlafman, et al., “Variable Transmission Lines: Structure and Compact Modeling,” in IEEE COMCAS, Tel-Aviv, Israel, Nov. 2011. [3] Chun-Hsing Li, et al., “16.9-mW 33.7-dB Gain mm-Wave Receiver Front-End in 65 nm CMOS,’’ in IEEE SiRF, Santa-Clara, US, Jan. 2012, pp.179-182. [4] Jeng-Han Tsai, et al.,“A 25-75GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology,’’ in IEEE Microwave and Wireless Components Letter Vol.17, April 2007, pp.247-249.
