A 930MHz CMOS DC-Offset-Free DirectConversion 4-FSK Receiver
Zhaofeng Zhang, Zhiheng Chen, Louis Tsui, Jack Lau Hong Kong University of Science & Technology, Hong Kong Although direct-conversion has potential for high integration and low cost, it is plagued by issues ranging from DC offset to flicker noise. While most recent integrated single-chip direct conversion receivers [1] concentrate on wideband applications where flicker noise and DC offset can be filtered out without affecting performance, focus here is on a narrow-band application using CMOS technologies. This effort is to fully integrate RF and baseband circuitry for a narrow-band application such as a high-speed pager, which uses a 4-FSK modulation scheme. The receiver overcomes the problem using a harmonic mixing and a DC-offset cancellation. Differential structures are used throughout the receiver design (Figure 18.4.1). To minimize the DC offset induced by self-mixing, harmonic mixers [2] replace conventional ones. The two LO signals driving the mixer pair have 45° phase difference rather than the quadrature phase used in standard structures. The AGC circuitry adjusts the VGA gain to increase dynamic range, and the DC offset due to device mismatch is removed at this stage. This stage is followed by a 5th-order gyrator-C low pass filter. Filter output signals are processed by a 4-FSK on-chip demodulator. In the RF frequency range, the NQS phenomenon of the MOS transistor becomes important. The input impedance of the transistor has a significant but not-well-modelled real part, making complete on-chip matching difficult. In this design, the matching network is off-chip with one single inductor and a balun to convert the single-ended signal to differential. The measured S11 is less 20dB gain using off-chip inductors. The large gain gives room to reduce the effect of flicker noise from the following stages. The transistor sizes are optimized for input matching and noise performance. Self-mixing induced DC offset is more problematic than static DC offset caused by device mismatch. It changes with operating conditions and incoming signals. Unlike conventional mixers, a harmonic mixer utilizes the LO harmonics to mix down the RF signal and is theoretically free of self-mixing. It can be seen from Figure 18.4.2b that the LO stage (m1-m4) acts as a frequency doubler to convert input differential LO voltage to current which contains even harmonics of LO and controls transconductances of the RF stage. There is no coupling between the RF port and the current. Any LO leakage to the RF port is mixed with the second harmonic of LO frequency back to the same LO frequency which is filtered out at a later stage. A double-balanced mixer structure improves linearity and provides a constant impedance to LNA. An injected current, Ii, reduces flicker noise and improves RF gain without introducing noise at the differential output. The measured harmonic mixer is self-mixing-free and achieves ~12dB gain. To provide enough gain to reduce the noise contribution from the baseband, a buffer with 16.5dB gain is inserted after the harmonic mixer.
The AGC circuitry is shown in Figure 18.4.3. The differential variable MOS resistors are used to construct the VGA, which provides -14.5dB to 18.6dB gain. The linear resistor R0 improves linearity. It takes part of the input voltage drop so that the MOS resistors stay in the linear region even at relatively large inputs. The signal level is sensed by a peak detector and is compared with a reference voltage. Beside self-mixing, DC offset also results from other sources such as device mismatch. Since 4-FSK modulation schemes contain significant DC and low frequency energy, AC-coupling is not feasible. In this study, the peak detector performs DC offset cancellation. The difference between two DC levels of equal-amplitude sinusoidal signals is equivalent to the difference between their envelopes. The peak detector acts as an offset indicator and the offset is then subtracted from the signal. This approach is similar to high-pass filtering but it is intrinsically a nonlinear process. The minimum input signal frequency for the peak detector to carry out a DC offset cancellation is around 200Hz. With 100mV offset at the AGC input,
