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A Behavioral Modeling Approach to the Design of a Low Jitter Clock Source Gabriele Manganaro, Member, IEEE, Sung Ung Kwak, Member, IEEE, SeongHwan Cho, Member, IEEE, and Anurag Pulincherry, Member, IEEE
Abstract—Designing a low-jitter clock synthesizer is not a trivial task. Multiple noise and disturbance sources combine together in the nonlinear blocks of the phased-lock loop (PLL) affecting its performance. Moreover, deceptively small circuit nonideal characteristics can have nonnegligible effects in the behavior of the whole system. A behavioral modeling approach allowing a systematic design of the PLL is discussed here. This approach allows the designer to maintain a grasp of the fundamentals using coarse models at the early stage of the design and to eventually gain insight on the lower order effects by gradually increasing the level of detail as the design develops. Moreover, accurate design specifications for the actual circuit blocks are obtained and, eventually the transistor-level results can be back-annotated into the behavioral model for further verification. This methodology is here demonstrated in the context of the modeling, design and the implementation of a fully integrated BiCMOS 1.76 ps rms jitter 180-MHz clock synthesizer. A detailed functional model including the crystal oscillator, the main circuit nonlinearities, and noise sources of the PLL is presented. The building blocks’ models development has been motivated by actual circuit implementations. Moreover, computational pitfalls have been identified and solutions have been proposed. Finally, the key behavioral model results have been compared against measured results obtained from an actual fabricated prototype validating the effectiveness of the proposed approach. Index Terms—Analog integrated circuits, BiCMOS analog-integrated circuits, circuit modeling, circuit simulation, frequency synthesizers, integrated-circuit design, integrated-circuit modeling, jitter, nonlinear circuits, ocillator noise, phase jitter, phase-locked loops (PLL), phase noise, voltage-controlled oscillators (VCO).
I. INTRODUCTION
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IRELESS communication systems demand very high-performance analog and mixed-signal integrated circuits (ICs) with very tight cost constraints. A phased-lock loop (PLL)-based low-phase noise/jitter clock source is a key component of most of these systems. The overall phase noise performance of the synthesized clock results from the multiple sources of noise/disturbance in the PLL and their combination through the loop’s many nonlinear building blocks. Furthermore, deceptively small circuit nonideal characteristics can have nonnegligible effects on the final performance of the loop.
Manuscript received May 11, 2003; revised July 2003. This paper was recommended by Guest Editor M. Perrott. G. Manganaro and A. Pulincherry are with Engim Inc., Acton, MA 01720 USA (e-mail:
[email protected]). S. U. Kwak was with Engim Inc., Acton, MA 01720 USA. He is now with Silicon Laboratories Inc., Nashua, NH 03062-5737 USA. S. Cho was with Engim Inc., Acton, MA 01720 USA. He is now with the South Korean Army. Digital Object Identifier 10.1109/TCSII.2003.819134
As systems become more complex, behavioral modeling techniques allow the designer to maintain a grasp of the fundamental design issues by allowing control of detail when doing simulations. Fundamentals can be explored quickly by using coarse models during the initial stage of design, and performance can be verified by adding detail in later stages of the design. The primary contribution of this paper is to demonstrate a behavioral modeling methodology for a PLL-based clock generator design using Simulink/Matlab [1]. The concepts introduced can be applied to a number of PLL applications, and can also be implemented with a variety of other simulation frameworks such as CppSim [3], [4], EESof, and AMS Designer/Verilog AMS.1 Particular attention is devoted to the modeling of the main noise sources and to the nonideal characteristics of the building blocks motivated by their actual circuit implementation. Moreover, some computational pitfalls have been identified and corresponding solutions have been proposed. A few system models, at different level of abstraction, have been created using Simulink/Matlab, i.e., • small-signal (linearized) phase-domain models enabling an initial optimization of the phase noise performance [2]; • various large-signal (nonlinear) time-domain models, at different level of detail, allow verifying the jitter performance, the loop response, and to provide accurate specifications for the subsequent individual blocks circuit design. Eventually, transistor-level simulators such as Spectre and SpectreRF are used for the actual circuit-level design of the individual building blocks and the corresponding results can be back-annotated onto the behavioral models for further verification. Let us remark that the development process is not necessarily a straightforward top-down approach as lower level details can impact the overall performance and dictate a review of some of the prior design assumptions or a further refinement in the models. Several iterations up and down the different abstraction levels are often needed until a satisfactory result is obtained. Our methodology is here discussed in the context of the modeling and design of a fully-integrated BiCMOS PLL-based 180 MHz-clock synthesizer with a rms jitter of 1.76 ps to be used as the clock source for the RF front end, the data converters, and the digital-signal processing (DSP) in a complex wireless LAN access point. The key simulation results (phase noise and jitter) obtained from the more detailed behavioral model have been 1Our choice of Simulink/Matlab is based on our familiarity with this software tool and the modeling and the design approach here discussed can be easily adopted, with little or no modification, on a different simulation environment.
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Fig. 2. Block diagram of the PLL. The dashed line marks the on-chip portion of the system.
Fig. 1.
Flowchart describing the design methodology.
compared against the measured results obtained from a prototype designed and implemented using our methodology, validating in this way the proposed approach. The paper is organized as follows. The PLL system-level design methodology is discussed in Section II. The circuits for the main blocks and their functional-level models are discussed in Section III. Section IV reports and compares simulation and experimental results. Finally, conclusions are drawn in Section V. II. DESIGN METHODOLOGY The design methodology is briefly summarized by the flowchart shown in Fig. 1. An initial design is obtained using traditional PLL design techniques based on a linearized (small signal) model for the loop [2], [5]. A linear noise and a dynamic simulation can be quickly performed. Loop parameters such as the voltage-controlled oscillator (VCO) gain, the loop bandwidth and charge-pump current are chosen based on an initial estimate of the noise sources and their contribution to the output phase noise [2]. Matlab/Simulink can be useful tools for this design phase. These initial parameter choices are subsequently plugged into a more detailed functional model, which reproduces the nonlinearities of the PLL together with models of the main noise sources. Initially, a simplified nonlinear model allows to obtain more realistic results and to improve the prior design choices based on the linear model. Subsequently, the nonlinear models can be gradually made more complex and accurate, the simulation precision can be increased, so that more realistic and detailed results can be gradually obtained at the expenses of simulation time and memory. A time-domain analysis is performed with the nonlinear models (NM) [6]. Spectral analysis of the phase of the periodic waveforms obtained in this way provides us with phase noise results. At the same time, the statistics of the periods of the same waveforms provide information on the jitter distribution and magnitude. Once a satisfactory performance is obtained the corresponding design parameters provide the specifications
and the circuit parameters for the transistor-level design of the actual building blocks (VCO, charge pump, loop filter etc.). The subsequent transistor level design can be performed using a transistor level simulator such as Spectre/SpectreRF. The results obtained with the transistor level models are compared with the specifications and results provided by the nonlinear model. If the transistor level circuit design cannot meet these specifications or an inconsistency between the two models is found then the nonlinear model is updated to better reflect the reality of the actual circuits. Tradeoffs between the nonlinear model parameters are sought, using this model, to still meet the final system specifications. Then an updated set of circuit specifications is found and the circuit design is modified accordingly. The cycle is repeated until the specifications are met with reasonable design margins. Moreover, successive extensions of the functional models and iterative back annotation from the transistor-level simulations allow to refine the overall design at the expenses of lengthening the system-level simulation and lead ultimately to the more complete models discussed in Section III. This iterative process provides the designer with a lot of insight. By back-annotating the circuit results into the functional models and then performing a new system-level simulation, it is possible to immediately evaluate, both qualitatively and quantitatively, the effects of low-level changes into the overall performance or to explore other architecture alternatives. Subsequently, the layouts are designed, extracted, and simulated following the traditional design methodology for analog and RF integrated circuits. III. PLL AND MODELS FOR ITS COMPONENTS This Section illustrates how incrementally complex behavioral models can be developed on the basis of actual circuit implementations. Our methodology has been applied to the design of a BiCMOS 180-MHz clock synthesizer with a rms jitter of 1.76 ps. This synthesizer is based on a PLL that uses a 60-MHz oscillator with approximately 6 ps rms jitter as a frequency reference. A block diagram of the PLL is shown in Fig. 2. All the functional blocks, except for the crystal oscillator, are integrated on a single chip without need for external components. The structure of the loop is the one of a classical “charge-pump
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Fig. 3. Power spectral density plot for the phase noise of the crystal oscillator. The 1=f , 1=f and the white-noise regions and their corner frequencies are highlighted.
PLL” [5] and uses fully differential signals, except for the inputs of the phase and frequency detector (PFD). The crystal oscillator provides a single-ended rail-to-rail output. The balanced outputs of the PFD are up and upz and as dn and dnz, respectively. These control the charge pump which sinks to the fully differential and sources the differential current loop filter (LPF). The output of this latter block is the differential control voltage for the VCO. Its outputs are fed to a chain of differential dividers which ultimately divide the frequency down to the reference frequency and provide the feedback signal for the PFD. As shown in Fig. 2 a 180-MHz output is available at the input of the last divider with modulo-3. Taking the output at this location would not be an optimal choice. The kick-back noise at 60 MHz coming from the modulo-3 divider would be directly coupled to this output. To overcome this problem, an additional divider with modulo-2 has been introduced, as shown in Fig. 2, before the preceeding modulo-2 divider. In this way, a better 180-MHz output can be obtained and buffered off-chip.2 A fully differential LC-tank VCO with differential CMOS varactor has been chosen for its excellent phase noise and relative insensitivity to power supply noise and common mode disturbances. Our VCOs natural frequency is 2.88 GHz: 1) it allows to select an on-chip inductor fully characterized by the foundry and large Q; 2) this frequency is reasonably far away from other frequencies available in other sections of the communication system to avoid interference;3 3) it is an integer multiple of the reference and the output frequency and avoids in this way, the need of fractional modulus dividers. The circuits for the PLL blocks will be discussed in the following paragraphs together with their corresponding functional models. 2The kick-back noise problem can be simulated at transistor level using Spectre. This disturbance, however, has not been included in our functional models as the above proposed modification of the PLL architecture makes its contribution to the final output clock jitter negligible. 3Since this synthesizer has been designed for a wireless LAN system based on the 802.11a/b/g standard, frequencies close to 2.4 and 5 GHz should be avoided as these are carriers for the RF front end.
A. Crystal Oscillator A 60-MHz oscillator4 with a rms jitter of about 6 ps has been chosen both for its very low cost and because the desired output clock frequency is an integer multiple of this reference. The jitter information alone is insufficient as the design involves tradeoffs between the various noise contributions at the different locations of the loop. The manufacturer has provided a phase-noise plot for this oscillator and it is shown in Fig. 3. From this plot it is possible to identify the typical three retrend, a trend and gions where the phase noise has a finally flattens out [7]–[9]. An empirical model for this phase noise has been created. A gaussian/white noise source is filtered using a cascade of transfer functions , , in order to obtain a colored noise source approximating the trend of Fig. 3
(1a) (1b) and the uniform trends can be obtained using the The . The positions for and zero-pole transfer function can be determined as the corner frequency between the region and the region, and the corner between the region and the white noise region respectively. 4This crystal oscillator has a single-ended rail-to-rail output and a frequency stability of 50 ppm for the industrial temperature range ( 40 C to 85 C). Frequency stability is important if a clock signal is provided to the RF front end.
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are:6
, , , , , , , . It can be seen that the resulting rms jitter obtained by the time-domain simulation is around 7.4 ps and that the PSD of the phase noise corresponds to the measured data in Fig. 3, validating this model. B. Voltage Controlled Oscillator
Fig. 4. PWL approximation of the crystal oscillator’s phase noise using a colored noise source.
The trend, with its 30 dB/dec slope offers some modtrend, over the range 10 eling challenges. We modeled the Hz–1.1 KHz, by a piece-wise linear (PWL) approximation made of alternate, suitably placed, 40 and 0 dB/dec segments.5 The complete approximation is depicted in Fig. 4. at the beAn initial placement can be done by setting (that uniquely ginning of the frequency range ) and at a frequency slightly higher than the defines (otherwise the zeros of and the poles will zeros of cancel out). Eventually, the position of can be finely adjusted (at this point is deterthrough spectral analysis of mined). The crystal oscillator output can then be modeled as (2) is a hysteresis function with outputs levels 1 is the inverse Laplace transform of , . The corresponding Simulink model is shown in Fig. 5. The top part of Fig. 5 shows the synthesis of . is very large compared with When the simulated time , then numerical problems occur the simulation step-size to the argument of the cosine function in (2). In fact, the curis smaller rent simulated time will reach a point at which than the last digit used for the representation of . Then, is anymore because of the roundoff and not incremented by serious numerical problems arise. To solve that, it is possible to take advantage of the -periodicity of the cosine function. , instead of creating the arguSince , it is possible to subment of the cosine in (2) as with a saw-tooth function with time-increment rate stitute and that resets to zero any time the function reaches equal to . This is obtained using the loop shown on the lower left part of Fig. 5. Without this numerical artifice, a similar error would is small occur, for getting large, when the noise term . The simuenough to be rounded off by the addition to and lated power spectral density (PSD) of the phase noise the corresponding jitter distribution obtained by the statistics of for the time-domain simulation of this the rising edges of model are shown in Fig. 6. The parameters used for the model where and 1, while
5A different pole/zero placement method to approximate fractional slope Bode plots can be found in [10]. More can also be found in [16].
The circuit schematic for the LC-tank voltage controlled os, together with their cillator is shown in Fig. 7. The BJTs base and emitter resistors implement the active element. The is biased through which is generated cross-coupled pair with by a replica circuit not shown in Fig. 7. allows to bias a high dc collector voltage and, hence, to maximize the swing across the tank and reduce the distortion due to the saturation of . The integrated inductor and the equivalent capacitor in parallel to it define the tank (3) is the capacitance of the CMOS differential Here varactor MP-MN proposed by Tiebout in [11] and controlled by . Also, we assume that the capacitance seen is negligible. The optimization of the tank has at the base of been done as discussed in [11]. However, the actual integrated inductor has been selected from the component library provided by the foundry, as these inductors have been fully characterized and optimized to provide large quality factors.7 and , instead of a single capacitor directly in Using parallel with the varactor, we have the following advantages: • the voltage swing across the tank (specifically, across the inductor ) can be kept very large maximizing the phase noise performance; and allows to • the capacitive divider constituted by provide an AC coupled attenuated oscillation to the suband ) and, hence, sequent emitter follower stage ( reducing distortion at the followers output. This also prevents overdriving the input BJTs in the following divider stage. A plot of the tuning characteristic (output frequency versus differential control voltage ) obtained by parametric8 postlayout simulation using Spectre is depicted in Fig. 8. The noise analysis of LC-tank VCOs has been widely discussed in the technical literature [7], [8], [12], [13]. Here, we will assume that the oscillation across the tank is sinusoidal and noise component that the phase noise is dominated by the 6T is the absolute temperature in Kelvin degrees while S is the power density of the white noise source N (s) in rad . 7A superior inductor layout is discussed in [11], but that may require prior fabrication and characterization. The actual inductor used in our final implementation is a spiral inductor with 4 turns, an outer dimension of 220 m 220 m, a metal width of 15 m, an inductance of about 2.5 nH, and a declared Q of about 12 14 at the desired oscillation frequency of 2.88 GHz. This is realized on the highest metal level, which is manufactured with a very large thickness (4 m) to minimize losses in the conductor. Moreover, a maze of deep trenches has been created in the substrate underneath the inductor to minimize the losses in the substrate. All other conductors are spaced apart from the inductor compatibly with the limits dictated by the metal density requirements of the foundry. 8The differential control voltage is the parameter.
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Fig. 5. Simulink model for the crystal oscillator.
(a)
(b) Fig. 6. (a) PSD for the model of the crystal oscillator’s phase noise. (b) Cycle jitter statistical distribution obtained through the time-domain simulation of the oscillator’s model.
over the interval of our interest. In order to obtain that, the equivat the control input of the VCO with alent white noise source is found transfer function (4)
where is the Boltzman’s constant, is the absolute temperais the equivalent resistance modeling the tank loss, ture, is a corrective factor to account for the noise contributed by the is the oscillation frequency, active element of the VCO [13], is the quality factor of the tank and is the VCO gain. The linearized noise model is depicted in Fig. 9.
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Fig. 8. VCO tuning characteristic.
Fig. 7. Circuit schematic for the VCO.
Fig. 9. Linearized noise model for the VCO.
Even though a good estimate for can be calculated from has been dethe physical data of the tank, the actual value for termined by back-annotation from the VCO circuit. The actual VCO circuit has been simulated using the phase noise analysis is adjusted so that the phase noise at the of SpectreRF and output of the above-linearized model matches the one obtained from the transistor level model. The VCO output can be written as (5) But, as shown by the tuning characteristic of Fig. 8, is not constant over the input range of the differential control voltage . A more accurate (nonlinear) model is
(6) is the voltage-to-angular frequency characteristic of and the VCO, namely the tuning characteristic of Fig. 8, apart for a ( is the slope of when the scale factor equal to loop reaches its steady state). Here we are implicitly making does not change dramatithe simplifying assumption that and we actually evaluate (4) at the steady state cally with condition. A PWL model of the voltage-frequency characterhas been included in our VCO functional model istic shown in Fig. 10 by means of a lookup table block. The same numerical consideration done previously for the phase of the crystal oscillator applies here because of the round-off error. The same solution using counter-like cycles is used. A similar count-reset cycle with periodicity equal to has also been introduced for the integral in the argument of the is cosine in (6) as can be seen in the upper part of Fig. 10. not shown in this figure as it is added onto before being fed to this model.
C. Phase and Frequency Detector, Charge Pump, Loop Filter, Dividers The phase and frequency detector is a well-known “type 4” PFD using two edge-triggered resettable D flip-flops and [5]. All these digital a NAND gate with transmission delay blocks are part of the Simulink block-set and an accurate gate-level model for the PFD is easily built. The circuits for the modulo-2 dividers have been implemented using a cascade of fully differential master-slave BJT flip-flops like the one depicted in Fig. 11. The final division by 3 is implemented by a modulo-3 counter using two of these flip-flops and a differential NAND gate. Similarly to the PFD, the feedback dividers have been modeled using Simulink flip-flops and logic gates, mirroring the actual gate-level structure of the final implementation. Thermal noise introduced by the dividers has been added to their output. The circuit for the charge pump and the loop filter is shown , , and . in Fig. 12. The loop filter is composed by , and determine the low-frequency filter characteristic, is used to attenuate the output ripple at the while reference frequency by adding another pole one decade higher than the cutoff frequency. An additional pole is placed one and . more decade higher for more attenuation by The CP is based on a fully differential current-steering approach. The transistors MNb and MPb are used as current . Clearly this charge sources, each one providing pump requires a common mode feedback circuit, not shown and in the picture, sensing the common mode level across regulating the stabilizing it to a set point at current by acting on the gates of MPb. The Simulink model for the CP/Loop Filter is depicted in Fig. 13. On the upper-left part of Fig. 13 it is possible to see the simple model for the CP constituted by the gain blocks and followed by a summing node. These represent the transconductances that respectively source and sink the output differential current of the CP into the filter.
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Fig. 10.
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Functional model for the VCO.
(a) Fig. 12. Circuit schematic for the charge pump and the loop filter.
(b) Fig. 11. Master-slave flip-flop used as a divide by two stage; (a) single stage and (b) complete master-slave flip-flop.
Most of the remaining part of the model is a state representation of the filter with a current input and voltage output. The white-noise source on the bottom of Fig. 13 models the noise produced by the filter and the white noise contributed by the CP. noise has been neglected. In our design, the cutoff The CPs frequency for the loop filter has been set at around 250 KHz, while the stabilizing zero has been placed at around 170 KHz. D. Complete Time-Domain Functional Model and Final Implementation As discussed in Section II, a variety of frequency domain and time-domain models have been used to simulate and design the
PLL at the functional level. The most interesting and complex is the complete nonlinear time-domain model shown in Fig. 14. The previously described blocks can be recognized in this model. Moreover, a variety of additional blocks measuring the waveforms’ periods at different locations of the loop or tracking entire waveforms for limited time are visible in the same figure. The time-domain simulation of the most complex model, at high precision and very narrow step-size can take a considerably long time. A significant speed-up (up to ten times faster, according to “The MathWorks” [1]) can be obtained using the so-called “Simulink Accelerator”: the Simulink model is automatically translated into a corresponding C code, which is then compiled and run. The simulation problems of PLLs due to the wide differences between loop time-constants, oscillation periods, and magnitude of the jitter, are well known [3]–[6], [14], [15]. The Matlab code simulating the model has been mostly optimized in terms of the amount of memory necessary to gather the data using programming techniques and common sense. For example, in order to determine the statistics of the jitter, it is not necessary to save the entire output waveform; it is sufficient to monitor
MANGANARO et al.: A BEHAVIORAL MODELING APPROACH TO THE DESIGN OF A LOW JITTER CLOCK SOURCE
Fig. 13.
Charge pump and loop filter Simulink model.
Fig. 14.
A complete time-domain model for the PLL.
the completion of each period and update the average and standard deviation of the current estimated jitter using the information about the new period. Also, oversampling/decimating blocks have been appropriately used in some parts of the system. The time needed for simulating the most complex model can however be significant and more sophisticated Matlab code is needed if an interactive use of these models is required. Alternatively, our models can be used with other simulators such as CppSim [3], [4]. The PLL has been implemented on a six-metal levels 3.3-V 0.5- m BiCMOS technology and it ocSiGe . The layout for the cupies an active area of about PLL shown in Fig. 15(a) completes the description of the design. The floor-plan highlighting the individual blocks is depicted in Fig. 15(b). The spiral inductor is visible on the upper-center part of the layout. All the areas not occupied by circuits have been filled up with decoupling capacitors for the power supplies. The
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block marked as “I ref” is a bandgap current reference which generates all the bias currents. The die has been packaged in a micro lead frame package (MLP): a quad sides TQFN package with 24 pins with pin inductance of around 1.2 nH. IV. FINAL SIMULATION AND EXPERIMENTAL RESULTS Some simulation results, obtained using the complete nonlinear model, are here discussed. Our main attention, however, is devoted to the phase noise/jitter performance and the corresponding simulation results will be compared with actual measurements to validate our methodology. Various control voltage trajectories are shown in Fig. 16 for different initial conditions. The intrinsic nonlinear behavior of the loop is clearly visible in some of these waveforms. However, when the state approaches the desired final equilibrium, the
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(a)
(b) Fig. 15.
(a) Layout and (b) floorplan of the die.
system behaves more linearly and the classic two-pole system settling with a small overshoot is observed. A phase noise plot simulated with the above complete PLL model and obtained at the output of the VCO once the loop has reached the steady-state is shown in Fig. 17(a). Notice that the accuracy of this PSD decreases at lower-frequency offsets. This is due to the finite length of the simulated VCO waveform. The corresponding statistics for the jitter of the desired output clock at 180 MHz is reported in Fig. 17(b). The phase noise and jitter measured for the output clock at 180 MHz is shown in Fig. 18. This plot can be compared with the plot obtained in simulation and shown in Fig. 17(a), keeping in mind, however, that the PSD of Fig. 17(a) is obtained at the VCO output while the plot of Fig. 18 is obtained after further division by 8. From both plots it is possible to distinguish the noise contributions from the various blocks of the system consistently with what is discussed in Section III. In particular, in Fig. 18 the crystal oscillator noise contribution is clearly visible in the lower-frequency range and up to approximately 1 3 KHz. Further comparison can be made in this range with Fig. 3. The multiplied divider noise is dominating the range between 3 5 KHz and 100 200 KHz. Moreover, it is responsible for a broad-band increase in power of the entire phase noise beyond about 5 KHz [2], [3]. It appears that this noise contribution turned out to be a bit worse than our simulated predictions. The filter cutoff frequency at 250 KHz can be recognized close to the noise peaking near the cursor 2 in the picture. The phase noise is dominated by the VCO in the range that goes from around the cutoff frequency up to approximately 10-MHz offset frequency. The noise flattens out and becomes white beyond this
Fig. 16.
Transient behavior of the control voltage v for different initial states.
range. A small spur can be seen at 60-MHz frequency offset in Fig. 18 but not in Fig. 17(a). That could be due to the update rate of the charge pump, which can couple to the output in different ways, including substrate and power supply. It could also be due to a charge-pump offset. Moreover, the kick-back noise from the last divider, mentioned above but not modeled at functional level, is another possible contributor to this spurious tone. These and some other parasitic effects have not been accounted in our model but can easily be added improving its predictions. The total rms jitter measured in the offset frequency range from 100 Hz to 100 MHz is shown in the upper right corner of Fig. 18 and it is equal to 1.76 ps. A summary of all the PLL features and measurement results is reported in Table I.
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(a)
(b) Fig. 17. Overall PLL noise performance: (a) PSD for the phase noise at the output of the VCO obtained from the functional model of the PLL and (b) corresponding jitter statistics of the desired output clock.
TABLE I SUMMARY OF THE IMPLEMENTATION INFORMATION
Fig. 18. Phase noise plot measured using an Agilent E4440A Spectrum Analyzer. The corresponding rms jitter obtained integrating over the range 100 Hz 100 MHz is shown in the upper right corner. Notice the vertical axis reference at 70 dBc/Hz in order to evaluate the actual power density.
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V. CONCLUSION A behavioral modeling approach for the design of low jitter clock synthesizers has been here discussed. A thorough system design allows an optimal building block design and gives in-
sight to the key characteristics determining the overall performance by selectively controlling and evaluating the contribution of each noise source and nonideal element. Gradual refinements of the model complexity and block parameters lead to realistic
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design specifications for the actual circuits and provide accurate predictions of the overall system performance. The proposed models have been here developed on the basis of actual circuit implementation and allow iterative back-annotation from the actual circuits for further verification. The effectiveness of the proposed modeling approach has been validated by direct comparison against experimental results. In particular, the measured phase noise of the output clock follows the predictions obtained using the more sophisticated behavioral model; the rms jitter estimated by our behavioral model (1.58 ps) differs from the actual rms jitter measured on a prototype (1.76 ps) by only 10%.
ACKNOWLEDGMENT The authors thank all the people at Engim Inc. for their support. In particular J. Archambault for insightful discussions and help with the measurements, and A Chandrakasan for his technical advice and support. Finally, the comments and advice from the anonymous reviewers have been greatly appreciated and helped in improving the quality of this paper.
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Gabriele Manganaro (S’95–M’99) received the Dr.Eng. Degree (M.Sc.) in electronic engineering and the Ph.D. degree in electrical engineering from the University of Catania, Italy, in 1994 and 1998, respectively. From 1996 to 1997, he was a Research Associate and Lecturer with the Department of Electrical Engineering, Texas A&M University, College Station. From 1998 to 2001, he was a Mixed-Signal Designer and Member of the Technical Staff at Texas Instruments Inc., Dallas. In 2001, he joined Engim, Inc., Acton, MA, as Director of Analog Baseband Design. He is author or co-author of 47 scientific papers in international journals and conferences, and is co-author of Cellular Neural Networks (New York: Springer, 1999) based on his doctoral dissertation. He holds three U.S. patents and four more are pending. His research and professional interests include high-performance analog integrated circuits design, in particular, data converter and phase-locked loop design, and in the theory, design and application of nonlinear electronic circuits and systems. Dr. Manganaro served as Program Chairman and as General Chairman for the Dallas Chapter of the IEEE Circuits and Systems Society from 1999 to 2001. He has served on the technical committee of several IEEE international conferences and has given invited lectures in Italy, U.K., and the U.S. He was the recipient of the 1999 IEEE Circuits and Systems Outstanding Young Author Award and the 2000 IEEE Dallas Section Outstanding Service Award.
Sung Ung Kwak (S’95–M’97) was born in Seoul, Korea, in 1965. He received the B.S., M.S. and Ph.D. degrees in the electrical and computer engineering from the University of Illinois, Urbana-Champaign, 1991, 1993, and 1997, respectively. In 1995, he joined the Semiconductor Division of Harris Corporation, Melbourne, FL, which later became Intersil, as a lead engineer working at various high-speed A/D converter products. From 1998 to 2001 he was with Texas Instruments, Dallas, TX, where he was a Project Leader for the communications and video IC products. In 2001, he joined Engim, Inc., Acton, MA, as Director in the Analog Baseband Group involved in the wireless communication IC design. He is currently with Silicon Laboratories, Nashua, NH, where he is a Senior Engineer in the Optical Network Group. His research interests include RF IC design for communications and high-speed circuit design for data acquisition system.
SeongHwan Cho (S’94–M’03) received the B.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1995, and the S.M. and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology, Cambridge, in 1997 and 2002, respectively. In 2002, he joined Engim, Inc., where he was involved in data converters, phased-locked loops (PLL) and voltage-controlled oscillator (VCO) design. Since 2003, he has been with the military of South Korea working as a public service assistant. His research interests include low-power circuits and systems for wireless sensors.
Anurag Pulincherry (S’00–M’03) was born in Kerala, India, in 1978. He received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Madras, in 2000, and the M.S. degree in electrical engineering from Oregon State University, Portland, in 2002. He is currently a Design Engineer in the Analog group at Engim, Inc., Acton, MA. His research interests are in the area of high speed, high performance A/D converters.
