A Block-Based Open Source Approach for a

A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA Technology* Andres Cicuttin, Maria Liz Crespo, Alexander Shapiro ICTP-INFN, Microprocessor Laboratory Trieste, Italy email: {cicuttin, mcrespo, ashapiro}@ictp.it

Abstract Recent advances in Field-Programmable Gate Arrays (FPGA) have made it possible and affordable to efficiently build various complex hardware emulation systems. This technology promises new levels of system integration onto a single FPGA, but also presents significant challenges to designers. The proposed Reconfigurable Virtual Instrumentation (RVI) project leverages the latest FPGA technological advances. Its goal is to provide a low-cost reusable hardware/software platform for the emulation of multiple electronic and scientific instrumentation systems. Unlike previous approaches, the proposed architecture leverages a block-based design methodology that emphasizes design reuse as an effective mean to cope with the challenge of a growing design complexity. An open source approach to the project allows future contributors to rely on previously developed software, making the emulation of new instruments increasingly more costeffective. This paper details the architecture of the RVI system with its main building blocks. It also illustrates its capabilities with multiple implementation examples.

1. Introduction With its recent architectural evolutions and everincreasing capacity, FPGAs today represent the fastest growing segment of the Programmable Logic Device (PLD) market. One of the primary attributes of FPGAs is flexibility. Additional advantages such as virtually unlimited in-circuit re-programmability, fast design cycle, almost free design tools, and low nonrecurring engineering fees make FPGA-based systems an increasingly attractive solution for evaluating and implementing alternative design architectures; thus accelerating the design process and time to market of new products. Latest generations of FPGAs integrate resources such as, on-chip dual-port memory, higher speed input/output (I/O) implementations, optimized arithmetic operators, microprocessors, and advanced clock control circuitry. These features serve to expand the range of applications FPGA components can implement. Some of the most exciting new uses of FPGAs go beyond the *This work is supported in part by Actel Corp.

Nizar Abdallah, Member, IEEE Actel Corp. Mountain View, CA, USA email: [email protected]

implementation of digital logic, and also harness most FPGA architectures and devices as a general-purpose computation medium [1]. As FPGAs keep on evolving, there will continue to be a growing number of opportunities for implementing quite different FPGA-based systems that were only possible with other complex and expensive technologies. This is the case for our area of interest in experimental physics where FPGA technology is opening up new possibilities in custom and standard general purpose instrumentation such as waveform generators and logic analyzers. However, using FPGA components for system emulation does not come without its own assortment of challenges across system architecture and logic design. Where system architects may be available, skilled logic designers are a scarce resource [2]. Current projects are driving design teams to gain experience with more design skills than ever before [3]. Today’s FPGA engineer may require skills from system, software, and hardware engineering roles. Critical skills include implementation using advanced FPGA fabrics, embedded processors, intellectual property, and high-speed board level design. As a consequence, there is a need for modern applications to include creative and rigorous design approaches to address the complexity of FPGA-based design [4]. While the concept of reconfigurable virtual instrumentation using FPGA technology is not new, past approaches have not had all the right elements to create a successful solution. As will be demonstrated throughout this paper, one important element is a strong, shared opencore library. Instead, earlier work and publications were only focusing on the FPGA re-configurability aspect through a software interface [5][6][7][8]. Building a new virtual instrument required a full hardware re-design of the FPGA part in the system with all the challenges it presents as mentioned earlier. Little effort, if any, was spent on building re-usable FPGA blocks that would allow a painless development of new systems or the enhancement of existing ones to benefit from future FPGA generations. Moreover, the software itself did not include low-level capabilities, such as an open interface to access FPGA resources suitable for custom non-standard architectural experimentations. We believe that nowadays, FPGA technology reached a level of maturity and popularity that

allows giving birth to a broad platform for the creation of an open core, open source library of modular components for reconfigurable virtual instrumentation. The platform is essentially based on FPGA devices and standard personal computers. Besides allowing a rapid evaluation of new custom instrumentation, such a platform is of a particular interest to the academic and scientific community, as it represents a low-cost educational solution for universities and research institutions. This is particularly the case in developing countries where financial constraints are extremely tight making it very difficult to afford the cost of expensive instruments such as digital oscilloscopes, waveform generators, or logic analyzers. In this paper, we start by showing through the architectural description of the RVI platform how FPGAs can be used to emulate electronic and scientific instrumentation. Then we will show that by relying on a modular block-based design and design for re-use methodology, we’re able to cope with the complex mix of skills and design effort required in promoting a future expansion of the project. Building adds-on incremental solutions that can be reutilized by a large community of users and developers represents one of the major ideas behind the RVI platform. This concept is enforced at the hardware architecture level through the use of the public Wishbone IP interconnection standard, which is present on many of the IP cores offered by the OpenCores organization [9]. This also implies that the solution needs to be open source [10] allowing a constructive synergy among all developers who could leverage existing achievements. Each new implementation increases the value of the RVI platform by enhancing its library of virtual instruments. In the following, we first describe the architecture of the RVI platform. In Section 3 we present some of the target architectures that can be emulated with RVI. In Section 4 we explain the mechanism to add new instruments to the system. Finally, in Section 5 we summarize the capabilities of RVI and conclude.

(e.g. digital oscilloscope, arbitrary waveform generator, logic analyzer, digital filter…) from a library of instruments and configures the RVI system to convert it into the selected instrument with its associated console. A modular architectural approach will permit independent software and hardware upgrades, allowing reusing most of the developed components (software code and hardware cores). The above concept can be concretely implemented by exploiting the latest cutting-edge powerful FPGAs present in the market. For our implementation, we will be using medium to large size devices from the Actel Flash ProASIC3E family [11].

2.1. High-level architecture A high-level RVI system architecture comprises both hardware and software sub-systems. The hardware includes a standard personal computer and the RI connected to it through a physical connection. The connection allows the reconfiguration of the RI as well as the exchange of information between the PC and the RI. The information exchanged can be data, commands, error messages, or acknowledgement messages. Figure 1 shows a board-level description of the RVI hardware sub-system. The software related to the PC is called Computer Software (CS) and the code corresponding to the FPGA of the RI is called Synthesizable Hardware Description Code (SHDC). The CS is responsible for the user interface, the port management, and eventually a few offline data elaboration programs and utilities. The SHDC is responsible for the management of the physical connection with the PC, the ADC and DAC operations, data generation and acquisition, real-time online data processing (arithmetic, compression, filtering…), and on-board real time mass data handling (storage, retrieving, fetching…). Figure 2 shows the RVI block-level global software architecture.

2.2. Reconfigurable instrument

2. RVI system architecture By Reconfigurable Instrument (RI) we mean a versatile hardware device that can be reconfigured into different electronic instruments using a software tool. By Virtual Instrumentation we mean a hardware and software combination that allows the emulation of an instrument through a custom virtual console and a graphical user interface. The interface allows operating and controlling the electronic device from the software console as if it was a real instrument. The RVI system can be seen as a “magicbox” connected to a PC through a standard port (Serial, Parallel, USB, Ethernet…). The system has several generic inputs and outputs, both analog and digital. A high-level software application runs on the PC and provides a user interface to the operator who can select a virtual instrument

The reconfigurable instrument includes one mother board (the RVI main board) and two daughter boards. The mother board is built around a medium to large capacity FPGA device (ACTEL A3PE 600/1500/3000) and four main blocks, namely: a block of communication ports, an extension memory, debugging facilities and miscellaneous components, and two high quality board-to-board connectors with 54 pins directly connected to the FPGA general purpose I/Os. After having performed several partial tests on different FPGA development platforms and several external interface circuits we have decided to build a specific RVI prototype system based on custom boards. A complex RI prototype has been designed and verified. The board is expected to be manufactured soon, once the targeted FPGA is

Development/Debugging Facilities LCDs, LEDs, Push Buttons

Trigger I/O

External Physical World

A/D, D/A, Triggers in/out A/D, D/A, Triggers in/out

FPGA

Digital Interfaces

Actel ProASIC3E

Extension Connectors (board-to-board)

Personal Computer (User, Operator)

Communication Ports PP, RS232, USB, Ethernet

External memory extension SDRAM Module

Digital Analog I/Os I/Os

Daughter Boards

Digital Analog I/Os I/Os

RVI Main (mother) Board

Trigger I/O

Figure 1. Initial board set for an RVI System commercially available. In the meantime, simplified versions were built using available less complex devices to prove the concepts presented in this paper. Four standard communication ports are logically connected to the FPGA: RS232, USB1.2, USB2.0, and Ethernet 10/100. The main board has a SODIMM 144STD socket for SDRAM modules from 128 MB to 512MB. For debugging purposes, the main board also counts on four push-buttons (one denounced for manual clocking), four LEDs, and a four-digit seven-segment LCD display; all attached to the FPGA. The first daughter board, a Low Performance Daughter Board (LP-DB), contains a dual channel 10-bits 20 MSPS Digital-to-Analog Converter (AD9201, Analog Devices), a dual channel 14-bit 1 MSPS Digital-to-Analog Converter (LTC1654, Linear). The second daughter board, a High Performance Daughter Board (HP-DB) contains a single channel 14-bits 125 MSPS Digital-to-Analog Converter (LTC2255, Linear), a single channel 16-bit 50 MSPS Digital-to-Analog Converter (LTC1668, Linear). Both boards have signal conditioning circuits to accept and generate AC and DC signals in different ranges as described in Table 1. Also, both daughter boards have one generic digital I/O for triggering, a general purpose digital extension connector, and a high quality board to board connector Table 1. Analog I/O ranges of the daughter boards LP-DB

In Range DC AC 0–2V 0–1V

HP-DB

+/– 3 V

–

Out Range DC AC 0 – 1.65 V 3.3 V +/– 4 V

–

allowing the daughter boards to be directly plugged into the RVI main board. Optionally, the RI could count on an on-board mass storage SDRAM memory to expand the FPGA memory capacity. This can be used for real time data acquisition or other fast applications where the bandwidth of the physical connection is not sufficient to rely on the PC memory. Other miscellaneous components include a crystal oscillator, a small (PLD device) circuit to switch the physical connection between communication and configuration modes. As an example, using a medium size FPGA with 500 user I/Os, it is possible to attach an SDRAM module from 128MB to 1GB, four 12-bits ADC, four 12-bits DAC, and a generic input/output multi-standard digital connector with around 200 pins.

2.3. The computer software The computer software is a collection of independent modules hierarchically organized. Each module operates on standardized files (buffers) containing all relevant information including data, commands, and error messages. In the RVI system, time critical operations are carried out in the RI while non critical operations are processed by the PC. Basically, the CS provides: • A generic RVI graphical and textual user interface. • A Library of virtual instruments with custom user interfaces. • Data storage facilities. • Automatic physical communication control (drivers).

User Interface

PC

buffers/files

buffers/files

Data Processing Modules

Data Processing Modules

buffers/files

buffers/files Device Driver

FPGA

PC Interface Core

Dual Port Memory

only for the PC. A few registers are reserved to handle the RVI communication protocol. Therefore, these are not available for generic use. Depending on the nature of the port and the core instrument, the RI may send an interrupt signal to the PC to trigger a specific action. Also, the PC can do polling on specific registers to check whether there’s a request for a given action. The PC may also use registers to pass signals and parameters to the core instrument. The exchange of signals through registers could be used to implement a semaphored mechanism for the simultaneous access to the dual port memory or to regulate the access to the external memory unit.

3. Case examples Registers

Instrument Core FPGA Ports

Figure 2. Global software architecture Optionally, the CS could also provide additional services such as: • An internet connection for remote instrument control and operation. • Specific data analysis packages and other facilities. • A friendly interface with a general purpose in-chip logic analyzer for development and debugging.

2.4. Synthesizable hardware description code The synthesizable hardware description code is essentially a synthesis friendly VHDL description divided into four basic blocks: A port communication module, a dual port memory and registers to communicate with the core, the instrument core, and an FPGA port assignment (and other constraints) description file. Optionally, the SHDC could include an external SDRAM module controller, an on chip logic analyzer and stimuli generator modules for debugging and development, and physical as well as timing constraints files. The port communication module supports the basic protocol of the connection and, at a higher level, an RVI specific protocol to handle the RI. The communication between the PC and the Core Instrument is done in two ways. The first is by reading and writing data into the dual port memory. The PC accesses the memory from one port and the Core Instrument from the other port. The second way is by reading and writing into registers. Some registers are read-only for the Core Instrument and others are read-

In order to integrate a reconfigurable instrument core in an RVI system it must comply with the standardized interfaces of the PC-FPGA communication block and the external hardware specific interface block. It should also comply with a common mechanism of interaction. If the three main blocks: PC-FPGA communication block, instrument core, and the external hardware interface respect both previous conditions, then each block can be updated or upgraded independently and can be reused in different contexts. The interfaces and the mechanism of interaction depend on the complexity and performance of the overall system. In order to define an Open Standard for an RVI system based on FPGA, several important factors must be considered: • Expected evolution of FPGA devices in terms of Logic capacity, performance, and special resources. • External hardware availability such as (daughter/mezzanine boards with ADCs, DACs, FPAAs, cables, connectors). • Possible PC communication ports (PP, USB, Serial, Ethernet, etc…). • Software tools: Synthesizers, FPGA programming tools, Simulation and Debugging tools, Ad Hoc tools (GUI, High Level RVI design capture and synthesis, on chip logic analyzers). • Quantity and quality of targeted instruments. • Portability, updatability and upgradeability of the system and/or any of its subsystems (Software, Operating System, PC ports, FPGA families, external hardware, etc…). In this section we briefly describe a few examples to demonstrate the feasibility of the project. Part of the challenge is to be able to foresee the needed evolution in terms of complexity and performance that needs to be achieved by the system.

3.2. Arbitrary waveform generator and digital oscilloscope Figure 5 shows the block diagram of the FPGA architecture for instruments such as an Arbitrary Waveform

+

-1 Z

Z

-1

+

Z

-1

+

–

-1 Z

+

+

–

-1 Z

–

-1 Z

Figure 3. Hogenauer SINC3 filter architecture

Instrument Core

FPGA RAM

PC-FPGA Block

SINC3 Single Channel data_out

Σ−∆ modulated input bit stream

FPGA

Registers

This is a simplified implementation of a third order Sigma-Delta demodulator [12]. This module is an essential part of a Sigma-Delta analog-to-digital converter [13]. In this case, it is basically a third order SINC filter that takes a bit stream input from a second order sigma-delta modulator and generates a digital representation of the sampled analog signal. We have followed the architecture proposed in [14] because its suitability for an FPGA implementation. The final instrument must contain sixteen demodulators working in parallel at a clock frequency of 80 MHz. Since the required computational power exceeds the capability of any ordinary general purpose processor or digital signal processor, we have naturally decided to use an FPGA by mean of an RVI system. Without going into too many technical details, in this implementation each demodulation channel is a sequence of three adder-accumulators followed by a decimator and three differentiators as depicted in Figure 3. The bit stream input enters from the left activating the three integrators at every new bit, while a decimator passes an output value from the last integrator to the differentiator chain at a lower rate (decimated rate). The decimation factor R is the parameter that determines the working frequency of the differentiators. This frequency is that of the integrators divided by R. Hence, the decimation factor R (decim_rate) is the only relevant parameter of the demodulator. An additional start/stop signal resets the block and is used to initiate the demodulation activity and to save the final value coming out of the last differentiator. In the extreme case in which R is one, this channel performs six arithmetic operations per clock cycle, sixteen channels perform 96 operations per clock cycle, and thus a clock frequency of 80 MHz determines a total of approx. 8 x 109 16-bit arithmetic operations per second, which is clearly beyond the capacity of most modern processors based on traditional sequential architectures. The performance achieved by this demodulator allowed implementing an analog-to-digital converter which achieves 12 effective bits at 1 MHz conversion rate. For quick evaluation, we implemented this example in an APA300 FPGA [15]. Overall, it occupied approximately 55% of the logic resources. At a high level, the Instrument Core (reduced to a single channel) looks very simple; it can be seen as a black-box with few inputs and one output. Figure 4 shows the FPGA implementation of the core schematic with its connections to the external world and to the communication module.

+

Parallel Port

3.1. Third order sigma-delta demodulator

data_in start/reset clk

decim_rate

Figure 4. Block diagram of the FPGA architecture for a reconfigurable demodulator

Generator or a Digital Oscilloscope. In both cases, it is required to deal with the external hardware in charge of conditioning the analog signal and its digital conversion. A basic digital oscilloscope requires handling fast analog-todigital converters, processing the input digitized data stream in real time for triggering and storing data in fast on-chip or on-board memory before offline transfer to the PC. A simple waveform generator capable of generating standard waveforms such us triangular, square, ramp, etc has been implemented in an APA300 Flash FPGA [15]. It also contains a custom 14-bit CORDIC [12] block for the generation of sine waves through the 14-bits 1 MSPS digital-to-analog converter working at 1 MSPS. The control of this signal generator is operated from a PC through the parallel port. The operation is done essentially by means of reading and writing the registers of the communication block, where each field conveys different information such as type of wave, frequency, amplitude, etc... Figure 6 shows a LabView interface developed under Windows XP for the RVI standard waveform generator with a dual channel 14-bit 1MSPS DAC.

PC-FPGA Block

Instrument Core

Clock Clock R/W R/W

Registers

Paramete Parameters rs Control Control Signals Signals Status Status

Data

Control Signals

Trigger

Daughter Board Specific Interface Block

Address Address

Digital Oscilloscope Arbitrary Waveform Generator, etc

FPGA RAM

Parallel Port

Data Data

Extension connector

FPGA

Figure 6. Interface for an RVI waveform generator

Figure 5. Block diagram for a reconfigurable virtual arbitrary waveform generator or a digital oscilloscope

4. Designing new complex instruments Most of the software involved in the above virtual instrumentation examples can be reused for many other core instruments without modification. The hardware is simply reconfigured to turn it into a different instrument. Moreover, the availability of general purpose debugging interfaces as shown in Figure 7, greatly simplifies the process. Such interfaces allow reading and writing from and into the registers and memory of the communication block, as well as downloading or uploading data between the FPGA and the PC. Such interface was validated with an APA150 and an APA300. Figure 8 depicts the block diagram of the next level of FPGA implementation for a more complex Reconfigurable Virtual Instrumentation system that is currently being implemented in the Main Board. The internal RVI bus allows exchanging data between the PC/FPGA communication block and each of the other blocks having a common interface. In our implementation, we will be using the Wishbone interconnection standard, which is already present on many available open-cores. For speed critical communication, we foresee point-to-point fast dedicated connections. The highlighted parts in the figure show a possible concrete implementation for two instruments simultaneously: a Low Performance Arbitrary Waveform Generator and a Low Performance Digital Oscilloscope, with a display controller for debugging and monitoring. The RVI Controller block receives commands from the PC to perform direct memory access data transfers between the dual port memory and any block, as well as between any two blocks connected to the common bus.

Figure 7. General purpose RVI debugging interface By promoting an open source/open core approach with the RVI project, we allow a large community of users/contributors to rely on all developed materials, saving important costs of commercial IP blocks. It will also be possible to modify the cores in order to adapt them to different situations for optimal performance. In general all benefits of open source software apply to an RVI system like the one proposed here, contributing socially and economically through a sustainable development. We expect from the RVI system to stimulate the intellectual property production with a high technological content and a very low financial investment since, in this case, the manpower is the dominant cost. While the cost of the RVI hardware is expected to remain approximately constant, its value will strongly increase with each new virtual instrument that can be implemented through the RVI platform. An easy updateability and upgradeability of the system will mitigate the obsolescence of the hardware, while the portability will allow an expansion of the potential users/developers base. After an initial global architecture proposal, the open source approach will allow the developers to evolve towards better open standards that facilitate the interchangeability and interoperability of the different software and hardware building blocks.

5. Conclusion FPGA technologies are opening up new opportunities including in the field of scientific instrumentation. Although the concepts of virtual instrumentation and reconfigurable computing are not new, only recently we reached the possibility of implementing a complete RVI system based on FPGA technology at a reasonable hardware cost/performance ratio. However, the main remaining cost of such system is the high effort required to develop all the software/hardware chain of new systems. We cannot expect to obtain commercial solutions at reasonable costs anytime in the near future, and this prevents scientists from fully taking advantage of the great potentialities modern FPGA technologies have to offer. This situation will not improve unless a wide freely available collection/library of standardized functional blocks (at PC and FPGA levels) is promoted to implement a complete prototyping/instrumentation system. In this paper, we showed through the architectural description of the RVI project how FPGAs can be used to emulate electronic and scientific instrumentation. Through

an RVI platform, it is possible to emulate many standard general purpose instruments but it is also possible to implement sophisticated instrumentation for custom specific applications that cannot be accomplished by standard instruments. The RVI platform represents in itself a low cost solution for those who cannot afford the high cost of standard electronic and scientific instrumentation, a very common situation at universities and research institutions in developing countries. The capability of reconfiguring the FPGA in the RVI system to execute specific tasks and algorithms on demand at high performance opens up the possibility of reconfigurable computing. The RI could be seen as a parallel coprocessor of the PC which can accelerate the execution of time consuming or time critical tasks such as online digital signal processing or real time hardware control. Last but not least, an open source approach as proposed in this paper is a practical approach that has demonstrated to stimulate innovative projects of high technological content. We believe it is the right choice for a complex system like the RVI platform.

FPGA

SPI to USB Controller

LP-DB-DAC controller

HP-AWG

HP-DB-DAC controller

Instructions

LP-OSC

LP-DB-ADC controller

RVI Status

HP-OSC

HP-DB-ADC controller

USB 2.0 Controller

Ethernet Controller

RS232 Controller

LED Display Controller

High speed point to point connections

Figure 8. Block diagram of a more complex Reconfigurable Virtual Instrumentation system

To Extension Connectors

LP-AWG

Bus arbiter with DMA capabilities

Wishbone RVI Bus

Dual Port Memory

RVI CONTROLLER

Parameter

Register

Parallel Port

External SDRAM Controller

Conference on Field-Programmable Technology (FPT’03) , December 2003, pp. 296–298.

6. Acknowledgment The authors wish to thank Jorge Hernán López Botero from the Universidad de Antioquia, Medellín, Colombia for his involvement in this project during his visit to the ICTP, mainly engaged in the development of the standard waveform generator, the CORDIC algorithm, and its LabView interface.

[7]

M.J. Moure, M.D. Valdés, and E. Mandado, “Educational Applications of Reconfigurable Hardware Based Virtual Instruments,” in the 29th ASEE/IEEE Frontiers in Education Conference, November 1999, pp. 12C6/17.

[8]

M.D. Valdés, M.J. Moure, C. Quintáns, and E. Mandado, “A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications,” in the International Conference on Field-Programmable Logic and Applications (FPL), September 2003, pp. 1107–1110.

[9]

The OpenCores organization at http://www.opencores.org.

7. References [1]

[2]

S. Hauck, "The roles of FPGAs in reprogrammable systems", Proceedings of the IEEE, April 1998, pp. 615– 638. G. Spivey, S.S. Bhattacharyya, K. Nakajima, Logic Foundry: A rapid prototyping tool for FPGA-based DSP systems”, Proceedings of the Asia South Pacific Design Automation Conference, January 2003, pp. 374–381.

[10] A. M. St. Laurent, Understanding Open Source and Free

Software Licensing, O'Reilly Media Inc., ISBN 0596005814, August 2004. [11] ProASIC3E Flash Family FPGAs Datasheet, Actel Corp.,

Mountain View, CA, V0.5, April 2006. [12] U. Meyer-Baese, Digital Signal Processing with Field

[3]

R.C. Cofer, B. F. Harding, Rapid System Prototyping with FPGAs, Newnes Elsevier Publisher, ISBN 0750678666, September 2005.

[4]

H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly and L. Todd, Surviving the SOC Revolution: A Guide to Platform-Based Design, Kluwer Academic Publishers, ISBN 0792386795, November 1999.

[14] E.B. Hogenauer, "An Economical Class of Digital Filters for

G.-R. Tsai, M.-C. Lin, G.-S. Sun, and Y.-S. Lin, “Single chip FPGA-based reconfigurable instruments”, The International Conference on Reconfigurable Computing and FPGAs (ReConFig’04), September 2004.

[15] ProASICPLUS Flash Family FPGAs Datasheet, Actel Corp.,

[5]

[6]

J.-W. Hsieh, G.-R. Tsai, and M.-C. Lin, “Using FPGA to implement a n-channel arbitrary waveform generator with various add-on functions”, 2nd IEEE International

Programmable Gate Arrays, Springer, ISBN 3540211195, June 2004. [13] Principles of Sigma-Delta Modulation for Analog-to-Digital

Converters, Motorola Inc., ref: APR8/D Rev.1, 1990. Decimation and Interpolation," IEEE Transactions on Acoustics, Speech and Signal Processing, April 1981, pp. 155–162. Mountain View, CA, V5.3, May 2006.