paper, a new method of clockless time-to-digital conversion. (TDC) is proposed ... simple and contains only binary-weighted capacitor array, current source ...
2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel
A Clockless Time-to-Digital Converter Dariusz KoĞcielnik
Marek MiĞkowicz
AGH University of Science and Technology Kraków, Poland
AGH University of Science and Technology Kraków, Poland
Abstract—Existing implementations of time-to-digital converters are based on the use of reference clocks. In the paper, a new method of clockless time-to-digital conversion (TDC) is proposed where the discretized time interval is first converted to the corresponding charge packet, and next processed in the charge domain by successive charge redistribution. The proposed circuit configuration is extremely simple and contains only binary-weighted capacitor array, current source, group of controlled switches, 2 comparators and asynchronous state machine. The TDC is self-timed and does not contain the DAC.
I. INTRODUCTION With improving the time resolution due to the reduction of CMOS technology feature size, encoding signal values in the time domain has become a technique of increasing importance in modern electronic instrumentation and signal processing. Time encoding is used both in synchronous and asynchronous systems. The well-known examples of the time-based synchronous ADCs are multislope converters (especially a dual-slope ADC) that have been commonly applied for decades. In the asynchronous circuits and systems, encoding signal values in the time domain is even more significant because without independent time base in self-timed architectures, the time becomes a dependent variable in system operation. Due to recent progress of theory, the methods and algorithms for loss-free recovery of bandlimitted signals encoded in the time domain using the time-encoding machines have been developed [1], [2]. In order to transmit the time information representing asynchronous sequence of time intervals via the digital communication channel and recover the analog signal in remote location, the time sequence has to be converted into sequence of digital numbers. To provide the digital output, the information encoded in time-based parameters has to be digitized in the time-to-digital converters (TDCs). The TDCs are widely used, among others, in industrial, military, medical, and scientific applications. The examples are high energy physics experiments, laser distance meter, pressure sensors, speed sensors, etc. In particular, time-to-digital conversion is used as the second step in the asynchronous analog-to-digital converters (A-ADC) to discretize information encoded in the time-domain [3-7]. Moving the quantization process from the signal amplitude domain to the time domain allows to avoid the problems with decreasing accuracy of signal value quantization in the amplitude domain. All the known
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approaches to asynchronous analog-to-digital conversion use the clock-based TDCs where the time discretization is based on counting periods of a high frequency (local) reference clock during the discretized time intervals [3-7]. However, the time quantization based on a reference clock introduces 3 dB more quantization noise than a conventional quantization in the amplitude domain or in the time domain with synchronization of the pulse leading edge with the reference clock (e.g., in dual slope ADCs) [8]. As a result, a resolution of the A-ADC with clock-based TDC is a half bit worse than the resolution of the conventional ADC. Moreover, with the maximum error equal to ±LSB, the quantization of a given time interval may result in two different values of a digital code depending on the phase of the reference clock in relation to the beginning of the discretized time interval [8]. We propose a new method of clockless time-to-digital conversion that makes possible a significant reduction of the number of state transitions per conversion cycle. The concept of the proposed time-to-digital conversion consists in applying the binary search principle to the conversion in the time domain. To the authors’ knowledge, the proposed time-to-digital conversion method is the first attempt to implement the binary search algorithm in the time-domain. The motivation to use the time-based binary search scheme is a desire of reducing the number of state transitions in the circuit in order to reduce the power consumption. In the n-bit clock-based TDCs, used both in synchronous and asynchronous ADCs, the relationship between the number of bits of resolution and the number of clock cycles needed per a single conversion is exponential and equal to 2n. In the time-based energy-efficient ADC presented in [9]-[10], the exponential relationship of state transitions has been substituted by a linear relationship, and the number of required transitions is 5n. In the clockless TDC proposed in the present paper, a number of transitions per a single conversion is (n+2) only. Furthermore, the proposed time-todigital conversion is characterized by 3 dB lower quantization noise and a lack of uncertainty of digital code on the converter output if the asynchronous time sequence is provided to the TDC input [8]. In our approach to time-to-digital conversion, the discretized time interval is first converted to the corresponding charge packet, and next processed in the charge domain by successive charge redistribution. The proposed Successive Charge Redistribution Time-toDigital Converter (SCR-TDC) architecture is extremely simple and self-timed. The n-bit SCR-ADC is built of the binary-weighted capacitor array with (n+1) capacitors, two
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asynchronous comparators, one or two current sources, the asynchronous state machine, and a group of controlled switches. Compared to the conventional successiveapproximation ADCs, the SCR-TDC does not contain a digital-to-analog converter and does not need an external clock. Moreover, the SCR-TDC does not contain any time base and any reference voltage. The only reference used is the sum and the ratio of capacitances of the working capacitors. II. BINARY SEARCH SCHEME IN TIME DOMAIN A. Time-to-Charge Conversion The block diagram of the Successive Charge Redistribution Time-to-Digital Converter (SCR-TDC) is presented in Fig. 1, and the corresponding circuit diagrams are shown in Figures 2 and 3 in Sect. III.
Fig. 1. Block diagram of successive charge redistribution time-todigital converter (SCR-TDC).
The main component of the SCR-TDC is the binaryweighted capacitor array with a number of n+1 capacitors. Detecting a leading edge of the pulse signal provided to the SCR-TDC input causes the input capacitor Cn to be charged by the current source of constant intensity Ia (see Figs. 2 or 3). The trailing edge of the pulse, whose duration TIn is discretized, stops charging the input capacitor. Thus, the charge portion collected in the input capacitor as an intermediate variable is proportional to the time interval TIn corresponding to the pulse length. The time-to-charge conversion may be considered as the sampling process of time interval duration since the continuous signal is converted to the discrete-time signal. B. Charge-to-Digital Conversion The trailing edge of the pulse on the SCR-TDC input terminates the sampling, and starts the conversion phase. The conversion, carried out in the charge domain, consists of n steps where n is a number of bits in the digital output codeword. The charge portion collected in the input capacitor Cn and represented the discretized time interval during the sampling process is divided into a set of working capacitors C0, C1, …, Cn-1 of binary weighted capacitances where Ci+1 = 2Ci, i = 0, …, n-1, and Cn = 2Cn-1. Charge dividing consists in successive redistribution of charge portion collected in the input capacitor to working capacitors. Each working capacitor Ci corresponds to the appropriate bit bi in the output digital word. In particular, the capacitance Cn-1, equal to the half of the input capacitance Cn, is assigned to the most-significant bit (MSB), and the capacitance C0 corresponds to the least-significant bit (LSB).
In the first conversion step, the input capacitor plays a role of a source of charge that is successively moved to the largest working capacitor Cn-1 operating as the first destination capacitor. If a voltage on the capacitor Cn-1 reaches the prespecified threshold VL, then the most significant bit bn-1 is set to one. Next, the remaining charge stored in the input capacitor Cn is transferred in the second conversion step to the capacitor Cn-2 that takes over the role of the next destination capacitor. However, if the capacitor Cn is discharged before the voltage on the capacitor Cn-1 reaches the threshold VL during the first conversion step, then the most significant bit bn-1 is set to zero. Furthermore, in the second conversion step, the capacitor Cn-1 plays the role of the next source capacitor and the charge is then moved from the Cn-1 to the Cn-2. The cycle is repeated for the subsequent steps. Each conversion step produces one bit more precise discrete estimate of the input time interval. The state of bits of the output digital word are determined successively from the MSB to the LSB. In the ith conversion step, the states of the bits bn-i+1, bn-i+2, …, bn-1 are already fixed. C. Current Source and Current Destination Capacitors In each conversion step, the charge is transferred from the particular capacitor that operates currently as a source capacitor to a current destination capacitor. In fact, during the sampling process preceding the conversion, the input capacitor Cn operates as the destination capacitor. In successive conversion steps, the role of the destination capacitor is taken over by the working capacitors Cn-1,…, C0 in the order of decreasing capacitances. In each conversion step, the index of the source capacitor is lower than the index of the destination capacitor since the charge is always moved from a larger capacitor to a smaller capacitor. The status of the first source capacitor is assigned to the input capacitor Cn. As follows from the description of the proposed charge redistribution method, the role of the source capacitor is handed over in the (i+1)th conversion step to the capacitor Ci if the state of the bit bi has been fixed and set to zero. Otherwise, the index of the source capacitor is not changed in the next packet cycle. The conversion is completed after the nth step when the role of a destination capacitor plays a capacitor C0. In particular, if the input time interval length is such that the initial bits are set to one in the output digital word, then the input capacitor Cn operates as the source capacitor during the whole conversion cycle (excepting the charge portion less than LSB that may be further redistributed throughout the capacitor array to C0). On the other hand, if the converted charge packet is very small and not greater than 2*LSB (i.e., if the initial (n-1) bits are equal to zero in the output digital word), then the role of the source capacitor is switched from Cn to C1 during each conversion cycle. Generalizing, during the ith step of charge redistribution when the states of the number of (i-1) most significant bits bn-1,…,bn-i+1, are already fixed, the capacitor Cn-i operates as the destination capacitor Dest_C(i): Dest _ C (i ) = Cn −i (1)
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when i = 0, 1, …, n, and the sampling process is considered as the 0th conversion step. The status of the source capacitor denoted by Source_C(i) is assigned to the capacitor Cj, where j ≥ n−i+1 such that: Source _ C (i ) = C j (2) where n; if∀k = n − i + 1, n − i + 2,..., n : bk = 1 (3) j=® ¯min( k ; k = n − i + 1, n − i + 2,..., n : bk = 0); otherwise or alternately by the use of a recursive sequence: Dest _ C (0) = Cn
Dest _ C (i ) = Dest _ C (i ) − 1
(4)
and: Source_C(1) = Cn
(5a) Source _ C (i ); if bi = 1 Source _ C (i + 1) = ® (5b) ¯ Dest _ C (i ); if bi = 0 As follows from the formula (3), the index of the current source capacitor Source_C(i) is the index of the least significant bit among the bits whose states have been fixed and set to zero. This index depends on the state of output bits that have been already evaluated. On the other hand, the index of the destination capacitor Dest_(i) is decremented from n-1 to zero in each conversion step and is independent of the states of output bits. In Table 1, the example of the possible 6 initial steps of the conversion cycle with a specification of Source_(i) and Dest_(i) is presented. The control signals that are active in the relaxation, sampling, and during successive conversion steps are listed. These signals are referred to the converter architecture presented in Figures 2 and 3. Tab. I. Example of 6 Initial Steps of n-bit TDC Cycle Conversion Index of bit Example of step index Source_(i) Dest_(i) evaluated evaluated (i) bit states (Relaxation) (Sampling) 0 1 2 3 4 5 6
-
N
-
-
Active control signals Dall, Dn, I0,…,In CSa,In,Dn
n n n n-3 n-3 n-5
n-1 n-2 n-3 n-4 n-5 n-6
n-1 n-2 n-3 n-4 n-5 n-6
1 1 0 1 0 ...
CSb,Dn,In-1 CSb,Dn,In-2 CSb,Dn,In-3 CSb,Dn-3,In-4 CSb,Dn-3,In-5 CSb,Dn-5,In-6
D. Classes of Events in Conversion Process Two classes of asynchronous internal events occur in the process of the proposed time-to-digital conversion with successive charge redistribution. The first class of events detected by the comparator K2 signal that the current destination capacitor Dest_C(i) has been charged to the threshold voltage VL. The other class of events detected by the comparator K1 report that the current source capacitor Source_C(i) has been discharged. Thus, the comparators K2, K1 respectively signal that the voltage on the capacitors C0, C1, …, Cn-1 reaches the threshold voltage VL, or the voltage on the capacitors C1, …, Cn equals zero. The asynchronous control logic is driven only by outputs of both comparators, and by the input signal provided to the SCR-TDC input that defines instants when sampling starts and when it is terminated. Thus, the converter is self-timed and no external time base is needed to control its operation.
III. CONVERTER ARCHITECTURE The architecture of the proposed asynchronous successive redistribution charge-to-digital converter (SCR-TDC) with two current sources is presented in Fig. 2, and with a single current source in Fig. 3, respectively. The further discussion will be carried out for the converter with two current sources as a more general version. As stated, the main component of the SCR-TDC is the binary-weighted capacitor array with a number of n+1 cells. Each cell contains a capacitor Ci and three controlled switches: SGi, SLi, SHi, i = 0, 1, …, n. The cells differ from each other only by a value of the capacitance of Ci. In the ith cell, the capacitance Ci equals 2iC0, where C0 is a unit capacitance located in the cell corresponding to the LSB. The SCR-TDC contains also two comparators (K1, K2) for detection of internal events driving the self-timed conversion process, and the asynchronous state machine to produce control signals that manage charge redistribution.
Fig. 2. The SCR-TDC circuit diagram with two current sources. The controlled switch positions correspond to the relaxation phase.
Fig. 3. The SCR-TDC circuit diagram with a single current source. The switch positions correspond to the relaxation phase.
A. Converter Operation In general, the SCR-TDC operation consists in controlling the sampling process and successive charge redistribution by a dynamic reconfiguration of states of controlled switches as a response to internal events occurring in the conversion process and reported by both comparators. The switch reconfiguration is managed by the asynchronous state machine. The main task of the asynchronous state machine (ASM) is a selection of the source Source_C(i) and destination Dest_C(i) capacitors, and to establish the path between both capacitors to enable a charge transfer driven by the current
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source Ib (Fig. 2). In the proposed SCR-TDC configuration, the current source Ib input is connected to the rail H, and its output to the rail L respectively. Thus, to enable the charge transfer, the Source_C(i) is connected between the rail H and the potential VH, and the Dest_C(i) between the rail L and the ground (Fig. 2). As it will be shown further, to simplify the switch control during the conversion process, the bottom plates of all the other capacitors, except of the Dest_C(i), are also kept on the potential VH but their top plates, except the top plate of the Source_C(i), are disconnected from both rails L and H. In this way, the current source Ib is put into the path established only between the Source_C(i) and the Dest_C(i). Moving the charge results in growing the potential of the top plate of the Dest_C(i), and falling the potential of the top plate of the Source_C(i). If the former potential reaches the VL
