A CMOS Low-Noise Amplifier With Reconfigurable Input Matching ...

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 5, MAY 2009

A CMOS Low-Noise Amplifier With Reconfigurable Input Matching Network Mohamed El-Nozahi, Student Member, IEEE, Edgar Sánchez-Sinencio, Fellow, IEEE, and Kamran Entesari, Member, IEEE

Abstract—A reconfigurable low-noise amplifier (LNA) with tunable input matching network is proposed. The tunable input matching network provides continuous tuning of the input resonant circuit. The LNA is implemented using 0.13- m CMOS technology. The amplifier has a tuning range of 1.9–2.4 GHz with an input return loss better than 13 dB. The LNA has a measured voltage gain of 10–14 dB and a noise figure of 3.2–3.7 dB within the band. The LNA consumes 14 mA from a 1.2-V supply. The detailed analysis of the proposed LNA, including the tuning range and additional noise of the proposed reconfigurable input matching network, is presented. To our knowledge, this is the first architecture that provides continuous tuning of the input matching network. Index Terms—Low-noise amplifier (LNA), reconfigurable input matching network, tunable inductor.

I. INTRODUCTION ODAY, the advances in CMOS technology have guided the progress in the wireless communications circuits and systems area. Various new communication standards have also been developed to accommodate a variety of applications at different frequency bands, such as cellular communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and 1.5 GHz, and Bluetooth and WiFi at 2.4 and 5.2 GHz, respectively. The modern wireless technology is now motivated by the global trend of developing multiband/multistandard terminals for low-cost and multifunction transceivers. Wu et al. [1] reported a 900-MHz–1.8-GHz CMOS dual-band heterodyne receiver employing weaver architecture. Zargari et al. [2] demonstrated a dual-band heterodyne CMOS receiver for 2.4/5.2-GHz wireless local area network (WLAN) applications using sliding IF architecture. Ko et al. [3] reported a CMOS 1.2/1.5-GHz dual-band heterodyne GPS receiver with dual-conversion architecture. Chen et al. [4] used the concept of dual-band concurrent receiver [5] for GPS and Bluetooth applications. The main goal in these receiver architectures is to share as many building blocks as possible for the various standards to reduce the cost and area of the handheld devices. One of the challenging building blocks in multiband/multistandard receivers is the low-noise amplifier (LNA). Parallel,

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Manuscript received June 30, 2008; revised January 30, 2009. First published April 14, 2009; current version published May 06, 2009. The authors are with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843 USA (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2009.2017249

concurrent, or wideband LNAs are the commonly used approaches employed in multifunction receivers [1], [5]–[8]. Parallel LNAs are achieved by using several LNAs for each band/standard [1]. This approach requires an additional area for various LNAs in addition to switches for band selection, which increases the complexity of the receiver. Concurrent LNAs provide dual input matching at two different frequency bands [5], and wideband LNAs provide wideband matching [7]. Concurrent and wideband LNAs occupy less area at the cost of higher requirement on the 1-dB compression point, and hence, higher power consumption. Solving the tradeoff between area and power consumption for multiband/multistandard LNAs is currently a main challenge. Recently, a new approach for designing switchable LNAs has been proposed to solve this dilemma [9]. This approach provides discrete tuning. However, this is not efficient for selecting a large number of bands because it relies on adding a new inductor for each additional band; hence, increasing the area of the LNA. A multiband positive feedback LNA for the UMTS, 802.11b-g and DCS1800 standards was reported [10]. This approach uses a common gate topology along with a positive feedback to provide the discrete tuning of the input matching network for the three bands. In this approach, stability is an important factor that needs to be carefully considered during the design phase. The approach results in high noise figure (NF) and power consumption. The linearity of this approach is also limited as a result of the positive feedback, which reduces the overdrive voltage across the main transistor. Another approach was reported for the 750-MHz–3-GHz frequency range [6]. The reconfigurable LNA uses a two-stage architecture where the first stage is a wideband LNA and the second stage provides band selection through an active recursive bandpass filter. The main advantage of this approach is removing any on-chip inductor. However, this approach results in high NF, low linearity, and high power consumption. In this paper, a new continuous reconfigurable LNA is proposed. Continuous tuning is preferred over discrete tuning, as in [9] and [10] because it is less sensitive to process variations. Any shift in the performance can be electronically tuned using the proposed architecture. In addition, for a larger number of frequency bands, discrete tuning is not suitable, as it is harder to design for good input matching and it necessitates additional components (such as inductors), which increases the overall area of the LNA. The proposed LNA is characterized by its continuous tuning, lower NF compared to the active recursive bandpass filter, and the positive feedback approaches in [6] and [10], respectively. Similar linearity is achieved when compared to the

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EL-NOZAHI et al.: CMOS LNA WITH RECONFIGURABLE INPUT MATCHING NETWORK

Fig. 1. Conventional narrowband LNA architecture (biasing is not shown).

single-band LNAs. In addition, the presented architecture does not require higher linearity similar to the wideband approach due to its narrowband nature. The proposed tuning technique is not only suitable for tuning the matching network, but also can be used to scale the inductance value for any application. This paper is organized as follows. In Section II, the motivation and background are stated. The basic theory for the tunable inductor and tunable input matching network is presented in Section III. The overall architecture and the analytical expressions for the proposed LNA are then shown in Section IV. The simulations and measurement results are discussed in Section V. Finally, results are concluded in Section VI. II. MOTIVATION The common approach for designing a narrowband LNA is to use a cascode amplifier with inductive degeneration, as shown in Fig. 1 [11]. This architecture provides simultaneous input matching and low NF. The output tank circuit is tuned to the required band, and the input series resonant circuit is adjusted to provide sufficient matching at the desired frequency band. For this LNA, the input impedance is approximately calculated from [11] (1) where is the frequency of operation in radians per seconds, is the transistor cutoff frequency in radians per seconds, and is the gate–source capacitance of the main transistor . The real part of the input impedance is adjusted using the source inductor , while the imaginary part is removed at the resonant frequency using the inductor . and the gain at the resonance freThe NF quency are obtained by [11] (2) (3) (4)

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is the zero bias drain transconductance of , where is the noise coefficient, is the excess noise factor due to is the source resistance, and is the load the gate noise, resistance. The NF defined in (2) is the lowest NF that can be obtained from this architecture, while the input is perfectly matched and the output is tuned to the operating frequency [11]. The same conclusion holds for the gain defined in (3). These results indicate that the performance of the narrowband LNA depends on the resonant frequency, which is adjusted using the inductor at the input matching network, and inductor and capacitor at the output tank circuit. To achieve an LNA with optimum performance (gain, NF, and linearity) across a wide frequency range, the inductor or the capacitor has to be changed for each operating frequency. Tuning the value of changes the cutoff frequency, should also be tuned to achieve the and hence, the inductor does not reperfect matching. On the other hand, tuning is a quire any additional component to be tuned. Tuning challenging problem because the additional circuitry should not increase the NF, degrade the linearity, or affect the gain of the LNA. In addition, it is not trivial to tune a floating inductor. One simple approach is to place several inductors in parallel and switch among them. In this case, the active switch loss and its nonlinear behavior degrade the NF and linearity of the LNA considerably. On the other hand, switching among various inductors does not provide a continuous tuning scheme. In this is proposed. This paper, a new tuning scheme for the inductor tuning scheme is applied to the narrowband LNA to achieve a reconfigurable input matching network. The load of the LNA can be either a tunable tank circuit with a bank of capacitors or a wideband load over the tuning range. In this paper, two resonant circuits are used to provide a constant load across the frequency range. III. TUNABLE FLOATING INDUCTOR A. Basic Idea Fig. 2(a) shows a model for the conventional input matching network of the LNA. In this model, the input impedance of the . As discussed in LNA is combined into a single term Section II, the input matching network is tuned by changing . To achieve this goal, the input the value of the inductor matching network is modified according to Fig. 2(b) where an ideal amplifier is placed to provide the necessary scaling for . The input impedance of this architecture is calculated from (5) is the voltage gain of the amplifier, and is an where impedance used to change the gain of the amplifier, as discussed is scaled by later in this section. Based on (5), the inductor . Depending on the the amplifier with the factor polarity of the gain, the inductor value can either increase or decrease. In this architecture, the common node of the amplifier [node in Fig. 2(b)] is floating and not connected to the ground of the circuit.

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Fig. 2. (a) Input matching network of the conventional LNA. (b) Proposed tunable floating inductor basic architecture. Fig. 4. Effective inductance value versus the tuning coefficient

10 nH and f = 1 GHz) for the architecture shown in Fig. 3(a).

x (L =

(8) where is the effective inductance and resistance that appear due to this architecture. coefficient defined as

is the nonideal is the tuning (9)

Fig. 3. (a) Proposed tunable floating inductor architectures based on a common drain configuration (C is decoupling capacitor). (b) Equivalent RL model of the common drain tunable architecture.

B. Practical Implementations Several approaches can be used to implement the proposed amplifier. A common drain configuration is considered, and the associated nonidealities and their effect in the inductance tuning is presented. Common source configuration is not applied because it leads to higher NF. Common gate architecture is not considered because it has a small input impedance, which affects the overall input impedance of the architecture shown in Fig. 2(b), and therefore, the tuning of the inductor. 1) Common Drain Configuration: The common drain configuration is shown in Fig. 3(a), where the common node is is replaced by connected to the node . The impedance to provide the necessary inductance a variable resistance tuning. This resistance is implemented using a transistor biased . Transistor is the main transistor in the triode region of the common drain amplifier. The biasing of this stage is done through an RF choke coil to lower the NF of the LNA. The input impedance of this architecture is calculated from

(6) where is the transconductance of the main transistor. in (5) is Note that for a common drain configuration. As can be noticed, the ideal model in (5) does not predict the additional resistive term in (6). This additional resistive term in (6) is due to the finite output impedance of the amplifier, which was not considered in the basic idea for simplicity. The proposed tunable architecture equivalent circuit, as shown in can be modeled by a series Fig. 3(b), with (7)

Equation (7) shows that this architecture reduces the effective inductance value by either increasing the transconductance or the resistance . Fig. 4 shows versus the tuning coef. This simulation is performed using Spectre1 for ficient GHz and nH, where the transistor is replaced with an ideal voltage controlled current source. For is larger than the common drain configuration, real inductor ; however, having a larger inductor is better if compared to having several inductors in parallel for band selection. The introduces additional loss, which nonideal resistive term lowers the quality factor of the tunable inductor. In this case, the for the ideal inductor effective quality factor is found as (10) The quality factor in this architecture does not depend on , and it depends only on the resisthe transconductance of . It should be mentioned that the parasitic capacitance tance changes the inductive behavior of the proposed tunable inductor architecture at higher frequencies. Therefore during circuit simulations, it is important to take into account this nonideal effect. In this implementation, the additional circuit consumes 40% of the total power. The noise contribution of the additional tuning circuit mainly depends on the additional power consumption. The noise contribution of the tuning circuit and its dependency to the tuning range will be discuss in Section IV. IV. RECONFIGURABLE LNA The complete architecture of the proposed reconfigurable LNA is shown in Fig. 5. In this architecture, the reconfigurable input matching network is realized using the tunable inductor common drain configuration discussed in Section III-B. The output load is realized using two resonant circuits, each tuned at a different frequency. This approach increases the bandwidth of the load to cover the frequency range; however, the effective load 1Spectre

5.1, Cadence, 2007.



Fig. 6.

g

Fig. 5. Proposed reconfigurable LNA (biasing circuit not shown).

resistance (gain) is reduced. Placing the two resonant circuits farther apart results in a nonconstant load with respect to frequency. Hence, this approach is not suitable for covering a large bandwidth. For a larger bandwidth, it is preferred to use a bank of capacitors and a varactor for narrowband output tuning.

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R (x

versus the tuning factor g 1 R ).

=

x

for either changing

R

or

and keeping the transconductance increasing the resistance constant, while it decreases when the transconductance is increased . The first case does not change the power consumption is constant, while the latter changes the power since consumption when the tuning frequency is changed. Hence, for good matching along a wide tuning range, it is better to change and keep the transconductance as high the resistance value as possible to keep nearly constant over the tuning range. B. Gain

A. Input Impedance

The gain of the LNA,

The input impedance of the LNA in Fig. 5 is

, at resonance is found to be (14)

(11) For this case, the resonant frequency and the input impedance at resonance are determined from the following equations:

(12)

(13) Equation (12) shows that for frequency tuning, either the resistance or the transconductance can be changed. The , which appears due to the tuning additional resistive term circuit, can be considered as part of the real input impedance can be designed for a value to adjust the matching, i.e., less than 50 . does not affect the gain of the amplifier, as will be shown later. It is important to mention that the real part changes with the resonant frequency due to changing of , and therefore, perfect matching cannot be obtained along the entire frequency range. Fig. 6 shows the change of the effecversus the tuning factor based on (13) tive resistance or the transconductance is changed. if either the resistance As can be noticed, the effective resistance increases in case of

Under the perfect matching condition , the overall gain of the LNA reduces to (15) is the total load resistance at the drain of the tranwhere . The above equation is similar to the gain of the narsistor rowband LNA with inductive degeneration, as shown in (3), and therefore, this technique does not affect the overall gain of the LNA. C. NF Fig. 7 shows the main noise sources that contribute to the NF of the LNA. The main noise sources are due to the main , the resistance , and the transistor . The transistor noise current due to the transistor and the resistance circulates in the loop consisting of and . A small fraction of this noise is injected inside the main circuit of LNA, and therefore, the additional circuit does not increase the NF significantly. The contribution of each noise component is calculated below. The equivalent input referred noise spectral density due to the resistance under perfect matching is calculated from condition


(16)

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Fig. 8. Left axis: input referred noise density of R . Right axis: required tuning coefficient x versus the value of R for two cases, where Z (f ) = 50 (! 1 L = 10 and ! 1 L = 20 ). Fig. 7. Main noise sources for the proposed reconfigurable LNA.

where is the Boltzmann constant and is the temperature in can be reduced by inkelvin. The noise of the resistance or increasing . Fig. 8 shows the creasing the factor versus equivalent input referred noise spectral density of its value for two cases ( , and , ). Increasing the value of reduces the equivalent input referred noise on the cost of in, and hence, the power creasing the transconductance consumption of the tunable inductor stage. Therefore, there is a tradeoff between the NF and power consumption for the proand are deterposed architecture. The values of mined from (13). The second noise source in this architecture is the noise contributed by the transistor . The equivalent input referred and noise spectral density due to the gate noise under perfect matching drain thermal noise condition are

Fig. 9. Left axis: input referred noise density of M . Right axis: required for two cases, where tuning coefficient x versus the value of g Z (f ) = 50 (! 1 L = 10 and ! 1 L = 20 ).

ysis shows that the total equivalent input referred noise density , is due to

(18)

(17)

where is the shunt gate conductance, is the gate noise coef[11]. Both the above noise sources can ficient, and be combined in a single expression that considers the correlation between the gate and drain noise. The mathematical anal-

where is the correlation coefficient of the gate and drain noises [11]. Fig. 9 shows the change of the input referred noise density versus for two cases ( , of and , ). As indicated in this increases the input referred noise beplot, increasing is required to achieve the 50 recause higher value of quired matching. In addition, the tuning coefficient increases with the increase of . The above analysis shows that the input referred noise depends on both , , and . The analysis also shows increasing lowers the noise contributions of , and , as depicted in Figs. 8 increases the noise contribution of and 9, respectively. Hence, there is an optimum solution for the design parameters ( , , and ) that minimizes the



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additional noise due to the tuning circuit for a given power consumption. This issue is addressed in more detail in Section IV-D. The total noise spectral density due to the additional tuning ciris found by adding the two input referred noise cuitry voltages in (16) and (18), resulting in

(19) Assuming that the input referred noise spectral density of the , additional circuitry is less than a specified value (19) is rearranged to find the value of the required transconductance

(20) The above equation shows that there is a minimum value for the transconductance to satisfy the noise constraints if the tuning is specified. This minimum value leads to mincoefficient imum power consumption of the additional circuitry. The value is then calculated from . The optimum of the resistance value for the tuning coefficient is determined from the tuning range, as will be discussed in Section IV-D. The final major noise source, which contributes to the total . For this case, the NF, is the noise of the main transistor amount of noise that appears at the output is the same as the conventional LNA with inductive degeneration. Therefore, the input referred noise spectral density under a perfect matching condition is [11]

Fig. 10. Required g versus the percentage contribution of additional tuning circuit for different input mismatch values (NF = 3 dB; = 2).

in higher transconductance, and hence, higher power consumption (Fig. 6). In the actual design, the tuning coefficient is not much higher than one, leading to a mismatch at the input of the LNA. Therefore, there is a tradeoff between the mismatch and the power consumption of the additional circuitry along the tuning range. To find the optimum design parameters of the proposed architecture for a defined mismatch, a numerical approach has been developed. This numerical approach relies on solving a set of equations to find the minimum power consumption for along a given mismatch and tuning range. The mismatch with the tuning range is estimated from the following equation:

(23) where subscripts and denote the higher and lower frequency for the proposed LNA bands, respectively. The tuning range is derived from (12), and is

(21) Combining (16), (17), and (21), the total NF of the LNA is

(24) Equations (23) and (24) are two equations with three unknowns ( , , and ), and therefore, they cannot be solved to find the optimum solution. The third equation is the one defined in (20), where the high tuning coefficient is written in terms of the transconductance as follows:

(22) The last term in the above equation is the noise introduced by due to its finite the series physical resistance of the inductor quality factor. As depicted, the additional noise is reduced when is increased. For off-chip inductors, this term is smaller than the other noise sources. D. Tuning Range and Input Mismatch The frequency of operation depends on the value of and . Changing either of these two values changes the input resonant frequency. However, this change varies the real input impedance, as described in (13). Smaller variations in the real input impedance require larger tuning coefficients, which results

(25) In the above equation, is only considered because it results in a higher input referred noise, while for , lower input referred noise is obtained. The set of the equations in , (23)–(25) are solved numerically to find the values of , and , and hence, and . For our design, the targeted tuning range is 1.9–2.4 GHz and the overall NF is versus 3 dB. Fig. 10 shows the numerically calculated the percentage noise contribution of the additional circuitry for different misto the total input referred noise match values . As depicted in Fig. 10, the required


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Fig. 11. Die microphotograph of the reconfigurable LNA. Fig. 13. Measured and simulated S of the reconfigurable LNA for different tuning frequencies. (L: lower band, I: intermediate band, U: upper band).

Fig. 12. PCB model of the measured LNA. The RF input and output signals are measured using the probes.

transconductance increases for lower noise contribution. This presents the tradeoff between the NF and power consumption of the proposed tuning circuit. The gray area represent the is negative. This value is not realizable with region where the common drain configuration. For this design, a 35% noise of 6 are assumed. This contribution and a mismatch results in an increase of 40% of the total power consumption of the reconfigurable LNA due to the additional circuit when compared to a single-band LNA. For this case, the calculated is 46 mS, is 1.2, and is 0.38, which result in and of 24.5 and 7.2 , respectively. It is important to mention that this technique is valid for a wide tuning range by properly selecting the tuning coefficient.

Fig. 14. Measured and simulated voltage gain versus the frequency. (L: lower band, I: intermediate band, U: upper band).

Fig. 15. Measured and simulated NF versus the tuning frequency.

V. SIMULATION AND EXPERIMENTAL RESULTS The reconfigurable LNA is fabricated using 0.13- m CMOS technology provided through the United Microelectronics Corporation (UMC), Hsinchu, Taiwan. The chip is encapsulated in a quad flat no leads (QFN) package for connecting the external components of the LNA including . The RF signal is applied and monitored using on-wafer probing to reduce the losses and mismatches introduced by the measurement setup. The die micrograph is presented in Fig. 11, where the total area including the pads is 0.52 mm . The active area for the integrated devices and inductors is 0.083 mm . The effect of the output buffer is deembedded from the Buffer measurements using the measurement results of a fabricated standalone buffer. The complete schematic of the LNA including the external components, bonding, and printed circuit board (PCB) parasitics is shown in Fig. 12. A buffer is added at the output of the LNA to drive the 50- input impedance of the network anis implemented using the wire bond alyzer. The inductor

Fig. 16. Two-tone IIP3 measurement result (f = 2 GHz).

inductance. The package and bonding effects are modeled by an LC network, and it is assumed that 1 mm of bonding wire length is approximately 1 nH, and the pin capacitance is approximately 150 fF. An FR-4 PCB is used, and PCB traces are modeled using an equivalent LC circuit. Modeling the external



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TABLE I PERFORMANCE SUMMARY OF THE PROPOSED RECONFIGURABLE LNA AND COMPARISON WITH THE EXISTING WORK

components helps during the design phase to optimize the targeted performance after the measurement. The RF signals are applied and monitored using ground–signal–ground (GSG) RF probe to characterize the performance of the LNA. The circuit -parameters are measured using an HP8719ES network analyzer. Fig. 13 shows the measured and simulated for different tuning frequencies. As noticed, is lower than dB for the entire frequency range from 1.9 to 2.4 GHz. This frequency range is suitable for the personal communications system (PCS) standard at 1.9 GHz and various other standards at 2.4 GHz. The input tuning frequency is changed using the control voltage , which changes the equivalent resistance of . As depicted from Fig. 13, the simulated and the transistor measured results matched over the same tuning range because of the accurate modeling of the PCB and bonding parasitics. Fig. 14 shows the voltage gain after deembedding the buffer effect. The measured voltage gain is between 10–14 dB for 1.9–2.4-GHz frequency bands. Both simulated and measured voltage gains have the same behavior; however, the measured gain is about 2 dB lower than the simulated one. This difference or transconduccould be due to the lower load resistance as a result of process variations. tance The NF versus the tuning frequency is shown in Fig. 15, where the NF varies from 3.2 to 3.7 dB. The higher measured NF is mainly due to the lower gain of the LNA and the inaccuracy of the provided technology noise models. Having a tuned output load instead of the wideband one reduces the NF by 1 dB based on our simulation results. A two-tone third-order intermodulation intercept point (IIP3) measurement is performed for the LNA and the result is shown in Fig. 16 for at 2 GHz. The two tones are applied with the same amplitude and a frequency offset of 10 MHz. The measured IIP3 is 6.7 dBm, and is limited by the transistor . The measurement shows that IIP3 is almost constant for the entire tuning range. The LNA consumes 14 mA from a 1.2-V supply. The main LNA section consumes 8 mA, and the additional circuitry for tuning consumes 6 mA. The performance of the proposed LNA and comparison with the existing tunable architecture are summarized in Table I. As depicted in this table, the proposed reconfigurable LNA provides continuous tuning of the input matching network, while the other existing techniques either provide discrete tuning or wideband matching. The power consumption for the proposed architecture is higher when compared to [9] because an active circuit is used for tuning the inductor. To analyze another case, the circuit is designed for a wide tuning range with a reconfigurable load. Table I summarizes

the performance summary for the post-layout simulated wide tuning-range LNA. For this case, the output load is a resonant circuit, and the output tuning frequency is changed by means of a bank of capacitors and a varactor for coarse and fine tuning, respectively. This design example shows lower NF when compared to design 1 because the gain is higher and the noise contributed by the load resistance is lower. Design 2 demonstrates the extension of the proposed approach for wider tuning ranges to support various standards that appear in this frequency range. In addition, it is not easy to design a discrete input matching network that can provide this wide/fine-tuning range functionality. VI. CONCLUSION A reconfigurable LNA with continuous tuned input matching network was presented in this paper. By means of an inductor tuning circuit, a tunable narrowband LNA is obtained. The detailed analysis of the LNA, including the tuning range and additional noise of the proposed reconfigurable input matching network, was presented. In addition, a design methodology for minimizing the power consumption of the additional tuning circuit was proposed. This methodology was used to design and implement a reconfigurable LNA along the frequency band of 1.9–2.4 GHz. The 0.13- m CMOS technology was used to implement the LNA, which consumes 14 mA from a 1.2-V supply. Measured performance shows an input matching better than dB, a voltage gain of 10–14 dB, and an NF of 3.2–3.7 dB over the tuning range. In addition, post-layout simulations of a wide-tuning range LNA is also presented in this paper; the input matching network is tunable from 2.4 to 5.2 GHz. This paper demonstrates the first technique for continuous tuning of the input matching network. This technique results in multiband LNAs that are smaller in area than either concurrent or switchable LNAs, and superior in performance to wideband LNAs. In addition, the proposed technique is not only suitable for tuning the matching network, but can be generally used to scale the inductance value for any application. REFERENCES [1] S. Wu and B. Razavi, “A 900 MHz/1.8 GHz CMOS receiver for dualband applications,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2178–2185, Dec. 1998. [2] M. Zargari, M. Terrovitis, S. H.-M. Jen, B. J. Kaczynski, M. P. MeeLan Lee Mack, S. S. Mehta, S. Mendis, K. Onodera, H. Samavati, W. W. Si, K. Singh, A. Tabatabaei, D. Weber, D. K. Su, and B. A. Wooley, “A single-chip dual-band tri-mode CMOS transceiver for IEEE 802. 11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2239–2248, Dec. 2004.


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[3] J. Ko, J. Kim, S. Cho, and K. Lee, “A 19-mW 2.6-mm L1=L2 dualband CMOS GPS receiver,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1414–1425, Jul. 2005. [4] P. D. Chen, C. H. Chen, W. M. Chang, K. H. Cheng, and C. F. Jou, “A dual-band concurrent RF front-end receiver design for GPS and Bluetooth applications,” in Proc. Asia–Pacific Microw. Conf., Dec. 2005, vol. 2. [5] H. Hashemi and A. Hajimiri, “Concurrent multiband low-noise amplifiers-theory, design, andapplications,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 288–301, Jan. 2002. [6] S. Andersson and C. Svensson, “A 750 MHz to 3 GHz tunable narrowband low-noise amplifier,” in Proc. NORCHIP Conf., Nov. 2005, pp. 8–11. [7] I. Ismail and A. A. Abidi, “A 3–10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2269–2277, Dec. 2004. [8] M. Liu, J. Craninckx, N. M. Iyer, M. Kuijk, and A. R. F. Barel, “A 6.5-kV ESD-protected 3–5-GHz ultra-wideband BiCMOS low-noise amplifier using interstage gain roll-off compensation,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 4, pp. 1698–1706, Apr. 2006. [9] V. K. Dao, Q. D. Bui, and C. S. Park, “A multi-band 900 MHz/1.8 GHz/5.2 GHz LNA for reconfigurable radio,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2007, pp. 69–72. [10] A. Liscidini, M. Brandolini, D. Sanzogni, and R. Castello, “A 0.13 m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 981–989, Apr. 2006. [11] D. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997. Mohamed El-Nozahi (S’00) received the B.Sc. and M.Sc. degrees in electrical engineering from Ain Shams University, Cairo, Egypt, in 2000 and 2004, respectively, and is currently working toward the Ph.D. degree in integrated circuits and systems at Texas A&M University, College Station. From 2000 to 2004, he was a Teaching and Research Assistant with the Electronics and Communications Engineering Department, Ain Shams University. Since 2006, he has been with Texas A&M University. In Summer 2007, he was a Design Intern with Texas Instrument Incorporated, Dallas TX. His research interests include transceivers system and circuit design at millimeter-wave frequencies and power management ICs. Mr. El-Nozahi was the recipient of the 2009 Semiconductor Research Corporation (SRC) Design Challenge Award.

Edgar Sánchez-Sinencio (F’92) was born in Mexico City, Mexico. He received the Communications and Electronic Engineering degree (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, Mexico, in 1966, the M.S.E.E. degree from Stanford University, Stanford, CA, in 1970, and the Ph.D. degree from the University of Illinois at Champaign-Urbana, in 1973. He is currently the TI J. Kilby Chair Professor and Director of the Analog and Mixed-Signal Center with Texas A&M University, College Station. His current interests are in the area of power management, RF communication circuits, and analog and mixed-mode circuit design. Dr. Sánchez-Sinencio was the editor-in-chief of THE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING. He was the IEEE CAS’s representative to the IEEE Solid-State Circuits Society (2000–2002). He was a member of the IEEE Solid-State Circuits Society Fellow Award Committee (2002–2004). He was the recipient of an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Puebla, Mexico, In 1995, which was the first honorary degree awarded for microelectronic circuit design contributions. He was a corecipient of the 1995 Guillemin-Cauer for his work on cellular networks and the 1997 Darlington Award for his work on high-frequency filters. He was also the recipient of the 1999 IEEE Circuits and Systems Society (CAS) Golden Jubilee Medal and the IEEE CAS 2008 Technical Achievement Award. He is a former IEEE CAS vice president of publications.

Kamran Entesari (S’03–M’06) received the B.S. degree in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 1995, the M.S. degree in electrical engineering from the Tehran Polytechnic University, Tehran, Iran, in 1999 and the Ph.D. degree from The University of Michigan at Ann Arbor, in 2005. In 2006, he joined the Department of Electrical and Computer Engineering, Texas A&M University, College Station, where he is currently an Assistant Professor. His research interests include the design of RF/microwave/millimeter-wave integrated circuits and systems, RF microelectromechanical systems (MEMS), related front-end analog electronic circuits, and medical electronics. Dr. Entesari was the recipient of the Semiconductor Research Corporation (SRC) Design Contest Second Project Award for his work on dual-band millimeter-wave receivers on silicon.
