three valued memory cells. The ROM has been contacts are shared. designed for use in a ternary digital system. It is a 21 87x5 trit, contact programmed device.
A CMOS TERNARY ROM CHIP
Y.H.
Cho and H.T. Mouftah
Dept. o f E l e c t r i c a l E n g i n e e r i n g Q u e e n ' s U n i v e r s i t y a t Kingston K i n g s t o n , O n t a r i o K7L 3N6 ABSTRACT T h i s p a p e r p r e s e n t s a r e a d o n l y memory b a s e d o n t h r e e v a l u e d memory c e l l s . T h e R O M h a s b e e n It designed f o r use i n a t e r n a r y d i g i t a l system. i s a 21 8 7 x 5 t r i t , c o n t a c t programmed d e v i c e . The N o r t h e r n T e l e c o m CMOS 3 m i c r o n , d o u b l e m e t a l process has been used i n t h e implementation of t h e device. 1 . INTRODUCTION Read O n l y M e m o r i e s ( R O M s ) a r e used
for many p u r p o s e s i n d i g i t a l systems. Microprogramming and program code are t h e usual c o n t e n t s f o r ROMs b u t l o g i c f u n c t i o n s may a l s o be implemented u s i n g t h e ROM
.
T h i s paper p r e s e n t s a ROM u s i n g t h r e e - v a l u e d memory cells. The R O M has been designed f o r a t e r n a r y d i g i t a l s y s t e m a n d t h e r e f o r e has b o t h t e r n a r y i n p u t s and o u t p u t s . I t h a s b e e n s u b m i t t e d f o r f a b r i c a t i o n t o t h e N o r t h e r n Telecom S i l i c o n f o u n d r y t h r o u g h t h e Canadian M i c r o e l e c t r o n i c s C o r p o r a t i o n . 1.1 P r e v i o u s ROM Designs The ROM h a s a m a j o r a d v a n t a g e o v e r o t h e r memory d e v i c e s . T h i s f e a t u r e is t h e n o n - v o l a t i l e n a t u r e o f t h e memory d e v i c e . I f t h e power s u p p l y i s s h u t o f f , t h e ROM w i l l r e t a i n d a t a . T h i s makes t h e d e v i c e well suited for storing data which should be k e p t i n t h e s y s t e m f o r a l o n g p e r i o d of time, a n d especially when t h e system power s u p p l y i s s h u t off. The R O M achieves t h i s b y s t o r i n g t h e b i t s as d e v i c e s o r c o n t a c t s i n a memory m a t r i x . The t y p i c a l representation would be t h e p r e s e n c e o f a
t r a n s i s t o r i f t h e memory location were t o store a zero and the absence of a transistor if t h e memory l o c a t i o n were t o s t o r e a one. There a r e two b a s i c ROM s t r u c t u r e s , t h e N O R a r r a y a n d t h e N A N D a r r a y CHODG831. The NAND s t r u c t u r e is very a n d a c h i e v e d by u s i n g s e r i a l l y c o n n e c t e d t r a n s i s t o r s i n the memory matrix. This structure, w i t h the load, yields a N A N D g a t e . The NOR s t r u c t u r e u s e s t h e memorv m a t r i x t r a n s i s t o r s i n a p a r a l l e l s t r u c t u r e . ~ 1 t " h o u ~t hh e g e o m e t r i c l a y o u t s d i f f e r , t h e f u n c t i o n a l o p e r a t i o n o f most ROMs f o l l o w e i t h e r t h e NAND o r NOR arrangement. E a r l y ROMs a r e based on an a r r a y of t r a n s i s t o r s , a r r a n g e d i n r o w s a n d c o l u m n s [HNAT77]. T h i s h a s made t h e l a y o u t o f t h e d e v i c e s v e r y s i m p l e b u t h a s not y i e l d e d t h e most a r e a e f f i c i e n t l a y o u t available.
The n e x t s t e p i n minimizing t h e a r e a o f t h e memory c e l l h a s been t h e u s e o f s h a r e d c o n t a c t s CHNAT771. The r e g u l a r a r r a y s t r u c t u r e i s m a i n t a i n e d b u t t h e contacts a r e shared.
to a The array type s t r u c t u r e has been Stage where the area t h i s type Of structure Occupies has been m i n i m i z e d . I t was e v i d e n t t h a t f u r t h e r m i n i m i z a t i o n o f a r e a would be p o s s i b l e o n l y i f t h e b a s i c c e l l s t r u c t u r e was c h a n g e d . T h i s f u r t h e r m i n i m i z a t i o n h a s been a c h i e v e d by t h e u s e o f t h e X-cell s t r u c t u r e . The u s e o f v i r t u a l grounds a n d t h e arranging transistors so that form an X around s h a r e d c o n t a c t s h a s minimized a r e a CPR1N831' Obviouslv. - . t h e o n l -v way - t o further increase density reduce the s i z e ' This is a w i t h b i n a r y ROMs. The d a t a c a p a c i t y o f t h e b i n a r y R O M i s d e p e n d e n t on t h e c o n t i n u e d r e d u c t i o n of t h e transistor
size.
Some d e s i g n e r s h a v e c o n c e n t r a t e d on a t t e m p t i n g t o p l a c e more d a t a p e r memory c e l l . I f a memory c e l l c a n be d e s i g n e d t o h o l d more d a t a than t h e usual one b i t , y e t m a i n t a i n a p p r o x i m a t e l y t h e s a m e s i z e , t h e n h i g h e r d a t a d e n s i t y can be a c h i e v e d . T h i s may b e p o s s i b l e by t h e u s e o f m u l t i - v a l u e d l o g i c design. One o f t h e f i r s t m u l t i - v a l u e d d e s i g n s h a s been used i n t w o I n t e l c h i p s . The 8087 numeric co- p r o c e s s o r and t h e I n t e l 432 1 1 0 ~ r o c e s s o rb o t h . u s e a n nmos ROM based on f o u r - v a l u e d c e l l s CAGAR841. M o t o r o l a h a s a c o m m e r c i a l d e v i c e , t h e MCM65256, i s a four-va1ued R O M 1 b a s e d On a combination of multi-valued c e l l s and an X-cell t y p e s t r u c t u r e CDON0851. General I n s t r u m e n t s a l s o r e a l i z e d a ROM w i t h t h e s a m e d a t a c a p a c i t y . T h i s d e v i c e is a l s o based on t h e four-valued c e l l [RICH86][RICH85]. At another R O M based O n t h e f o u r s t a t e memory c e l l h a s been p r e s e n t e d CETIE851. I t is a s m a l l d e v i c e , o f f e r i n g 1K b y t e s of s t o r a g e . I t is based o n t h e o l d e r a r r a y t y p e s t r u c t u r e , b u t h a s contacts.
C o n c e n t r a t i n g on t e r n a r y s y s t e m s , two p r e v i o u s ROMs h a v e b e e n d e s i g n e d . Mouftah [MOUF77] based h i s ROM d e s i n n on a s t r u c t u r e c a l l e d t h e M o d i f i e d T e r n a r y in the lnv'rter (MT1)' Each a n-type d e v i c e , a p- type d e v i c e a n d a ''Itage d i v i d e r . T h e p o s i t i o n O f the ' O n t a c t determines the programming Of the A n o t h e r t e r n a r y ROM d e s i g n i s b a s e d o n t h e
t r a n s m i s s i o n g a t e [MOUF84]. I n t h i s c a s e , t h e a t r a n s m i s s i o n g a t e connected t o memory c e l l e i t h e r t h e high o r low power supply. The o u t p u t of t h e g a t e i s connected through a r e s i s t o r t o ground t o provide t h e i n t e r m e d i a t e l e v e l . The programming o f t h e c e l l is accomplished by connecting t h e g a t e t o t h e low, o r high power s u p p l y f o r t h e low and h i g h s t a t e s r e s p e c t i v e l y , and l e f t unconnected i f t h e middle s t a t e -is t o be t h e o u t p u t .
is
1.2 Programming I s s u e s Programming a ROM is an important c o n s i d e r a t i o n . I f t h e s t e p which implements t h e programming can be kept t o One Of t h e l a s t p r o c e s s i n g s t e p s i n f a b r i c a t i o n , t h e n t h e a c t u a l firmware development may c o n t i n u e d u r i n g t h e i n i t i a l s t a g e s of c h i p fabrication. E a c h o f t h e a b o v e ROM t y p e s a r e p r o g r a m m e d d i f f e r e n t l y . The e a r l i e s t ROMs have t h e programming done a t one of t h e l a s t s t a g e s i n p r o c e s s i n n ; t h e m e t a l l i z a t i o n l a y e r . ~ h e s eROMs a r e programmed by connecting t h e a p p r o p r i a t e d e v i c e c o n t a c t s t o t h e bit lines. The shared contact memory structure is based on the
p r e s e n c e o r a b s e n c e of a t r a n s i s t o r a t t h e memory l o c a t i o n r e p r e s e n t i n g t h e b i t . The programming f o r t h i s s t r u c t u r e occurs a t e i t h e r the diffusion or .~ o l-v s i l i c o nf a b r i c a t i o n s t e p CPRIN831. The X - c e l l s t r u c t u r e i s programmed i n a s i m i l a r f a s h i o n [pRIN833. An implant may also be used to a l t e r t h e t r a n s , s t o r t h r e s h o l d v o l t a g e , and thereby program t h e device CHNAT771. The m u l t i - v a l u e d ROMS a r e a l s o programmed i n d i f f e r e n t ways. The ROM presented i n CETIE851, t h e I n t e l ROM [AGAR841 a n d t h e Motorola ROM [DON0851 a r e a l l programmed by a d j u s t i n g t h e width t o l e n g t h r a t i o o f t h e memory c e l l t r a n s i s t o r s . The General Instruments design CRICH851 uses implants t o v a r y t r a n s i s t o r thresholds. The v a r i a b l e w i d t h t o l e n g t h r a t i o t e c h n i q u e i s c a l l e d v a r i a b l e geometry and from t h e point of view of f a b r i c a t i o n , i t i s p r e f e r a b l e t o t h e v a r i a b l e t h r e s h o l d method CDON0851. I t u s e s t h e v a r y i n g s i z e s of t h e t r a n s i s t o r s t o c o n t r o l t h e c u r r e n t and v o l t a g e d r o p a c r o s s t h e t r a n s i s t o r . This means a s t a n d a r d f a b r i c a t i o n p r o c e s s can be u s e d , r a t h e r than a One' such as the implant s t e p s used i n t h e General Instruments ROM. 2. THE TERNARY ROM
The t e r n a r y ROM (TROM) presented i n t h i s paper i s a p u r e t e r n a r y d e v i c e , a s f a r a s t h e system designer is concerned; I t i s designed f o r a t e r n a r y s y s t e m and therefore the address and the Outputs of t h e device a r e t e r n a r y . The TROM uses a s p l i t power s u p p l y and t h e output l o g i c l e v e l s a r e a t +3 v o l t s f o r t h e high l e v e l , 0 v o l t s f o r t h e m i d d l e l e v e l and -3 v o l t s f o r t h e low l e v e l . The normal t e r n a r y l o g i c r e p r e s e n t a t i o n of (2,l.O) c o r r e s p o n d s t o t h e high, middle and low l o g i c l e v e l s . The device has seven address l i n e s and f i v e o u t p u t d a t a l i n e s . D a t a is 'lacedO n t o the O u t p u t pins when t h e c h i p e n a b l e i s p l a c e d i n l o g i c low. The o ~ e r a t i o nof t h e ROM is s t a t i c .
3. CHIP INTERNAL DESIGN The TROM h a s f i v e major subsystems. These a r e t h e i n p u t p r o t e c t i o n subsystem, t h e a d d r e s s t o memory m a t r i x d e c o d i n g s u b s y s t e m , t h e memory m a t r i x subsystem, t h e s e n s e a m p l i f i e r s u b s y s t e m and t h e output subsystem. The block diagram of t h e TROM is presented i n Figure 1. 3.1 Input P r o t e c t i o n C i r c u i t The i n p u t p r o t e c t i o n c i r c u i t r y used i n t h e TROM i s t h e s t a n d a r d d i o d e - b a s e d i n p u t p r o t e c t i o n pad described i n many VLSI textbooks. I t i s a wellt e s t e d c e l l s i n c e i t has been used s u c c e s s f u l l y i n many o t h e r i n t e g r a t e d c i r c u i t p r o j e c t s a t Q u e e n ' s . This cell is part of Q,CELL, the University double metal standard cell l i b r a r y [ Q U E E 8 7 ~ . 3.2 T h e A d d r e s s Subsystem
t o Memory M a t r i x D e c o d i n g
T h i s subsystem decodes t h e seven t r i t address t o a row i n t h e memory s u b s y s t e m a n d a p a r t i c u l a r b i t l i n e . The a d d r e s s i s divided i n t o two p a r t s . The l o w e r f o u r t r i t s a r e u s e d t o determine t h e row address and t h e upper t h r e e t r i t s a r e used f o r t h e determination of t h e t r i t l i n e . The t e r n a r y l o g i c f u n c t i o n s a r e implemented w i t h v a r i a b l e g e o m e t r y c i r c u i t s . An e x a m p l e u s i n g i n v e r t e r s is shown i n Figure 2. The f o u r a d d r e s s l i n e s used i n t h e row decoding a r e
zg:i: :neK ~~:;~~-:
~ ~ c ~ ~ f : ~ d a : ~ ~ ~ l ~ ~ a r e u s e d by a n o t h e r s e t o f d e c o d e r s t o a c t u a l l y s e l e c t t h e row. S i n c e t h e o u t p u t o f t h e o n e - t o t h r e e d e c o d e r s is b i n a r y , b i n a r y c i r c u i t s a r e used f o r t h i s f u r t h e r l e v e l of decoding. The row decoding f r o m the twelve signal
lines is accomplished by a s t a t i c CMOS row d e c o d e r ( F i g u r e 4 ) . I t i s a f o u r i n p u t system, and i s composed of The two binary NAND g a t e s and a b i n a r y NOR g a t e . s t a t i c decoder a l l o w s t h e chip-enable-to control t h e o u t p u t . This i s p r e f e r a b l e when t e s t i n g t h e TROM. The two d i f f e r e n t decoders a r e assembled a s shown i n Figure 5. T h e r e a r e three address lines reserved f o r the Of the ROM m a t r i x ' i.e' the t r i t l i n e . T h e s e t h r e e a d d r e s s l i n e s a r e passed through one-to-three decoders t o o b t a i n n i n e l i n e s . The n i n e l i n e s c o n t r o l a t r e e decoder s t r u c t u r e , which is used t o s e l e c t t h e c o r r e c t t r i t l i n e from for each bank' the twenty-seven 3.3 The Memory Matrix The memory matrix has been one of the major design problems i n m u l t i - v a l u e d ROMS. The c h o i c e of t h e Inemor m a t r i x d e t e r m i n e s t h e sense iers references a n d t h e
:~~hOycessary
The o t h e r multi-valued ROM d e s i g n s have used e i t h e r v a r i a b l e geometry t r a n s i s t o r s o r v a r i a b l e t h r e s h o l d v o l t a g e s . The CMOS p r o c e s s a v a i l a b l e t o Q u e e n ' s does allow a variable threshold process. Thus the TROM design was i n i t i a l l y t o use v a r i a b l e geometry
transistors. The v a r i a b l e g e o m e t r y a p p r o a c h t o memory c e l l d e s i g n h a s f l a w s CADLH851. The most i m p o r t a n t
o b j e c t i o n i s t h e balancing of t h e pullup t r a n s i s t o r t o t h e pulldown t r a n s i s t o r . A s e t of dimensions has t o be d e t e r m i n e d f o r a t l e a s t two o f t h e t h r e e s t a t e s . A l s o , t o improve t h e r e l i a b i l i t y of t h e device, r e f e r e n c e c e l l s have t o be i n c l u d e d i n t h e m a t r i x , r e s u l t i n g i n l e s s c o s t - e f f e c t i v e memory area.
s e n s e a m p l i f i e r s may cause problems i f t h e o u t p u t of t h e memory matrix is f a r from t h e designed l o g i c l e v e l s . This may happen due t o some v a r i a t i o n i n t h e f a b r i c a t i o n process f o r t h e p a r t i c u l a r lot. This is t h e main reason f o r t h e l a r g e p- t r a n s i s t o r loads.
The symmetry of t h e t e r n a r y l o g i c l e v e l s allows t h e use of t h e memory c e l l d e s i g n used i n t h i s TROM. U n l i k e t h e f o u r valued ROM c e l l s , a t e r n a r y memory c e l l has t o provide two l e v e l s o t h e r t h a n t h e h i g h l o g i c l e v e l . T h e r e f o r e a c o n t a c t programmed ROM, where t h e pulldown t r a n s i s t o r i s c o n n e c t e d t o e i t h e r t h e middle o r low l o g i c l e v e l , can be used.
R O M s a r e t o be connected on d a t a busses. The TROM must have some way o f i s o l a t i n g t h e b u s from t h e r a n d o m o u t p u t s o f t h e memory m a t r i x . T h i s i s provided by a q u a d s t a t e device, which is a n a l o g o u s t o t h e t r i s t a t e d r i v e r i n binary systems. The high r e s i s t a n c e s t a t e o c c u r s when t h e c h i p e n a b l e s i g n a l is high.
An important f a c t o r i n t h e design is t h e problem of p r o g r a m m i n g t h e TROM. F o r t h i s TROM, a l l t h e programming i s done manually. The programming t a s k i s t e d i o u s a n d t h e r e f o r e p r o n e t o e r r o r . The c o n t a c t programming method r e q u i r e s t h e minimum number of s t e p s per c e l l . A f u r t h e r extension t o t h i s TROM design is t h e u s e o f s h a r e d t r a n s i s t o r s . The t r i t l i n e s a r e passed between two t r a n s i s t o r s , one of which is c o n n e c t e d t o t h e ground and t h e o t h e r t o t h e negative p o t e n t i a l . The c o n t a c t t o t h e t r i t l i n e i s made t o one t r a n s i s t o r i f t h e z e r o l e v e l is d e s i r e d from t h e c e l l , and t o t h e o t h e r t r a n s i s t o r i f t h e low l e v e l is r e q u i r e d . This s t r a t e g y is shown i n Figure 6. This r e q u i r e d t h e use of l a r g e l o a d t r a n s i s t o r s , which slows t h e charging of t h e t r i t l i n e .
When two a d j a c e n t t r i t l i n e s a r e t o have t h e same v a l u e f o r a given row, then t h e t r a n s i s t o r between the trit l i n e s is shared,if possible. Since t h e m a j o r i t y c a r r i e r m o b i l i t y of t h e pulldown t r a n s i s t o r is a p p r o x i m a t e l y t h r e e t i m e s t h e m a j o r i t y c a r r i e r m o b i l i t y o f t h e p u l l u p p-type t r a n s i s t o r , t h e c o r r e c t l o g i c l e v e l is d e l i v e r e d from t h e c e l l d e s p i t e h a v i n g t o s i n k d o u b l e t h e c u r r e n t of t h e s i n g l e t r i t l i n e case. The t r a n s i s t o r s i n t h e memory m a t r i x a r e a l l of minimum s i z e . I n t h e 3 micron p r o c e s s b e i n g u s e d , t h e n - t y p e t r a n s i s t o r i s 3 microns by 3 microns. This r e s u l t s i n a very compact matrix. Realizing a TROM u s i n g v a r i a b l e geometry would r e s u l t i n a c o n s i d e r a b l e i n c r e a s e i n t h e u s a g e o f a r e a . The t r a n s i s t o r s a r e i n t e r l e a v e d , r e s u l t i n g i n an e f f i c i e n t l a y o u t . An example l a y o u t is presented i n Figure 7. The p-type t r a n s i s t o r s which a r e used a s l o a d s on t h e t r i t l i n e s a r e 33 m i c r o n s l o n g by 3 microns wide. These t r a n s i s t o r s a r e always on, k e e p i n g t h e t r i t l i n e s charged t o +3 v o l t s . The r e s u l t i n g geometry i n t h e TROM uses f i v e banks of t h e s e memory elements. Each bank i s composed of 2248 t r a n s i s t o r s , arranged i n 81 r o w s , e a c h o f 28 t r a n s i s t o r s . Twenty-seven t r i t l i n e s a r e l o c a t e d i n each of t h e s e banks. Each t r i t l i n e is connected t o a p-device load t r a n s i s t o r . This r e s u l t s i n a t o t a l of 21 87 t r i t s per bank. 3.4 Sense Amplifier Subsystem The s e n s e a m p l i f i e r used i n t h e TROM is t h e one-tot h r e e d e c o d e r . T h i s i s t h e same c i r c u i t used i n t h e a d d r e s s decoders and has good c h a r a c t e r i s t i c s f o r a s i n g l e ended s e n s e a m p l i f i e r . S i n g l e ended
3.5 Output Subsystem
The b a s i c s t r u c t u r e f o r t h e q u a d s t a t e c e n t e r s a r o u n d t h e s e n s e a m p l i f i e r . The o n e - t o - t h r e e d e c o d e r h a s c o n v e r t e d t h e o u t p u t o f t h e memory m a t r i x i n t o a h i g h l e v e l on o n e of t h r e e o u t p u t s from t h e d e c o d e r . T h e s e a r e c o m b i n e d w i t h a p o s i t i v e e n a b l e s i g n a l . The combinational c i r c u i t is based on a NAND g a t e and an i n v e r t e r f o r t h e low and m i d d l e l o g i c d r i v e r s . A NAND g a t e i s used f o r the positive voltage driver. A s shown i n F i g u r e s 8a and 8 b , t h e output of t h e combinational c i r c u i t a c t i v a t e s t h e voltage d r i v e r s . These a r e t r a n s i s t o r s c o n n e c t e d t o t h e power r a i l s and s i z e d t o d e l i v e r s i x t e e n t i m e s t h e c u r r e n t d r i v e of a minimum s i z e d i n v e r t e r . A m e t a l l i z a t i o n p l o t of
the complete chip is
presented i n Figure 9. 4. SUBSYSTEM SIMULATION An important p a r t i n t h e VLSI design methodology is t h e s i m u l a t i o n of t h e c i r c u i t s i n c o r p o r a t e d i n t o t h e chip. To s i m u l a t e t h e TROM, two s i m u l a t o r s were used. E a r l y i n t h e d e s i g n s t a g e , much o f t h e c o n t r o l l o g i c v e r i f i c a t i o n was c a r r i e d o u t by QUAIL, t h e Q u e e n ' s U n i v e r s i t y Asynchronous I n t e r a c t i v e Logic simulator. I t is capable of handling m u l t i p l e valued f u n c t i o n s . QUAIL simulated t h e decoder l o g i c i n t h e TROM. SPICE is s t i l l used a t t h e c i r c u i t l e v e l . The ROM matrix and a sample system have been simulated. The SPICE deck has been e x t r a c t e d from t h e l a y o u t . The s i m u l a t i o n of t h e decoder l o g i c and t h e s a m p l e s y s t e m a r e presented i n Figure 10. This s i m u l a t i o n a l s o i n c l u d e s t h e e s t i m a t e d capacitance of t h e t r i t l i n e . The SPICE parameters f o r t h e Northern Telecom CMOS3DLM process a r e l i s t e d i n Appendix 1 CCMC871. Memory o u t p u t v o l t a g e l e v e l s a r e p r o v i d e d i n Appendix 2. 5. CONCLUSIONS This paper h a s d e s c r i b e d a d e s i g n f o r a t e r n a r y read-only memory. I t has a memory c a p a c i t y o f 21 87 f i v e t r i t words. This is addressed by s e v e n t h r e e l e v e l a d d r e s s i n p u t s . This device f i t s i n t o a 0.45x0.45 cm d i e . I t i s d i f f i c u l t t o compare t h e TROM with a binary ROM. The TROM has a c o n s i d e r a b l e a d v a n t a g e i n t h e
number o f s t a t e s p e r memory c e l l . But t h e binary The c o m p r e s s i o n o f t h e TROM m a t r i x i s o n e a r e a f o r
ROM s t r u c t u r e s tend t o be more a r e a - e f f i c i e n t .
[RICH861
further investigation. T h i s d e s i g n w i l l be u s e d i n f u t u r e c h i p implementations of t e r n a r y l o g i c systems where r e a d o n l y memory is necessary. One plan being c u r r e n t l y developed is t o i n t e r f a c e t h e chip- based ROM w i t h t h e t e r n a r y c o m p u t e r QTC-1 CMOUF841. T h i s w i l l allow t h e c o n t i n u e d d e v e l o p m e n t o f an i n t e g r a t e d c i r c u i t t e r n a r y microprocessor.
APPENDIX 1 CMOS3DLM S p i c e Parameters SPICE Model Parameters used i n t h e s i m u l a t i o n . .MODEL N NMOS (LEVEL=l VTO=O. 7 KP=4OE-6 GAMMA=l . 1 P H I = O . 6 + LAMBDA=O. 01 P B = 0 . 7 CGSO=3.0E-10 CGDO=3.0E-10 CGBO=5.0E-10 + RSH=25 CJ=4.4E-4 MJ=O. 5 CJSW=b.OE-10 MJSW=O. 3 JS=l .OE-5 + TOX=5.OE-8 NSUB=l .7E16 TPG=l XJ=6.OE-7 LD=3.5E-7 U0=775 )
6. REFERENCES CADLH851 A d l h o c h , R . , " Q u a t e r n a r y R O M D e s i g n U t i l i z i n g Variable Threshold S t o r a g e C e l l s " , P r o c . 1 5 t h I n t e r . Symp. M u l t i p l e Valued L o g i c , K i n g s t o n , May 1985, pp. 310-316. [AGAR841 Agarwal, V. K . , J. H. P u g s l e y , a n d C . B . S i l i o , " M u l t i p l e Valued O u t p u t ROM C i r c u i t s w , P r o c . 1 4 t h I n t e r . Symp. M u l t i p l e V a l u e d L o g i c , W i n n i p e g , May 1984. pp. 224-231 CCMC871 Canadian M i c r o e l e c t r o n i c s Corporation," Guide t o t h e I m p l e m e n t a t i o n S e r v i c e s of t h e Canadian M i c r o e l e c t r o n i c s Corp.", Jan. 1987. Donoghue,B., P. Holly, and K. I l g e n s t e i n , "A 256K HCMOS ROM Using a Four S t a t e C e l l A ~ II. I E EDE J o u r . ~ s o l i d - ~s t a t e c i r c u i t s . ~ o SC-20, i No.2, A p r i l 1 9 8 5 , pp.598-602. Etiemble, D . , B. Nathegi, and J . E r l i c h , " A 4 - v a l u e d 1 Kbyte ROM D e s i g n e d With Lambda-Rulesw, P r o c . 1 5 t h I n t . Symp. M u l t i p l e V a l u e d L o g i c , K i n g s t o n , May 1985. pp. 92-100. H e u n g , A.N.C., L. W o n g , " T e r n a r y Microcomputer System", R e s e a r c h Report, Queen's U n i v e r s i t y , 1983. H n a t e k , E. R . , "A U s e r ' s H a n d b o o k Of S e m i c o n d u c t o r M e m o r i e s n , John Wiley & Sons, New York, 1977. Hodges, D . A . , H. G. Jackson, " A n a l y s i s and D e s i g n o f D i g i t a l I n t e g r a t e d C i r c u i t s n , McGraw-Hill, New York, 1983. L a v e l l e , E., D. Etiemble, "Improved Sense A m p l i f i e r s f o r 4 Valued ROMsw , Proc. 1 4 t h I n t e r . Symp. M u l t i p l e V a l u e d L o g i c , Winnipeg, May 1984. pp. 232-239. Mouftah, H. T. and I. B. J o r d a n , " D e s i g n o f T e r n a r y COSMOS Memory and S e q u e n t i a l C i r c u i t s n , IEEE Trans. Comput. Mar. 1977, Vol C-26, pp. 281-288. Mouftah, H. T., A. N . C . Heung a n d L. M . C . Wong, "QTC-1, A CMOS Ternary Computeru, Proc. 1 4 t h I n t e r . Symp. M u l t i p l e Valued Logic, Winnipeg, May 1984, pp. 125-132. P r i n c e , B. and G. Due-Gundersen, n S e m i c o n d u c t o r Memoriesn, John Wiley & Sons, New York, 1983. "QUCELL 1 . O , CMOS3DLM D i g i t a l Logic C e l l L i b r a r y ", D e p t . o f E l e c t r i c a l E n g . , Q u e e n ' s U n i v e r s i t y , May 1987. R i c h , D . A , K . L. C. N a i f f a n d K . G . Smalley, " A F o u r S t a t e ROM U s i n g Multilevel Process Technology ", P r o c . 1 5 t h I n t . Symp. M u l t i p l e V a l u e d L o g i c , K i n g s t o n , May 1 9 8 5 , pp.236-240.
R i c h , D . A. " A S u r v e y o f M u l t i v a l u e d Memories", I E E E Trans.Comput. Vol V-35, No.2, Feb. 1986, pp. 99-106.
.MODEL P PMOS ( LEVEL-1 VTO=-0.8 KP=12E-6 GAMMA=O. 6 P H I = 0 . 6 + LAMBDA=0.03 PB=O. 6 C G S O = 2 . 5 E - 1 0 CGDO=2.5E-10 CGBO=5.0E-10 + RSH=80 CJ=1.5E-4 MJ=0.6 CJSW=O.OE-10 MJSW=O. 6 J S = 1 OE-5 + TOX=5.OE-8 NSUB=5.OE15 TPG=l XJ=5.OE-7 LD=2.5E-7 UO=250 ) APPENDIX 2
.
.
Memory C e l l Output Voltage Levels Low Level ( single ) -2.993
v
Middle Level ( S i n g l e P-Load ) 1.493E-2 V LOW
~
Level ( Shared P-Loads ) -2.986 V
M i d d l e~L e v e l ( S~h a r e d P - L o a d s ) - 2 . 9 9 2 E - 2 V
4
-WCoL. Sebct ate
~d~~~~
f3.
I
CoL Select Gate
. + Tram.
Array
bm
I I
To Output 1
I
To Output 5
Figure 1. Block Diagram of the TROM
Vdd (+3V) I
Width to Length Ratios Baaic
INPUT
SBI
Vsa (-39
PTI NTI SBI
Positive Ternary Inverter Negative Ternary Inverter Standard Binary Inverter
NTI
Figure 2. Variable Geometry Inverters
Figure 3. Type A Decoder - One to Three Decoder -
_I1 Output
Output Line
L
-
M
Figure 4. Type B Decoder
u ENABLE
Figure 8a. Logic Schematic of the Quadstate Driver
El Decoder
To Output Pad
1
Word Line 80
:$
Type B Decoder
D
vss (-3V)
Figure 8b. Output Stage of the Quadstate Driver
Figure 5. Complete Decoder Arrangement
Trit Lipe
1
2
1
I
0
1
Word Line
0
1 Shared
Transistor
F i g u r e 7 . E x a m p l e L a y o u t o f Programmed TROM Memory C e l l s
Laglc Level
4
I
G
i
I
1
o
o
2
I
Trlt L n e
Figure 6.
Shared Translstor
TROM Memory Cell
Arrangement
IX~O.,~
o ~ ~ L r s l
VllOZ YiN
- -
Figure 9. Metallization Plot of t h e TROM (4510 x 4510 microns)
2.07
I
I
V130O Y I I I O
I
1
v1301 \..Oh
[ 1 ,
i
,
j
-
--
A0
-
A6
I n p u t Address Lines
DO
-
D4
O u t p u t Data Llnes
E VDD, VSS.
-0.46
-1.73
-3.00 O OO
O 90
l BO
2 70
3 60
4 50
5.40
TIME
Figure 10
TROY Simulation
6 30
7 PO
8 10
I x l O e r p - 7 SECONOS1
9 OO
Enable
GND
+3V, -3V, OV
