A Cohesive FPGA-Based System-on-Chip Design Curriculum. John D. Lynch, Daniel Hammerstrom, Roy Kravitz. OGI School of Science and Engineering at ...
A Cohesive FPGA-Based System-on-Chip Design Curriculum John D. Lynch, Daniel Hammerstrom, Roy Kravitz OGI School of Science and Engineering at Oregon Health and Science University
Abstract A graduate-level computer engineering course sequence at the OGI School of Science and Engineering teaches state-of-the-art digital system design practices and system-on-chip design concepts. Commercial electronic design automation (EDA) software in conjunction with high-density programmable logic devices allows students to design projects of significant complexity. The course sequence, targeted for both full-time students, and part time students from local high-tech companies, consists of three consecutive courses taught fall, winter, and spring quarters. The first course covers logic design using Verilog, the second introduces logic synthesis and system-on-chip design concepts, and the third addresses timing and test of digital systems.
1. Introduction Advances in semiconductor technology have made it possible to implement a complex system on a single programmable chip. High-density FPGAs are an ideal vehicle to teach system-on-chip (SoC) design because the FPGA design cycle is short enough that students can complete complex designs within the time-frame of an academic quarter. Though FPGA implementation is used throughout the course sequence, the SoC design principles are taught in a way that is applicable to ASIC implementation as well. This three-course sequence is a core component of OGI’s computer engineering curriculum, which also includes courses in computer architecture, VLSI design, circuit design, and digital signal processing. The first course, EE570 Advanced Logic Design, teaches logic design using the Verilog hardware description language (HDL). The second course, EE571 System-on-Chip Design with Programmable Logic teaches logic synthesis and system-on-chip design concepts. In this project-oriented course, students design a series of SoC projects using an 8-bit processor and a simple graphics subsystem, and implement them in FPGAs. The final course, EE572
Advanced Digital Design: Timing and Test, completes the sequence, focusing on timing issues, such as timing-driven logic synthesis, static timing analysis (STA), metastability, synchronization, and multi-clock design techniques. Design-for-test topics such scan testing and automated test pattern generation are also introduced. Verilog HDL is used rather than VHDL because it is easier to learn and more widely used in local industry. Mentor Graphics and Xilinx EDA software is used throughout the course sequence. The ModelSim logic simulator is used for design verification in all three courses. Precision RTL Synthesis is used for logic synthesis in both EE571 and EE572. Xilinx ISE provides FPGA placement and routing in EE571 and STA in EE572. Students enrolled in the courses have access to OGI’s Computer Engineering laboratory. The CE lab is equipped with Xilinx FPGA development boards from Digilent, Inc., signal generators, oscilloscopes, and computer workstations with Mentor Graphics and Xilinx EDA software installed. Located in the heart of Oregon’s “Silicon Forest”, the OGI School of Science and Engineering’s computer engineering education program offers a Master of Science degree in electrical engineering. Most students work full-time in the technology industry and attend school part-time. These students are well prepared and have high learning expectations.
2. EE570 Advanced Logic Design This course introduces design and implementation of computer logic using methods that are commonly used in industry. Principles of discrete logic design are presented, including Boolean algebra, truth tables, logic gates, timing diagrams; finite-state machine design, logic optimization using both hand-compiled (Karnaugh maps) and automated techniques, along with the basics of the Verilog HDL. EE 570 is similar to logic design courses typically taught at the undergraduate level. However, it is taught as a graduate course by covering more material,
Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education (MSE’05) 0-7695-2374-9/05 $20.00 © 2005 IEEE
addressing more sophisticated design topics, and including a complex Verilog HDL design project using ModelSim.
3. EE571 System-on-Chip Design with Programmable Logic This course builds on the knowledge of Verilog HDL gained in EE 570, introducing logic synthesis, implementation and SoC design concepts.. The course has a project orientation: Students take designs from concept to Verilog HDL description, then verification using simulation, synthesis and then to programmable device implementation on an FPGA development board. During the first six weeks of the course, students do three lab projects, each more complex than the last, culminating in a complete SoC design incorporating an 8-bit microprocessor and peripherals. The first project, a simple FSM, serves to introduce students to logic synthesis and FPGA implementation tools and methods, and how to use the input/outputs devices (buttons, LEDs, etc.) on the FPGA development board. The second project introduces SoC concepts such as on-chip processor, memory and peripheral interfacing, and hardware-software trade-offs. An 8-bit soft processor core developed by the authors is used. The third project adds a graphics subsystem, inspired by Hamblin [1], to the SoC enabling students to display their design results on a CRT monitor. Concurrent with the lab sequence are lectures on programmable chip architectures, logic synthesis, SoC concepts, and the Verilog synthesizable subset, including design examples. During the final weeks of the course, students work in teams of two to complete an advanced FPGA design project of their choice. The only requirement is that the final project be more complex than any of the three previously assigned projects. There are no scheduled lectures during this portion of the course, but the instructors are available to answer questions. Having mastered basic graphics hardware design in last assigned lab, many students choose a graphicsoriented final project. The ability to visualize design results aids debugging as well as making the projects more fun for both students and instructors.
traditionally not well covered by academic curricula. The motivation to develop it comes from John Lynch’s experience as a hiring manager in industry, where he found recent college graduate engineers widely uninformed of timing issues in digital systems. The course is roughly divided into three parts. The first part of the course covers digital system timing fundamentals: Clock distribution, setup/hold timing path analysis, skew and jitter, pipeline retiming, delayand phase-locked loops, dynamic timing simulation and STA. This part includes lab exercises in STA, timing simulation, and synthesis with register retiming. The second part deals with design issues related to multiple asynchronous clocks: Metastability, synchronization, multi-clock design techniques, and self-timed logic. This part includes an asynchronous FIFO design exercise inspired by Cummings [2]. The final part of the course introduces testing of digital systems, giving a short overview of digital testing topics, including test economics, fault modeling and simulation, sequential test methods, and designfor-test techniques.
5. Future Work A new course on hardware functional verification is being developed to be offered Spring Quarter 2005. This new course will complement the present course sequence by addressing another significant problem in SoC design. Like digital system timing, the topic of hardware functional verification has not yet been widely addressed by colleges and universities. This course covers practical aspects of functional hardware verification for complex ASIC and FPGA designs. It introduces a variety of state-of-the art verification methods, beginning with functional simulation, then assertion-based verification and concluding with a subset of formal verification techniques. Topics include simulation coverage metrics, test bench design and automation, assertionbased verification using property specification language (PSL), and formal methods including model checking and logical equivalence checking. In addition to lectures and reading, students will do functional simulation, assertion-based, and PSL lab exercises using ModelSim.
4. EE572 Advanced Digital Design: Timing and Test
[1] J. Hamblen and M. Furman, Rapid Prototyping of Digital Systems, 2nd Edition, Kluwer Academic Press, 2001, ISBN 0-7923-7439-8.
This course focuses on timing and design-for-test topics in FPGA and ASIC design and implementation. It addresses real-world hardware design issues
[2] Cummings, Cliff, Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, Synopsys Users Group 2001.
Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education (MSE’05) 0-7695-2374-9/05 $20.00 © 2005 IEEE
