A Compact and Programmable High-Frequency Oscillator Based on a ...

IEEE 2008 Custom Intergrated Circuits Conference (CICC)

A Compact and Programmable High-Frequency Oscillator Based on a MEMS Resonator F. Nabki, F. Ahmad, K. Allidina, and M. N. El-Gamal McGill University, Montreal, Canada Abstract- This paper presents a 1.65-2.0GHz digitally programmable oscillator. The oscillator is based on a MEMS resonator combined with a high-resolution 0.18μm CMOS fractional-N PLL. Due to the dimensions of the MEMS resonator (350μm x 130μm), the size of the entire system is ~6.05mm2, and can be integrated into a single small form factor package. The phase noise for an oscillation frequency of 1.8GHz is –116dBc/Hz at a 600kHz offset, and the entire system consumes 50mW from a 2V supply. The PLL employs a 3rd-order 20-bit delta-sigma modulator to deliver an output resolution of ~220Hz, i.e. enabling a controlled frequency stability of better than 0.125ppm.

I. INTRODUCTION As data rates in communications systems continue to rise, there is an increased need for low-jitter high-frequency oscillators that are stable over both temperature and time. This is especially evident in optical networks and LANs operating at data rates close to 10Gbps. Currently, oscillators based on high-frequency fundamental (HFF) crystals or surface acoustic wave (SAW) resonators are used to fill this need. However, these devices are large, can only operate at a single frequency, and are complicated to manufacture with high frequency stability [1]. They also require off-chip connections to interface with the electronics, increasing the size, complexity, and cost of the overall system. This paper presents a stable high-frequency oscillator based on a micro electro-mechanical (MEMS) resonator combined with a fractional-N phase-locked loop (PLL). In the context of this work, stability will always refer to the ability to produce an accurate frequency over both temperature and time. The oscillator presented here could also be realized using a stable low-frequency crystal; however, the small size of the MEMS resonator enables the integration of the entire oscillator into a single package. This considerably reduces the form factor of the system, and the shorter connections between the electronics and the MEMS device result in higher levels of performance, due to the reduced parasitics and losses.

Fig. 1 – Simplified oscillator system diagram.

This paper will first provide a brief description of the MEMS resonator, along with its relevant characteristics. The circuits that make up the frequency synthesizer will then be presented, followed by measurement results of the entire system. III. BRIEF DESCRIPTION OF THE MEMS RESONATOR The MEMS resonators are fabricated in an in-house metalized, CMOS compatible, amorphous silicon carbide (a-SiC) surface micromachining process, described in detail in [2]. The specific device used in this work exhibits a motional resistance of ~26kΩ, a quality factor (Q) of 1040, and a resonant frequency of 8.3MHz. Various pictures depicting the fabricated clamped-clamped beam resonator and its characteristics are shown in Fig. 2. The entire structure with pads measures 350μm by 130μm, and the resonator’s dimensions are 25μm by 45μm, with a 200nm air gap. IV. THE FREQUENCY SYNTHESIZER This section presents the circuits used in the frequency synthesizer shown in Fig. 1.

II. THE OSCILLATOR The system diagram of the oscillator is shown in Fig. 1. It includes a 3rd order 20-bit delta-sigma modulator which allows the PLL to achieve a very high output resolution, on the order of 220Hz. When combined with an automatic feedback loop to dynamically control the delta-sigma modulator, this oscillator could achieve a stability of less than 0.125ppm, while operating in the GHz range. This would enable the fabrication of tunable high-frequency oscillators possessing stability characteristics which are much better than those of currently available commercial HFF or SAW based oscillators.

978-1-4244-2018-6/08/$25.00 ©2008 IEEE

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Fig. 2 – (a) 3-D model of the resonator. (b) Simulated mode shape of the resonator. (c) Micrograph of the resonator with wire bonds. (d) Close-up SEM picture of the resonator showing a 200nm gap spacing.

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Fig. 4 – Phase frequency detector.

A. The Transimpedance Amplifier (TIA) Due to the large motional resistance of a MEMS resonator, a very high-gain TIA is needed. At the same time, a large bandwidth is required to ensure that the phase shift around the loop is as close to zero as possible. From the resonator’s characteristics, it can be determined that the necessary gainbandwidth product of the TIA is 2.16THz. A TIA was custom-designed for this application, and its block diagram is shown in Fig. 3. The input stage is based on a gm-boosted common-gate amplifier, and is followed by a variable gain amplifier controlled by an automatic gain control (AGC) loop. This prevents the oscillation voltage from exceeding values which could exert non-linearities in the MEMS resonator and deteriorate noise performance [3]. The TIA has two voltage outputs: VOUT,RES is fed back into the resonator to form the positive feedback loop, and VOUT,PLL is a digital signal that serves as the reference frequency for the PLL. Both the input and output stages are designed to have very low impedances to avoid loading the resonator’s quality factor. The gain of the TIA can be varied from 17kΩ to 290kΩ, i.e. a tuning range of 25dB. The 3-dB bandwidths corresponding to these gains are 253MHz and 103MHz, respectively. Since these bandwidths are greater than ten times the resonant frequency of the MEMS device, the phase shift around the loop is ensured to be close to zero degrees. B. The Phase Frequency Detector (PFD) and Charge Pump The PFD used is shown in Fig. 4. It is based on D flipflops, with outputs depending on the time differences between the rising edges of the reference and those of the divided oscillator waveforms. A delay is introduced into the reset signal path to eliminate the dead zone associated with this PFD. An output stage (control signal generator) is used to convert the up and down signals generated by the PFD into eight separate control signals [4]. The purpose of these signals is to mitigate non-idealities in the charge pump, as will be described in the next paragraph. The charge pump schematic is shown in Fig. 5. A dummy branch (M7–M10) was added to preserve the voltages at the drains of M1 and M2, thus avoiding current spikes due to charge leakage. To eliminate changes in these voltages during transitions, the signals from the PFD are timed such that there is a small overlap between the time when the output branch turns on and the time the dummy branch turns off, and viceversa. A simple differential amplifier in a unity-gain configuration is used to ensure that the voltage on the dummy branch matches that of the charge pump output [5].

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Fig. 5 – Charge pump.

The eight PFD control signals are needed in order to allow the use of complementary switches in the charge pump, which drastically reduces charge injection and charge feedthrough errors, provided a careful layout is used to match the transistors. This reduces the ripples on the control line, and thus the level of spurs created by the VCO. Biasing is set by M11–M16, where M13–M16 are present to reduce the mismatch resulting from channel length modulation, when mirroring currents to the active branches of the charge pump. C. The Loop Filter The low frequency of the reference MEMS resonator (8.3MHz), combined with the 3rd order delta-sigma modulator necessitates a very small loop bandwidth, on the order of 25kHz. A simple passive or opamp-based loop filter would require a large capacitance to achieve this bandwidth, and would not be amenable to on-chip integration. Instead, the dual-path filter shown in Fig. 6 is used [4]. This type of architecture reduces the capacitance needed by a factor equivalent to the current multiplication between the two loop filter paths, i.e. corresponding to the variable B in Fig. 6. It however mandates the use of two charge pumps. It should also be noted that the inputs to this filter are negative, which means that the “Up” and “Down” signals from the charge pumps must be reversed to obtain the correct output. The low-pass filter R1 and C1 forms an additional pole at the output of the loop filter. In this design, the charge pump currents were set to 60μA and 5μA. This reduces the sizes of the capacitances needed by a factor of twelve. It should also be noted that the output voltages of both charge pump branches are fixed at a voltage

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Fig. 6 – Dual-path loop filter.

Fig. 8 – VCO schematic.

Fig. 7 – Schematic of amplifier A2.

VREF, when the loop is in lock. This helps ensure that the up and down currents do not suffer from mismatches due to channel length modulation. The amplifier used in the integrator (A1) is a simple one-stage differential pair with an active load. Amplifier A2 (detailed in Fig. 7) removes the DC offset (VREF) at the output of the low-pass filter formed by Cp and Rp. Also, M4 and M5 source bias currents equivalent to those of the differential pair M1 and M2, so that any differences between VREF and the low-pass filter voltage is mirrored to M7 through M6. At the same time, the commondrain stage of M8 converts the integrated voltage (Vz) into a current and adds it to that of M7. The body of M8 is tied to the source to eliminate the body effect and increase the available voltage swing. D. The VCO A top-fed cross-coupled VCO is used in this design. The schematic is shown in Fig. 8. The current mirror M5 and M6 serves to reduce sensitivity to power-supply variations, and capacitor C1 reduces the drain current at the zero-crossings of the tank voltage. This decreases the phase noise by reducing the current injected during sensitive portions of the cycle [6]. Accumulation mode PMOS varactors are used to provide fine tuning of the VCO, and a bank of five digitally switched capacitors is used to provide coarse tuning. With these two mechanisms, the tuning range of the VCO is 1.65GHz to 2GHz. The gain of the VCO has an average value of 150MHz/V. The inductors are intertwined to decrease their areas. One output of the differential VCO is fed to the divider through an inverter chain, while the other terminal is fed to an output buffer to drive the 50Ω load of the measurement equipment.

E .Multimodulus Divider and Delta-Sigma Modulator A 6-bit programmable pulse-swallow divider is used in this design for its simplicity and ability to interface well with the delta-sigma modulator’s 4-bit output without overflow. True signal phase clock (TSPC) logic was used for the programmable counters and the prescaler in the divider to increase the speed of the circuits. The delta-sigma modulator is a single-loop 3rd order modulator with multiple feedforward. It is important that the delta-sigma calculation is performed on the opposite edge of the clock as the edge which activates the PFD. This ensures that the switching noise from the delta-sigma modulator does not affect the PLL during lock. Dithering is also implemented to suppress the quantization noise idle tones. The modulator has a 20-bit input, which results in a PLL output resolution of: f ref (1) resolution = 20 × N , 2 where fref is the reference frequency and N is the divider ratio. This provides a high output resolution for the frequency synthesizer, on the order of 220Hz. By dynamically controlling the delta-sigma modulator through an automatic frequency control loop, this high resolution could be translated into a very high oscillator stability, i.e. better than 0.125ppm.

V. EXPERIMENTAL RESULTS The frequency synthesizer and the TIA are fabricated in a 0.18μm CMOS process. A micrograph of the chip is shown in Fig. 9, alongside the MEMS resonator. The resonator is significantly smaller than an on-chip inductor. The entire design occupies an area of ~6.05mm2 and consumes 50mW from a 2V supply. The synthesizer was tested both with the 8.3MHz MEMS resonator and a 10MHz temperature controlled crystal oscillator (TCXO). Fig. 10 shows a comparison of the phase noises obtained with each reference at an output frequency of 1.8GHz. The phase noise profiles are clearly similar, while the

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Fig. 11 – Fractional tuning of the output frequency.

Fig. 9 – Chip micrograph, along with a MEMS resonator (to scale).

Fig. 12 – Effect of dithering on the fractional spurs. (Centre frequency = 1.7GHz)

range simply by changing the tuning range of the RF VCO. For instance, a VCO in the range of 600MHz would make this design applicable to the SONET standards of optical networks.

Fig. 10 – Phase noise comparison using different references.

in-band phase noise of the PLL is actually slightly better with the MEMS resonator. The phase noise at a 600kHz offset is -116dBc/Hz. The optimization of the on-chip RF VCO is currently underway to reduce this value to below -121dBc/Hz, which will expand the potential applications of this oscillator to the wireless DCS-1800 standard. A plot of the spectrum with three output frequencies is shown in Fig. 11. The delta-sigma modulator was used to tune the output frequency in steps of 2.5MHz. This is far from the minimum resolution of the PLL, but it illustrates the oscillator’s ability to synthesize frequencies which are not multiples of the reference. The smallest measurable step size around the frequency of 1.8GHz is 220Hz, which could yield a frequency reference with stability on the order of 0.125ppm. Fig. 11 also shows that the power of the reference spurs is 56dB below that of the carrier. Fig. 12 shows the effect of dithering on the fractional spurs created by the delta-sigma modulator. The centre frequency for both curves is 1.7GHz. It can be seen that dithering reduces the power of the spurs by at least 11dB. Once the fractional spurs are suppressed close to the carrier by dithering, the noise shaping of the delta-sigma modulator becomes more apparent. It should be noted that the system reported here can be used to implement a highly stable oscillator, in terms of initial frequency accuracy and drift compensation, in any frequency

VI. CONCLUSION This paper presented a compact and programmable highfrequency oscillator based on a MEMS resonator and a highresolution PLL. Thanks to the MEMS-based reference signal, the entire system can be integrated into a single small form factor package. The oscillator tuning range is from 1.65GHz to 2GHz, and the high-resolution makes it possible to obtain a stability of less than 0.125ppm. REFERENCES [1] R. Clark, "Programmable Crystal Oscillators with Sub-ps Jitter and Multiple Frequency Capability," white paper, Silicon Laboratories Inc., Austin, TX. [2] F. Nabki, T. A. Dusatko, S. Vengallatore, and M. N. El-Gamal, "LowTemperature (