A Comparison Between the GPI and PID Controllers for the ...

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011

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A Comparison Between the GPI and PID Controllers for the Stabilization of a DC–DC “Buck” Converter: A Field Programmable Gate Array Implementation Eric William Zurita-Bustamante, Jesús Linares-Flores, Enrique Guzmán-Ramírez, and Hebertt Sira-Ramírez

Abstract—This paper presents a comparison between two stabilizing average output feedback controllers implemented on a field programmable gate array (FPGA) facility. A generalized proportional integral (GPI) controller and a proportional integral derivative (PID) controller are implemented using an FPGA, and their respective performances are duly compared. The GPI controller is found to present a better dynamic response than the PID controller in terms of the settling time while exhibiting a greater degree of robustness regarding disturbance rejection represented by severe changes in static and dynamic loads. The average controllers and their corresponding pulsewidth modulation actuators are implemented using a Spartan 3E1600 FPGA. Index Terms—Buck converter, dc–dc power conversion, field programmable gate arrays (FPGAs), generalized proportional integral (GPI) and proportional integral derivative (PID) control systems.

I. I NTRODUCTION

M

ANY industrial applications of voltage regulation are accomplished via dc–dc power converters. For example, uninterruptible power supplies [1] are used in dc motor drivers for electric traction on trolleys [2]. Lighting systems using electronic ballasts also benefit from the use of such devices [3]. Today, switching devices are currently available, exhibiting high switching speeds and high power-handling capabilities. It is possible nowadays to design low cost, light weight, small size, and switched-mode power supplies with efficiencies beyond 90% [4]–[7]. The classic power converter topologies used are, generally speaking, “buck,” boost, and buck–boost. In this paper, a generalized proportional integral (GPI) control scheme is presented to regulate the output voltage of a “buck” converter. This control is introduced by Fliess et al. in [8] as a means to circumvent classical observers and base output Manuscript received August 6, 2010; revised December 21, 2010; accepted February 2, 2011. Date of publication March 7, 2011; date of current version September 7, 2011. E. W. Zurita-Bustamante is with the División de Estudios de Postgrado, Universidad Tecnológica de la Mixteca, 69000 Huajuapan de León, Oaxaca, Mexico (e-mail: [email protected]). J. Linares-Flores and E. Guzmán-Ramírez are with the Instituto de Electrónica and Mecatrónica, Universidad Tecnológica de la Mixteca, 69000 Huajuapan de León, Oaxaca, Mexico (e-mail: [email protected]; [email protected]). H. Sira-Ramírez is with Sectión de Mecatrónica, Centro de Investigación y Estudios Avanzados del IPN (CINVESTAV-IPN), 07300 México, DF, Mexico (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2011.2123857

feedback loops in terms of structural state estimators and iterated tracking error integral compensation. The GPI technique has been used in recent years to control dc–dc power converters because of the following characteristics: fast dynamic response and enhanced robustness with respect to unknown constant and ramp disturbances. In addition, using this technique significantly reduces the use of sensors measuring the states of the controlled system. GPI controllers are based on integral state reconstructors processing the available inputs and outputs [9], [10] (see also [11]–[14]). On the other hand, in [15], a GPI control scheme is proposed for dc–dc power converters based on the use of an indirect current control scheme for several converter topologies which are the nonminimum phase from the available output. In particular, this allows regulation toward a desired output voltage for the switched-capacitor step-down dc–dc converter. The proposed GPI controller scheme is found to be robust with respect to sudden constant load variations, and it only requires the measurement of the output voltage of the inverter. However, the main features of the proposed GPI controller are evaluated only through computer simulations. In the work of Franco-Gonzalez et al. [11], a multivariable dc-to-dc converter is presented, which is a boost–boost type that is composed of two cascaded boost converters in the continuous conduction mode. Each converter feeds an independent resistive load. A sliding-mode feedback controller, based on the GPI approach, is developed for the regulation task. The feedback control scheme uses only the output capacitor voltage measurements as well as the input signals represented by the switch positions. In addition, the robustness of the feedback scheme is tested by nonmodeled sudden load resistance variations in the last resistive load. The experimental implementations of the controller were made by a computer with a data-acquisition card. In [16], the results of the performance of the GPI controller for a smooth starter of a dc motor based on a switch-controlled dc-to-dc power converter of the “buck” type were presented at a simulation level. The switched input actuator was proposed as a sigma–delta modulator (see [9]). The scheme proposes a direct regulation of the motor shaft speed using the flatness of the combined system. With regard to robust controllers implemented on a field programmable gate array (FPGA), for the regulation of the output voltage of the “buck” converter, the study in [17] presents a comparison between two proportional integral derivative (PID) average controllers. In [18], a modular design of embedded

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feedback controllers is proposed using an FPGA. They proposed a distributed arithmetic scheme, which is a bit-serial computation algorithm that performs multiplication using an LUT-based scheme, to control a temperature system. In [19], a digital implementation of an observation strategy of the flying capacitor voltages dedicated to stacked multicell converters is performed. They design a sliding-mode observer devoted to the flying capacitor voltages and their digitizing, which is implemented into the FPGA. Naouar et al. [20] show the benefits of using FPGAs on industrial control systems, particularly control techniques applied to ac machine drives. Gao et al. [21] presented the design of a classic PID control and a digital pulsewidth modulator (DPWM) as the main module for a “buck” converter. To verify the effectiveness of the DPWM, an 11-b DPWM was implemented on an FPGA. The experimental results using a fixed sampling frequency of 2 MHz demonstrate the ease of implementation of the DPWM. The implementation was performed on an FPGA Virtex-II Pro XC2VP30. The study in [22] shows the implementation of an efficiency estimator in a digital control scheme applied to a “buck” converter. The approach is based on an indirect estimation of the ratio between the output and input currents using a single current sensing. The experimental results on a synchronous “buck” converter with the efficiency estimator were also implemented in an FPGA, showing that the efficiency may be estimated with errors on the order of 5%. In [23], a “buck” converter is controlled through a high-bandwidth multisampled digitally controller using ripple compensation. The multisampling techniques reduce the PWM phase lag, ultimately breaking the bandwidth limitation. The proposed control is a feedback technique and needs no preliminary knowledge of converter parameters. The experimental results at 1.2 V–10 A and at a frequency of 500 kHz have been implemented on a Xilinx Spartan 3 FPGA. Recently, Idkhajine et al. have presented a fully integrated FPGA-based solution for motor control [36]. After making a brief description of the proposed control system, the authors have focused first on the description of the FPGA-based resolver processing unit (RPU) in extracting the rotor position and speed. Then, a description of the FPGA-based motor controller has been achieved. The FPGA-based RPU offers a good estimation accuracy of the position and speed. However, some studies have to be made in order to improve the treatment quality and, particularly, the synchronous demodulation. Furthermore, resource optimization has to be carried out in order to reduce the consumed FPGA hardware resources. Finally, in [37], an FPGA-based intelligent-complementary slidingmode control (ICSMC) is proposed to control the mover of a permanent magnet linear synchronous motor servo-drive system to track periodic-reference trajectories. In ICSMC development, a radial-basis function-network (RBFN) estimator with accurate approximation capability was modeled using VHDL language. Furthermore, the adaptive-learning algorithms for the online training of the RBFN were derived using the Lyapunov theorem to guarantee closed-loop stability. In this paper, we will focus on the comparison of two average output feedback controllers implemented in an FPGA to stabilize the output voltage of a “buck” power converter

Fig. 1.

Electrical circuit of the “buck” converter.

around a desired constant output reference voltage. We first implement a GPI controller and obtain the performance features related to settling time and recovery with respect to sudden, static, and dynamic load changes. Next, we implement a second controller on the same converter, corresponding to a classical PID controller, and proceed to evaluating the same features examined for the GPI control scheme. The average control inputs are used as a duty ratio generator in a PWM control actuator. The experimental setup used for the comparisons has the following features. 1) The PWM actuator is implemented through a triangular carrier signal and a comparator. The main function of this modulator is the conversion of the average signal to a pulsing signal that activates and deactivates the converter power transistor at a switching frequency of 48 kHz. 2) The processing time control for the GPI is 39.2 μs, while the processing time for the PID is 20.54 μs. These processing times were achieved owing to the parallel execution of units modeled within an FPGA [24], [25]. Progress of a programmable logic device (PLD), like FPGA or CPLD, enables the realization of a digital control system for power electronics, thus avoiding the use of microprocessors (CPU or DSP) [26]. 3) The output voltage is obtained through an analog to digital converter (ADC), which is the only additional hardware needed to operate the controllers. The used ADC is ADC0820, which is an 8-b converter. The remaining sections of this paper are organized as follows. In the next section, the mathematical model of the “buck” converter is presented. Sections III and IV describe the GPI and PID controller designs, respectively. Section V presents the design requirements of the controllers. The proposed architectures of the implemented controls can be found in Section VI. The results of the implementation of the GPI and PID controllers in the FPGA are provided and discussed in Section VII. Finally, Section VIII presents the conclusion of this paper. II. “B UCK ” C ONVERTER M ODEL Consider the “buck” converter circuit shown in Fig. 1. The system is described by the following set of differential equations: diL = −vo + Eu dt   1 dvo = −iL − C vo dt R L

y = vo

(1)

ZURITA-BUSTAMANTE et al.: COMPARISON BETWEEN THE GPI AND PID CONTROLLERS

where iL represents the inductor current and vo is the output capacitor voltage. The control input u representing the switch position function takes values in the discrete set {0, 1}. The system parameters are constituted by L and C which are, respectively, the input circuit inductance and the capacitance of the output filter, while R is the load resistance. The external voltage source exhibits a constant value E. The average state model of the “buck” converter circuit, extensively used in the literature [5], [16], [27], may be directly obtained from the original switched model (1) by simply identifying the switch position function u with the average control, denoted by uav . Such an average control input is frequently identified with the duty ratio function in pulsewidth modulation implementation. The control input uav is restricted to take values in the closed interval [0, 1]. From (1), the “buck” converter system is clearly a second-order linear system of the typical form x˙ = Ax + bu and y = cT x   E 0 − L1 (2) A= 1 b= L cT = [0 1]. 1 − RC 0 C Hence, the Kalman controllability matrix of the system C = [b, Ab] is given by  E 0 . (3) C= L E 0 LC The determinant of the controllability matrix is

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and the average control input is obtained as   1 ˙ 1 LC ¨ F+ F+ F . uav = E RC LC

(8)

Moreover, from the average model given in (1), we can see that the system is also observable from the output variable vo , i.e., the Kalman observability matrix given by   T   c 0 1 (9) O= T = 1 1 c A − RC C complies with the property of being full rank. Therefore, the system model is observable for the output y = F = vo . This fact establishes the reconstructibility of the system, i.e., all of the system state variables are parameterizable in terms of the input, output, and finite number of iterated integrals of the input and output variables (see [8]). By integrating both sides of (8) and by solving the variable F˙ , we have an integral estimator of the first time derivative of F ˙ = F



E LC

  t  1 1 F uav (τ ) − F (τ ) dτ − E RC 0

F = vo .

(10)

Note that, for nonzero initial states, the relations linking the actual values of the converter output voltage derivative to the structural estimate in (10) are given by

2

E = 0. L2 C

˙ + F˙ F˙ = F 0

The system is controllable and, hence, differentially flat (see [28]). This flat output for the “buck” converter system is obtained from the following proposition. Proposition 2.1: [27] The flat output of a linear controllable system in state space form

where F˙0 denotes the unknown initial rate of change of the output voltage.

x˙ = Ax + bu

III. GPI C ONTROLLER D ESIGN

(4)

is given, modulo a constant factor, by the linear combination of the states obtained from the last row of the inverse of the Kalman controllability matrix −1

F = [0, 0, . . . , 1][b, Ab, . . . , An−1 b] x.

Therefore, we can simply take the output voltage variable as a flat output [28] F = vo . The flatness of the system implies that all state variables of the system, including the control input variable, are parameterizable in terms of F = vo and a finite number of its time derivatives. Indeed vo = F

iL = C F˙ +

1 F R

From (8), we propose the following feedback control law for the stabilization of the “buck” converter output voltage around a desired constant reference value F : L ˙ 1 LC v+ F+ F E ER E v = −k3 F˙ − k2 (F − F ).

uav =

(5)

According to the previous proposition, the flat output of the “buck” converter is given by −1   E LC 0 iL L vo . (6) F = F = [0 1] E vo 0 LC E

(7)

(11)

(12)

For the GPI feedback controller, we replace the unmeasured ˙ given state variable F˙ by its structural estimated variable F in (10). However, this implies that the closed-loop system is ˙ , as acaffected by the constant estimation error present in F knowledged in (11). To suitably correct the destabilizing effect of the structural estimation errors and the effect of possible external perturbations, GPI control uses iterated integral error compensation as follows: L ˙ 1 LC v+ F+ F E ER E  ˙ v = −k3 (F ) − k2 (F − F ) − k1 γ − k0 η γ˙ = F − F

uav =

η˙ = γ.

(13)

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Fig. 2. PID control in closed loop.

Let e = F − F denote the stabilization error. The stabilization error dynamics is obtained by substituting (11) and controller (13) into the differential parameterization of the average control input given in (8). We obtain the GPI controller as (13) t F¨ = −k3 (F˙ − F˙ 0 ) − k2 (F − F ) − k1



F (τ ) − F dτ

0

t τ − k0





F (λ) − F dλ dτ.

0

(14)

Fig. 3. loop.

Output voltage transient responses of the “buck” converter in open

The closed-loop transfer function is readily found to be

0

The characteristic equation of integro-differential relation (14) in terms of the stabilization error is given by

H(s) =

e(4) + k3 e(3) + k2 e¨ + k1 e˙ + k0 e = 0. The values of the design parameters {k3 , k2 , k1 , k0 } are chosen so that the closed-loop characteristic polynomial p(s) = s4 + k3 s3 + k2 s2 + k1 s + k0

taking into account that ζ and ωn are positive quantities. Hence, the gains of the GPI controller are given by 2

k3 = 4ζωn

k2 = 4ζ

k1 = 4ζωn3

k0 = ωn4 .

ωn2

+

2ωn2

In order to compare the performance of the transient response of the GPI controller, a classical PID controller was also designed and implemented. The corresponding transfer function of the converter, obtained from the average model given in (1), is E LC 1 RC s

+

1 LC

while the transfer function of the PID controller is   1 + Td s . FPID (s) = Kp 1 + Ti s



1 EKp Td + RC LC



s2 +

EKp (1 + EKp ) s+ = 0. LC LCTi (18)

The coefficients Kp , Ti , and Td are chosen so that (18) becomes a third-order Hurwitz polynomial of the form  p(s) = s2 + 2ζωn s + ωn2 (s + α)

(19)

taking into account that ζ, ωn , and α are positive quantities. Equating the characteristic polynomial coefficients (18) with those of the desired Hurwitz polynomial (19), we obtain the following values of the parameters for the PID controller: 2ζωn αLC + ωn2 LC − 1 E EKp Ti = LCαωn2   LC 1 Td = α + 2ζωn − . EKp RC

Kp =

IV. PID C ONTROLLER D ESIGN

V0 (s) = 2 Uav (s) s +

The closed-loop characteristic polynomial of the PIDcontrolled system is then given by s3 +

has all of its roots in the left half of the complex plane. The controller parameters were chosen so as to achieve the following desired closed-loop characteristic polynomial: 2  (15) p(s) = s2 + 2ζωn s + ωn2

E (Kp Td Ti s2 + Kp Ti s + Kp ) LC 

. EKp Td (1+EK ) EK 1 s2 + LC p s + LCTpi s3 + RC + LC

(20)

(16)

V. D ESIGN R EQUIREMENTS OF THE C ONTROLLERS

(17)

Fig. 3 shows the open-loop response of the buck converter system with the following specifications: L = 1 mH, C = 100 μF, R = 100 Ω, E = 24 V, f = 48.828 kHz, Δvo /v0 = ¯av = D = 0.75 V (duty cycle) [4]. 0.013%, ΔiL = 0.092, and u The output voltage response is a steady-state error of 5.56%, and it has a settling time of 15 ms. On the other hand, we get that the diagram bode of the transfer function given by

The block diagram of the PID-controlled system is shown in Fig. 2.

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A. GPI Implementation Into the FPGA We rewrite the equations for the GPI controller as ˙ + a F uav = a1 v + a2 F 3 ˙ ) − k (F − F ) − k v = −k3 (F 2 1

t



F (τ ) − F (τ ) dτ

0

t τ − k0 0

˙ = F Fig. 4. Block diagram of the FPGA-based control system using the GPI or PID controller.

(16) with the same specifications has a gain margin Gm = Inf dB (at Inf rad/s) and a phase margin P m = 0.377 deg (at 1.58 × 104 rad/s). Given the fact that the buck converter system has an infinite gain margin, it can withstand greater changes in system parameters before becoming unstable in closed loop [30]. Since the system has this characteristic, we will design our controllers in closed loop with the following requirements: overshoot less than 4.32%, setting time less than 5 ms, steadystate error less than 1%, and maximum sampling time of 40 μs. In this case, we aim to have an overshoot less than 4.32%, a settling time less than 5 ms, and a steady-state error less than 1% for a desired output voltage of 18 V. We will tune in our controllers in closed loop through (15) and (19), with a damping coefficient of ζ = 0.707, α = 1000, and natural frequency of ωn = 2500. Hence, the following observations were noted. 1) The GPI controller gains obtained by the design requirements were k3 = 7070

k2 = 2.5 × 107

k1 = 4.42 × 1010

k0 = 3.90 × 1013 .

2) The PID controller gains obtained by the design requirements were kp = 0.15

Ti = 1.2 × 10−3

Td = 5.9 × 10−4 .

VI. C ONTROL A LGORITHM A RCHITECTURE The GPI and PID control laws and the PWM actuator for the regulations of the output voltage of the buck converter were implemented in a Spartan 3E board. Fig. 4 shows the block diagram of the FPGA-based control system based on the GPI or PID controller. The parameter values for the “buck” converter and the specifications were given in the previous section. The values of the design coefficients used by the GPI and PID controllers were obtained based on the design requirements given in the previous section. The only external hardware connected to the FPGA in measuring the “buck” converter output voltage was an ADC (ADC0820).



F (λ) − F (λ) dλ dτ

0

t (a4 u − a5 F ) dt − a6 F

(21)

0

where LC E E a4 = LC

a1 =

L ER 1 a5 = LC

a2 =

1 E 1 a6 = . RC a3 =

Now, to implement the GPI controller, it is necessary to obtain a discrete approximation of (21). Furthermore, if this method is used in the controller implementation on reconfigurable logic, it is necessary to consider that the most important condition is that the operation frequency of the controller must be a high value, and this feature directly depends on the application specifications. An important aspect in the discretization of (21) is obtaining a discrete approximation of the continuous integral. In the solution of this problem, we have used the Adams–Bashforth method of the second order [31], [32]. This method is given by 1 ˙ − y[n ˙ − 1]) y[n + 1] = y[n] + Δt (3y[n] 2

(22)

where Δt is the interval of time between two consecutive moments of the solution (usually called as the step of integration). It also needs knowledge of the current derivative y[n] ˙ and the derivative evaluated in a previous moment y[n ˙ − 1]. t Then, if the integral is defined by IF (t) = 0 (a4 u(t) − a5 F (t))dt, using the Adams–Bashforth method, it is defined as  1 ˙ ˙ [n − 1] [n] − IF IF [n + 1] = IF [n] + Δt 3IF 2

(23)

˙ [n − 1] = a4 u[n − ˙ [n] = a4 u[n] − a5 F [n] and IF where IF 1] − a5 F [n − 1]. On the other hand, if the integral is defined by I(t) = t ¯ 0 (F (τ ) − F (τ ))dτ , its discrete approximation is defined as  1 ˙ ˙ − 1] − I[n I[n + 1] = I[n] + Δt 3I[n] 2

(24)

˙ = F [n] − F¯ [n] and I[n] ˙ = F [n − 1] − F¯ [n − 1]. where I[n] t τ Now, if II(t) = 0 0 (F (λ) − F¯ (λ))dλdτ , its discrete

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Fig. 5. Architecture proposed for the discrete GPI controller implemented into the Spartan-3E1600 FPGA.

approximation is defined as

 1 ˙ ˙ − 1] − II[n II[n + 1] = II[n] + Δt 3II[n] 2

(25)

where   Δt 3 F [n]−F [n] −F [n−1]−F [n−1] ˙ II[n] =I[n] + 2 ˙ II[n−1] = I[n−1]   Δt 3 F [n−1]−F [n−1] −F [n−2]−F [n−2] + . 2 Hence, the discrete representation of (21) is defined as ˙ [n] + a F [n] uav [n + 1] = a1 v[n] + a2 F 3  ˙ [n]−k F [n]−F [n] −k I[n]−k II[n] v[n] = −k3 F 2 1 0 ˙ [n] = IF [n] − a F [n]. F 6

(26)

Based on (26), the GPI controller implementation on reconfigurable logic was realized. For this purpose, the Xilinx ISE Design Suite 12.2 tool and the Spartan 3E board were used; the Spartan 3E board, designed by Digilent Company, includes a Spartan-3E1600 FPGA. Furthermore, to acquire information of the buck converter, an ADC (ADC0820) was chosen. ADC0820 is an 8-b resolution converter, it offers a 2-μs conversion time, and it has a 0–5-V analog input voltage range. The GPI controller design is based on the top–down methodology, and the schematic description was chosen as top level. The GPI controller modules were modeled using the hardware description language VHDL (algorithm level modeling), generated using the Xilinx CORE Generator tool or using preoptimized elements that are included in the used device. The architecture proposed for the discrete GPI controller is shown in Fig. 5. Exploiting the independence existing in diverse modules, in each stage of the architecture, several modules can be working concurrently, and this allows obtaining high processing speeds; however, it uses many resources. It is clear that the processing in real time is relative to the application, i.e., based on the application, the interval of time

between the processing of two data must be chosen. So that our application operates in real time, the maximum time of processing in the GPI controller specifications is fixed at 40 μs. The GPI controller works with a frequency of 50 MHz (Clk_GPI). The implemented architecture is composed of 19 stages, and each of them needs 100 cycles to fulfill its function (2 μs). This indicates that the processing time of one datum is 38 μs [time between two consecutive data delivered by the controller to the next module (the PWM)]. The clock manager module generates the frequencies that are necessary for the GPI controller (Clk_GPI) and for the PWM (Clk_PWM) from the principal frequency of 50 MHz (Clk_main) (see Fig. 6). The principal element of this module is the digital clock manager (DCM). The DCM is embedded on the Spartan3E FPGA’s families, and it provides a flexible complete control over clock frequency, maintaining its characteristics with a high degree of precision despite normal variations in operating temperature and voltage. The Clk_GPI signal is the same as the Clk_main signal, but the DCM provides a correction clock feature, ensuring a clean Clk_GPI output clock with a 50% duty cycle. The Clk_PWM signal is derived from the input clock (Clk_main) by a digital frequency synthesizer included in the DCM. The frequency of the Clk_PWM is 25 MHz and also has a 50% duty cycle correction. The “GPI stage enable” function is also included in clock manager module (see Fig. 6). The “GPI stage enable” is a simple finite-state machine that generates the enable signals of the proposed architecture stages [Stage_en(1) . . . Stage_en(19)]. The description style adopted for this module was algorithm level modeling. The pulsewidth of all stage enable signals is tSE (1 Clk_main cycle and 20 ns). The time between two active stage enable signals is tS (100 Clk_main cycles and 2 μs). tF L is the time from an active Stage_en(1) to an active Stage_en(19) (1800 Clk_main cycles and 36 μs). tCE is the enable cycle time (1900 Clk_main cycles and 38 μs), and this is the time that the GPI controller needs to deliver new information to the PWM. The ADC control, normalization, and float-point encoder module was described based on algorithm level modeling. This module carries out three functions. First, it controls the

ZURITA-BUSTAMANTE et al.: COMPARISON BETWEEN THE GPI AND PID CONTROLLERS

Fig. 6.

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Clock manager module.

necessary signals to acquire information from ADC0820. Second, it normalizes the acquired information. The voltage range that the buck converter delivers to the GPI controller is 0–24 V, and the voltage that ADC0820 can process is from 0 to 5 V. Due to this, a noninverting amplifier with a gain of 0.25 is used to connect the buck converter to the ADC. Therefore, it is necessary to compensate this attenuation on the information obtained from the ADC; this process is called as normalization. Third, due to the range of results that the operations of the discrete GPI controller generates, it is necessary to use a floatingpoint format. For this intention, the IEEE Standard for Binary Floating-Point Arithmetic (IEEE Std. 754–1 985) [33] was chosen. The last function of this module is to codify the information normalized in the single-precision floating-point format. Xilinx ISE Design Suite 12.2 includes the CORE Generator tool, which allows generating preoptimized elements for Xilinx’s FPGA. Using this tool, the addition and multiplication operations in a single-precision floating point (standard Std-754) can be generated. In our discrete GPI controller architecture, the float point adder and multiplier modules have been generated using the CORE Generator. Finally, the result of the GPI controller must be delivered to an 8-b PWM. For this reason, the last two stages of the controller convert the results from single-precision fixed-point to 8-b unsigned binary. The float-point to fixed-point conversion and fixed-point to 8-b unsigned binary conversion modules are doing this work. Both modules are VHDL description based on algorithm level modeling.

Fig. 7. PWM module. TABLE I D ISCRETE GPI C ONTROLLER I MPLEMENTATION R ESULT

B. PWM Module A single up–down counter unit and one comparator unit are used to create the PWM signal required to drive the buck converter (see Fig. 7). The maximum count value of the counter, in conjunction with the speed of the clock used to drive the counter, determines the PWM period frequency Clk_PWM 2(maximum count + 1) 25 MHz = 48.828 kHz. = 2 × 256

PWM frequency =

The counter counts from zero to its maximum value and then from its maximum value to zero. The period of the PWM

is measured from zero point to zero point in the counter cycle. The compare unit compares the count value from the counter unit with the GPI controller output value. The compare unit has two PWM outputs: one is asserted when the count value is greater than or equal to the GPI controller output value, and the other is asserted when the count value is less than the GPI controller output value.

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Fig. 8. Architecture proposed for the discrete PID controller implemented into the Spartan-3E1600 FPGA.

The implementation result of the individual modules and the complete architecture for the discrete GPI controller are reported in Table I.

TABLE II D ISCRETE PID C ONTROLLER I MPLEMENTATION R ESULT

C. Discrete PID Controller Implemented on the FPGA In a manner similar to that used for the implementation of the discrete GPI controller, the discrete PID controller was synthesized on an FPGA. The equations for the continuous PID controller are defined as uav = Kp



F (t) − F (t) + Ki

t



F (t) − F (t) dt

0

+ Kd

 d F (t) − F (t) dt

(27)

where Ki =

Kp Ti

K d = Kp T d .

The discretization of (27) needs a discrete approximation of the continuous integral and a discrete approximation of the continuous derivative. By applying (22), the discrete approximation of the continuous integral is obtained. On the other hand, the discrete approximation of the continuous derivative is obtained based on the finite differences method of the first order [34] using the backward difference. This method is given by   y[n] − y[n − 1] ∂y . (28) ≈ ∂t n Δt Then, if the derivative is defined by D(t) = ∂(F¯ (t) − F (t))/∂t using the finite differences method, its discrete approximation is defined as D[n] − D[n − 1] D [n] = Δt 

where D[n] = F [n] − F [n] D[n − 1] = F [n − 1] − F [n − 1].

(29)

Hence, the discrete representation of (27) is defined as  uav [n + 1] = Kp F [n] − F [n] + Ki I[n] + Kd D [n]. (30) Based on (30), the PID controller was implemented on reconfigurable logic. This controller was implemented using the same tools and devices that are used for the GPI controller. The PID controller design is based on the top–down methodology, and the schematic description was chosen as top level. Fig. 8 shows the architecture proposed for the discrete PID controller. To obtain high processing speeds, in modeling this controller, the independence existing in some modules of the architecture is exploited. Therefore, several modules can be working concurrently. Fig. 8 shows that all of the discrete GPI controller modules were used in the architecture of the discrete PID controller. The PID controller works with a frequency of 50 MHz (Clk_PID). The implemented architecture is composed of ten stages, and each of them needs 100 cycles to fulfill its function (2 μs). This indicates that the processing time of one datum is 20 μs [time between two consecutive data delivered by the controller to the next module (the PWM)]. The implementation results of the complete architecture for the discrete PID controller are reported in Table II. VII. E XPERIMENTAL R ESULTS This section presents the experimental results of the performance of the GPI and PID controllers in regulating the “buck” converter output voltage. The experimental results depict the specifications of the transient response for each one of the controllers using a step reference signal. These specifications are the following: delay time td , rise time tr , time of peak tp , percentage of overshoot Mp , and settling time ts . In addition, we

ZURITA-BUSTAMANTE et al.: COMPARISON BETWEEN THE GPI AND PID CONTROLLERS

Fig. 9. Output voltage transient response of the “buck” converter with the GPI control action.

Fig. 10. Output voltage transient responses of the “buck” converter with the GPI and PID control schemes.

considered the recovery time trec when an armature-controlled dc motor load is suddenly connected to the converter output voltage terminals. Fig. 9(a) shows the GPI-controlled response of the “buck” converter output voltage for a constant reference voltage of 18 V. In this voltage response, an overshoot is not present in the recorded signal, while the settling time is approximately 4.64 ms. Fig. 9(b) shows the GPI average control law input signal. Fig. 10 shows the performances of the GPI and PID control laws in the stabilization task for the “buck” converter output voltage. As before, we used a constant reference of 18 V. The continuous line corresponds to the GPI-controlled response, while the dotted line corresponds to the PID-controlled converter. The settling time of the response of the “buck” converter output voltage through the PID controller is three times greater than that obtained with the GPI controller. The output voltage transient response of the buck converter with the GPI control scheme exhibits a different dynamic performance as that of the PID control scheme due to the structure of the controller, since this controller incorporates a double integrator of the error regulation. As a consequence, GPI controller tuning was done through a fourth-order Hurwitz polynomial, while PID controller tuning was done with a third-order Hurwitz polynomial. To illustrate the robustness of the GPI controller, in comparison to that of the PID control, we made a test by suddenly connecting a dynamic load (represented by an armature-controlled dc motor) at the output of the “buck” converter. The continuous

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Fig. 11. Output voltage response of the “buck” converter with sudden connection of a dc motor.

Fig. 12. Output voltage transient responses of the “buck” converter with the GPI scheme and average voltage of the GPI control.

line shown in Fig. 11 shows the behavior of the temporarily perturbed converter’s output voltage and the fast recovery of the output voltage to the desired reference signal when the converter is controlled via a GPI controller option. The GPI controller also results in reduced noise features affecting the regulated output voltage response (see Fig. 11). The reduced noise in the response is due to the fact that the GPI controller incorporates the estimated value of the first time derivative of F , while the PID controller uses the backward difference scheme to calculate the value of the first time derivative of F . In addition, the output voltage with the GPI controller and the average voltage of the controller uav are shown in Fig. 12(a) and (b), respectively, which shows that the maximum voltage uav is 5 V and that the GPI control immediately responds to the external perturbations. Fig. 13 shows the performance index between the GPI and PID controllers when a sudden dynamic load (dc motor) that is parallel to the load resistance is connected to the buck converter. This performance index is the integral of the square of the error (ISE), which is defined as [35] T ISE =

e2 (t) dt.

(31)

0

The upper limit T is a finite time chosen somewhat arbitrarily so that the integral approaches a steady-state value. It is usually convenient to choose T as the settling time ts . The step response

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TABLE III C OMPARISON B ETWEEN THE GPI AND PID C ONTROLLERS

Extensive tests were performed under different load conditions, including the following: 1) sudden static load changes by activating a resistive load in parallel with the output load resistance of the “buck” converter; 2) sudden dynamic load insertions in parallel with the load resistance; and 3) the use of a magnetic brake on the motor with sudden insertions of the brake. Figs. 10 and 11 clearly show how the GPI control action presents a faster response than that achievable with the PID controller for a constant reference signal. Also, the GPI controller shows a faster recovery in output voltage regulation than the PID controller when the system is subjected to sudden unforeseen changes in the load.

VIII. C ONCLUSION

Fig. 13. Calculation of the ISE of the GPI and PID controllers.

of 18 V for the GPI and PID feedback controller buck converter systems is shown in Fig. 13(a), and the errors are shown in Fig. 13(b). The squared errors are shown in Fig. 13(c), and the integral of the squared errors is shown in Fig. 13(d). This criterion will discriminate between excessively overdamped and excessively underdamped systems. The minimum value of the integral occurs for a compromised value of the damping. The performance index of (31) is easily adapted for practical measurements because a squaring circuit is readily obtained [35]. Hence, using a quantitative method, we verified the performance of the buck converter system and noted that the integral of the square of the errors for a damping coefficient of 0.707 (the error index of the GPI controller) was smaller than the PID controller [see Fig. 13(d)]. Table III exhibits the comparison between the performances of the two synthesized controllers. The main specifications of the transient response, along with the sudden dynamic load insertion recovery time, are depicted in this table. The bandwidth of the GPI controller is greater than the PID controller (see Table III), and these frequencies are calculated in the closed loop through the damping ratio and settling time [30]. The damping coefficient value is 0.707, while the values of the settling time are the following: 4.64 ms for the GPI and 13.64 ms for the PID.

In this paper, we have applied the GPI control scheme, synthesized via an FPGA implementation, for output voltage regulation in a dc/dc power converter that is “buck” type. The performance of the GPI control action was compared under several load conditions with that obtained from a classical PID control action also synthesized via an FPGA. We conclude that the GPI controller has a better transient response than that achieved with a PID control action. When we connect static and dynamic loads to the “buck” converter output, we have observed that the GPI control results in a significantly faster response than that obtained with the PID control with regard to the output voltage recovery time to the desired reference. Finally, the experimental results show the effectiveness of the FPGA realization of both the GPI and PID controllers, in this case, programmed into the FPGA, with relatively the same ease of implementation. Since the ISE index shows that the GPI control obtains a better performance from the buck converter than the PID control, this methodology can be used to design switched-mode power supplies with an efficiency greater than 90.

IX. F UTURE W ORKS As a continuation of this research, the following future works are proposed: 1) new controller implementations on FPGA, like passivitybased control, antiwindup, RSR polynomial, backstepping, etc; 2) in order to obtain a high-frequency operation, implementing a pipeline structure of the proposed architectures.

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Eric William Zurita-Bustamante received the B.S. degree in electronic engineering from the Universidad Tecnológica de la Mixteca, Huajuapan de León, Oaxaca, Mexico, in 2007, where he is currently working toward the M.Sc. degree. His research interests include development and implementation of hardware architectures on reconfigurable logic for power electronics, automatic control, and image processing applications.

Jesús Linares-Flores received the B.S. degree in electronics engineering from the Universidad Autónoma de Puebla, Puebla, Puebla, Mexico, in 1994, the M.Sc. degree from the Universidad de las Américas—Puebla, Cholula, Puebla, in 1999, and the Ph.D. degree from the Centro de Investigación y de Estudios Avanzados del I.P.N., México, DF, México, in 2006. Since 2007, he has been the representative of the Automatization and Control of the mechatronics systems UTMIX-CA-24-PROMEP. He is the Director of the Institute of Electronics and Mechatronics, Universidad Tecnológica de la Mixteca, Huajuapan de León, Oaxaca, Mexico. He is the author of 20 technical papers in credited journals and international conferences. He is interested in the theoretical and practical aspects of feedback regulation of linear and nonlinear dynamic systems, with special emphasis on passivity-based control techniques and its applications in power electronics.

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Enrique Guzmán-Ramírez received the B.S. degree in electronic engineering from the Escuela Superior de Ingeniería Mecánica y Eléctrica—IPN, México, DF, México, in 1992 and the M.Sc. degree in computer engineering (specializing in digital systems) and the Ph.D. degree in computer science from the Centro de Investigación en Computación—IPN, Mexico, in 2003 and 2008, respectively. He is currently a Research Professor with the Universidad Tecnológica de la Mixteca, Huajuapan de León, Oaxaca, Mexico. His research interests include development and implementation of hardware architectures on reconfigurable logic for control, artificial neural networks, and image processing applications.

Hebertt Sira-Ramírez (SM’85) received the Electrical Engineers degree from the Universidad de Los Andes, Mérida, Venezuela, in 1970 and the Electrical Engineers degree, the M.Sc. degree in electrical engineering, and the Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1974, 1974, and 1977, respectively. He is the coauthor of several books on automatic control and the author of over 400 technical papers in credited journals and international conferences. He is interested in the theoretical and practical aspects of feedback regulation of nonlinear dynamic systems, with special emphasis on variable structure feedback control techniques and its applications in power electronics. Dr. Sira-Ramirez is a Distinguished Lecturer of the IEEE and a member of the IEEE International Committee.