caseode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional. NAND/. NOR logic in terms of circuit delay, ...
528
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 4, AUGUST 1987
A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic KAN
—Differential
Abstract
circuit
technique
caseode voltage switch (DCVS)
which has potential
NOR logic in terms of circuit logic
flexibility.
advantages
delay, layout
logic
is carried
out
of fnfl adders designed
Specifically,
comparisons
and two
different
dyuamic
case,
DCVS
forms
implementations
of both
two
of static
conventional
NORA
and DOMINO
are
gation
delay time, and average power dissipation.
appears
gate capacitance,
to be superior
to frill CMOS
device count but inferior two technologies
circuits,
dynamic
0’
to input
‘UAL‘AIL X;-+ CONTROL
and com-
The speeds of the
case, DCVS
can be faster
logic, but only at the expense
I
Fig. 1,
Block diagram of a DCVS circuit. The load circuitry nected to nodes Q and Q‘.
tion, age
of
on
area,
both
and
All
these logic
this
purpose
building here
parameters sipation. needed
CMOS
in digital
SPICE of Area
area,
circuits.
simulations input
is represented
to implement
the
to
by adder
reasonably
The
comparison
assess
the
speed, the number loading
1)
TECHNIQUES
FOR DCVS
To
LOGIC
to
reported dis-
of transistors is quantified
Manuscript received August 29, 1986,; revised January 26, 1987. This work was supported by the Natural Sciences and Engineering Research Council of Canada. The authors are with the Electrical Engineering Department, University of British Columbia, Vancouver, B.C. V6T 1W5, Canada. IEEE Log Number 8714872.
the input of
the
vector switching
x = (xl, c . . . x.) function
when
X =(X1,...,
Q(x), node
Xu) is the false vector
is the true then
the
G and
the
of Q(x),
then the reverse holds.
full-
complex,
power
2)
logic
the
when
output Q is disconnected from node Q’ is connected to G; and
make
performance
and
CIRCUIT
vector
is suited
yet
and
to
using
adder
of operation
be
[3].
DCVS
forms
frequency
The basic DCVS circuit comprises two parts: a binary decision tree and a load (see Fig. 1). The tree is specified such that:
based
compared full
loading,
further
technique.
The
is a common,
appear
has
can
circuit
logic
vehicle.
A
they
methods
would
II.
cover-
procedures
CMOS we have
also
[2].
that
at the maximum
Speed is assessed by time. Power dissipa-
dissipa-
DCVS
tabular
features
possibility,
as it
block uses
and
promising
as a test
fact
is computed
propagation
which
can provide faults
is the
(K-maps)
conventional
circuit
dynamic
gate capacitance.
the worst-case
of each circuit.
NAND/NOR power
[1].
which
straightforward
worthwhile a very
investigate more
using
clelay,
flexibility
logic
technique
over traditional
property circuits
maps
DCVS
this
logic
DCVS
designed
adder
and
switch (DCVS)
circuit
of circuit
stuck-at
of
Karnaugh
and
in terms
self-testing
attraction readily
CMOS
to have advantages
layout
tion
cascode voltage proposed
techniques
an inherent
is con-
of
INTRODUCTION
INFERENTIAL
circuit
~
and power dissipation.
L
is claimed
‘uNcTION Q ‘x)
JG
simulating
is a recently
[
FOR
and
in terms of the input
D
Dcvs WEE
:;
SIGNALS xn~ x+--j
propa-
capacitance
..l
xl--i
and, in the
required,
II
11 . . . . . . 1. . . . . . . . . . . 1. . .
In the static case, DCVS
in regards
In the dynamic
CMOS
device count
LOAO .. . . . . . . . . . . . . . . . . . . . .
design
The parameters
of transistors
in regards to power dissipation.
are similar.
than more conventiottaf increased
number
the
Vdd
..1... .. .. ....
techniques.
implementations
logic.
pared
and
of
CMOS
full
DCVS NORA
+
aud
logic
SPICE,
circuit
a static
MEMBER, IEEE
NAND/
of DCVS using
using the different
are made between
between
input
comparison
L. PULFREY,
logic is a CMOS
power dissipation,
by simulation,
performance
DAVID
AND
over conventional
density,
In this paper a detailed
conventional
M. CHU
There are two trees required to implement a full adder, one to perform the sum and one to perform the carry function (see Fig. 2). These circuits, which were designed using the K-map procedure described in [3], are used as the tree circuits for all the DCVS circuit forms examined in this paper. The various DCVS forms differ in their load circuitry, as is now described. The load for a static DCVS
circuit
is the simple
latch
shown in Fig. 3. Depending on the differential inputs, either node Q or Q’ is pulled down by the DCVS tree network. Regenerative action sets the PMOS latch to static outputs
0018-9200/87/0800-0528$01.00
Q and Q’ of V~~ and ground 01987 IEEE
or vice versa. The
CHU AND PULFREY: COMPAIUSON OF CMOS CIRCUIT TECHNIQUES
Ci?
529
?
co
f’
T1
12
T3
T4
f VREF
Q Q’ . . . .. . .. . . . . . .. ..
* +: .: .: &i
Dcvs TREE
! j
......... ..... ]G
...1
(a)
(b) Fig. 4.
Fig. 2. sum,
The load for a static DSL circuit.
The DCVS trees for a full adder. (a) The circui~ providing the S(A, B, C) = A + B + C. (b) The circuit yielding the carry,
CO(A,B, C)= AB+BC+ CA.
’9’ 1
f
11
f’ Q’ ,... 1. . . . . . . . . . . L. . .
T2
-+: : \ DCVS TREE +
Q’
[
.. . . . . . . . . . ... . . . . . ..
--i: ; ~ DCVS TREE
‘1-l
~
i -’------”-l-i--”””-~
Fig. 5.
+7
Fig. 3.
The load
and circuit
Gnd
arrangement circuit.
for
a DCVS
DOMINO
The load for a static DCVS circuit.
4 logic
trees do not pass any direct
current
after
the latch
sets. A variation
of this static DCVS
split-level (DSL) logic circuit n-transistors T3 and T4 with reference
voltage
at nodes
Q and Q’. If
Q and
Q’
level.
from
at V~~/2.
from
Suppose
its low-current
drive state very quickly,
The voltage
+ ~k, where node
Q is
2.5 V (i.e., assume V~~ = 5 V) to a low
T1 switches
current
V~~~ is set to v~~/2
voltage of the n device, then the nodes
are clamped
down
is the differential
V~~~ are added to reduce the logic swing
~k is the threshold pulled
circuit
[4] shown in Fig. 4. Two their gates connected to a
state to its high-
because T4 is initially
times
Q’ is raised up to 2.5 V until T3 is in the cutoff DSL circuits would be expected to be about two
faster
than
standard
DCVS
circuits
Fig. 6.
The load and circuit arrangement for a DCVS NOM section.
pipelined
OFF.
on node f’ goes up to 5 V because T1 is fully
ON. Node
mode.
+
on account
of
menting
logical
structure flexibility.
functions.
In its original
consists of n- and p-logic The p-logic gates usually
and consume
form
the NORA
gates to enhance logic cause long delay times
large areas. Using DCVS
logic in the NORA
the need for logic swings of only half the rail-to-rail voltage difference. This should result in a reduction by two
technique will eliminate p-logic gates because of the inherent availability of complementary signals. The general
times of circuit.
structure of a DCVS NORA pipelined section consisting of only one dynamic gate is shown in Fig. 6. This type of
the
Turning consider
charges
now first
needed
to dynamic
the DOMINO
to be manipulated operation
of DCVS
[5] configuration
Nodes
Q and
Q’ are precharged
charge
phase ($ = O) and either
to high node
in
the
circuits,
of Fig. 5 [1]. during
Q (node
the pref)
or Q’
(f’) discharges to low during the evaluation phase (~ = 1). Transistor T1 (or T2) is a high impedance p transistor which serves as the feedback device to maintain the high logic level at node Q’ (or Q), where charges may be lost due to charge sharing [6]. For dynamic operation NORA
(NO
RACE)
circuit logic
technique design,
developed
techniques
pipelined
architectures,
[7] are suitable
for imple-
the
8 X 8 pipelined
for use in a heavily
case, for
example,
multiplier
[8].
of
pipelined a newly
As Fig. 6 indicates, the load circuitry is symmetrical, and thus, for analysis purposes, only one side of it need be considered. During the evaluation phase (-~ = 1), node Q is either floating or discharged depending on the inputs. The output
register
can be either of
is suitable
as in
acts as a clocked high
or low.
inverter,
During
and tlhe output
the precharge
phase
(0= O), the ground path of the register is blocked. If the output resulting from the previous evaluation is high, then
530
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 4, AUGUST 1987
+ -’+
c’
B+ c+ *
& i-a
A+
A
