ter and converter circuit applications cannot use this .... Table 1: PSD data of simple SI memory cells with ... ing the above PSD analysis, we nd that the THD.
A Comparison Of First And Second Generation Switched-Current Cells Peter M. Sinn
Northern Telecom 185 Corkstown Road Nepean, Ontario K2H 8V4
Gordon W. Roberts
Microelectronics and Computer Systems Lab. Department of Electrical Engineering McGill University, 3480 University Street Montreal, Canada H3A 2A7
Abstract The Switched-Current (SI) technique is a circuit method that enables analog sampled-data circuits to be realized with a standard digital CMOS process. At this time it is fair to say that SI circuits are realized from either rst- or second-generation type current memory cells, with the latter cell being favored owing to its perceived better sensitivity behavior. Unfortunately, however, the second-generation current memory cell has some serious circuit drawbacks. These include large internal transient glitches that cause large linear and nonlinear circuit errors, as well, requires a more complicated circuit. When all factors are considered including the sensitivity issue, it is our opinion that the rst-generation cell is superior to the secondgeneration memory cell. In this paper we shall present our arguments and experiments that back up these claims.
spond to the time of their introduction. Schematics of these circuits and their transfer functions are shown in Fig. 1. Note that the second-generation cell has 2 outputs; a direct and a mirrored output. A description of their operation can be found in [1, 4]. Ib
Iin
Sa ; 1 )
Iout
(
Ma
Mb
Io (z) = (W=L)b z, 12 Iin (W=L)a
(a)
Iin
S ; 1 )
Ib (S3 ; 2 )
( 1
Ib
Iod
A
Introduction The Switched-Current (SI) design technique [1, 2, 3] has received considerable attention recently as an alternative means for analog sampled-data signal processing. Its superiority over its counterpart, the Switched-Capacitor technique, comes from the fact that it can be implemented in a low-cost digital CMOS fabrication process. The basic circuit of the SI technique is the current memory cell. As its name suggests this circuit stores an input current in the form of a charge stored on the gate-source capacitance of a MOS transistor allowing this current to be accessed at a later time. Two di erent forms of this circuit has emerged since the introduction of the SI technique, duly labeled as the rst and second-generation current memory cell to corre-
Ib
S ; 1 )
( 2
Ma
Mb
Iom Iom (z) = (W=L)b z, 12 Iin (W=L)a Iod (z) = z, 12 Iin
(b)
Figure 1: Simple SI memory cells and their corresponding transfer functions: (a) 1st-generation (b) 2nd-generation. On the contrary to what is generally believed, the second-generation cell with mirrored output has the same sensitivity as the rst-generation cell. This should be obvious as the make-up of their respective transfer functions are the same. The better sensitivity of the second-generation cell comes about only when the direct output of the memory cell is used. In
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x 10 5 0 -5 0
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-.- input current
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4m/1.2m. The sizes of all memory transistors were made the same. In order to retrieve the output current, the output nodes of each circuit were connected to a constant voltage source whose level was set at the nominal drain-to-source voltage of the output transistor of the memory cell. The current passing through each voltage source is therefore equal to the appropriate output current.
1; S1 01; S2 2; S3
switch ON switch OFF
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x 10
| output current
Figure 2: Transient response: (a) 1st-generation cell (b) mirrored output of 2nd-generation cell (c) direct output of 2nd-generation cell. such a case, the sensitivity to component variations is zero. This is probably the only positive attribute of the second-generation cell. Unfortunately, most lter and converter circuit applications cannot use this variant of the second-generation memory cell, as nonunity current gain is usually necessary. As such, little sensitivity advantage is gained by using the secondgeneration cell. We begin this paper by performing a comparison of the two memory cells in terms of their transient behavior and linearity performance. The analysis will be extended to the SI delay cells and integrators, as these two elements form the basic components of FIR and IIR lter circuits, respectively. Finally, a conclusion will be given in the last section of this paper.
1st Gen. Vs. 2nd Gen. To investigate the behavior of the rst- and secondgeneration current memory cell we performed a simple HSPICE simulation. In each case, the two cells were clocked at a rate of 500 kHz and fed by a 20 kHz sampled-and-held input sinusoidal current signal with an amplitude of 10 A, leading to a drain current modulation factor of 50%. Each memory transistor was modeled after a typical device found in a 1.2 m CMOS process with an aspect ratio (W=L) of 400m/60m. Similarly, the switches were designed using MOS switches with an aspect ratio of
Figure 3: A 3-phase clocking scheme for the secondgeneration current memory cell. The results of the HSPICE transient analysis is illustrated in Fig. 2. The top graph indicates the input{output transient behavior of the rst-generation memory cell and the bottom two graphs illustrate the input{output behavior of the second-generation cell with respect to the two output terminals. In the case of the rst-generation memory cell we see that the output current is a close inverted replica of the input signal delayed by half a clock period. In the case of the mirrored output from the second-generation memory cell we see from the middle graph of Fig. 2 that the input-output current behavior is quite similar to the rst-generation cell with additional glitching present. In the case of the direct current output as shown in the lower graph the output current is available over one clock phase instead of a complete clock period and large levels of glitching are present. These glitches are a result of an internal node changing from a low impedance state to one of high impedance during the non-overlapping period of the clock. This is an obvious problem with the second-generation memory cell. As an attempt to remedy this problem, a 3-phase clock scheme shown in Fig. 3 is suggested. The purpose of this clock scheme is to shorten the existence of the high-impedance node. An HSPICE analysis reveals that the modi ed clock scheme reduces the level of glitching present but does not eliminate it completely. As a means to measure the linearity of the rstand second-generation cell (with the modi ed clock scheme), we computed the Power Spectral Density (PSD) associated with the output transient waveforms using the FFT algorithm [7]. Some of these key data are summarized in Table I for easy reading. We see
from this table that the rst-generation cell exhibits a much better performance than the second-generation memory cell in terms of DC o set and linearity. Furthermore, based on the data generated, the Total Harmonic Distortion (THD) was computed for each cell. In the case of the rst-generation cell, the THD was found to be 0.0873%, and for the second-generation cell, 0.0936% and 0.210% for the mirrored and direct outputs, respectively. With only a 2-phase clock scheme the THD of the second-generation cell rises to an unreasonable level of 3.55%. This increase in linearity error shows the impact of the transient glitches on the memory cell. The e ect can be understood by considering the following: the residual current creating the glitches enters node A of Fig. 1(b) at the end of clock 1 and leaves at the beginning of clock 2 . As a result of changing circuit conditions, a voltage spike is created having di erent rise and fall rates. Since the drain terminal of the memory transistor experiences this changing voltage, a net charge is coupled through the drain-gate capacitance to its gate terminal, thus introducing memorization errors. Harmonic 1st gen. 2nd gen. 2nd gen. tone direct o/p mirrored o/p DC -47.03dB -44.35dB -48.46dB principal -0.038dB -0.095dB -0.053dB second -61.42dB -53.69dB -60.73dB third -77.97dB -75.98dB -77.12dB fourth -80.97dB -89.26dB -89.12dB THD 0.0873% 0.210% 0.0936% Table 1: PSD data of simple SI memory cells with modi ed clock scheme incorporated. One means to minimize the impact of glitches on the operation of the second-generation current memory cell is to incorporate some form of cascoding. At this time it appears as though the regulated cascode memory cell [8] is the most robust to such errors. Repeating the above PSD analysis, we nd that the THD for the rst-generation memory cell has a THD of 0.0215% and the second-generation memory cell has a slightly higher THD of 0.0298% at each output. Clearly, cascoding improved the overall linearity of the two memory cells. The rst-generation memory cell remains, however, slightly more linear than the second-generation memory cell.
Other SI Structures SI memory cells are generally incorporated into various analog signal processing schemes instead of act-
Iin
Iout 1
2
Ma
Mb
Mc
Md
(a)
Iin 1
2
1
1 Ma
Iod
Iom
2 Md
Mb (b)
Figure 4: SI delay cells: (a) rst-generation (b) second-generation. ing as a memory element alone. Such schemes include FIR and IIR ltering, and data conversion. The central building blocks for such circuits include delay and integrator cells, each imposing di erent circuit conditions on the memory cell. Circuit schematics for the delay cell are shown in Fig. 4. In Table 2 we present an extensive summary outlining the linear and nonlinear operation of the regulated-cascode delay cell. Harmonic tone DC principal second third fourth THD
1st gen.
2nd gen. mirrored o/p -76.84dB -30.27dB -0.0198dB -0.3209dB -86.63dB -29.55dB -89.96dB -32.56dB -96.44dB -34.31dB 0.00709% 5.5107%
2nd gen. direct o/p -30.33dB -0.3204dB -29.55dB -32.56dB -34.31dB 5.5106%
Table 2: PSD data of SI regulated-cascode delay cells. According to Table 2, the second-generation delay cell exhibits severe harmonic distortion even with the regulated-cascode circuit enhancement incorporated. Thus, we conclude that this delay cell type should not be used for linear circuit application. On the contrary, the rst-generation delay cell demonstrates superb linearity performance. Such results are consistent with those obtained earlier for the memory cells. It is interesting to note that for the rst-generation simple
cell arrangement (not tabulated), the second and third harmonics are all less than 50 dB with a THD less than 0:2%. This implies that these cells are acceptable for most low performance designs where accuracy can be sacri ced for lower power supply and smaller layout area. For high performance circuits, the rstgeneration delay cell is still recommended because of its better linearity. Iin
1 M1
Io2
2 M2
M3
M4
1 2
Io1
1 M2
M1
Md
Mo1
1st gen.
2nd gen. inverting o/p -59.03dB -38.74dB -0.5141dB -0.8841dB -78.94dB -48.78dB -78.19dB -54.43dB -86.92dB -70.47dB 0.01878% 0.4639%
2nd gen. non-inv. o/p -32.85dB -1.2035dB -42.76dB -48.40dB -64.40dB 0.9629%
Acknowledgements
Mo1 (a)
Iin
Harmonic tone DC principal second third fourth THD
Table 3: PSD data of regulated-cascode SI damped integrator with modi ed clock scheme incorporated.
Mo2 Io1
Md
is a result of high levels of glitching present in such circuits.
Io2
Mo2
(b)
Figure 5: SI damped integrators: (a) rst-generation and (b) second-generation. A similar analysis was performed for the damped integrators of Fig. 5. A novel 4-phase clock scheme1 and a regulated-cascode con guration were incorporated. The PSD results are tabulated in Table 3. Once again, the rst-generation integrator out performed the second-generation cell by nearly a factor of 25.
Conclusions Based on the analysis presented in this paper, we have come to the conclusion that SI circuits created from rst-generation memory cell are superior to those created with second-generation cell in linearity and in ease of use. Although the second-generation cell with a direct output is component invariant, such a cell is limited to low-performance applications. This 1 A similar clock scheme was developed independently by de Queiroz et al [5].
The work presented herein has been supported by NSERC and by the Micronet, a Canadian federal network of centers of excellence dealing with Microelectronic Devices, Circuits and Systems for Ultra Large Scale Integration.
References [1] J. B. Hughes, N. C. Bird, I. C. Macbeth, \Switched currents { a new technique for analog sampled-data signal processing," IEEE ISCAS'89 Proceedings, pp. 1584-1587, May 1989. [2] G. Wegmann, E. A. Vittoz, "Very accurate dynamic current mirrors," Electronics Letters, vol. 25, pp. 644-646, May 1989. [3] T. S. Fiez, D. J. Allstot, \CMOS switched-current ladder lters," IEEE Journal of Solid-State Circuits, vol. 25, no. 6, pp. 1360-1367, Dec. 1990. [4] J. B. Hughes, I. C. Macbeth, D. M. Pattullo, \Second generation switched-current signal processing," IEEE ISCAS'90 Proceedings, pp. 2805-2808, May 1990. [5] A. C. M. de Queiroz, P. R. M. Pinheiro, \Switching Sequence E ects in Switched-Current Filters," IEEE ISCAS'93 Proceedings, pp. 982-985, May 1993. [6] P. M. K. Sinn, Master Thesis, Dept. of Elect. Eng., McGill University, 1994. [7] P. J. Crawley, G. W. Roberts, "Predicting harmonic distortion in switched-currentmemorycircuits," IEEE Trans. on Circuits and Systems { I: FundamentalTheory and Applications, Vol. 41, No. 2, pp. 1-14, Feb. 1994. [8] C. Toumazou, J. B. Hughes, D. M. Pattullo, \RegulatedCascode Switched-Current Memory Cell," Electronic Letters, vol. 26, no. 5, pp. 303-305, 1st March 1990.
