A comprehensive 2-D inductance modeling approach ... - IEEE Xplore

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 6, DECEMBER 2002

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A Comprehensive 2-D Inductance Modeling Approach for VLSI Interconnects: Frequency-Dependent Extraction and Compact Circuit Model Synthesis Gerard V. Kopcsay, Member, IEEE, Byron Krauter, Member, IEEE, David Widiger, Member, IEEE, Alina Deutsch, Fellow, IEEE, Barry J. Rubin, Member, IEEE, and Howard H. Smith, Member, IEEE

Abstract—Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix [2], [20] and its inverse [3], [9], 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods [29]. Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach used in [8] and [28]. It then extends the extraction algorithm in [29] to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis. Index Terms—Finite pole approximation, frequency dependence, inductance, loop inductance, model order reduction, partial inductance, pole residue, rational polynomial, three-dimensional (3-D), transmission lines, two-dimensional (2-D), VLSI interconnects.

I. INTRODUCTION

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ECENT papers [4], [13], [14] have advocated the use of complex three-dimensional (3-D) inductance models in VLSI design and analysis. While an accurate 3-D inductance model will always produce the correct answer—provided the magneto quasi-static approximation, which is the basis of RLC circuit analysis, is valid—3-D models are both impractical and

Manuscript received December 19, 2001. G. V. Kopcsay, A. Deutsch, and B. J. Rubin are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]; [email protected]; [email protected]). B. Krauter and D. Widiger are with IBM Microelectronics, Austin, TX 78758 USA (e-mail: [email protected]; [email protected]). H. H. Smith is with the IBM eServer Development Laboratory, Poughkeepsie, NY 12601 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2002.801574

unnecessary for most VLSI interconnect analyses. When a VLSI chip is designed to work at very high frequencies, its power grid conductors on the thick upper level metal layers will be closely spaced and continuous, and its power supply well decoupled with on-chip capacitors. These good design practices not only will insure high-frequency operation but will also make inductive effects easier to model. To a first approximation, the current loops will be two-dimensional (2-D), and long interconnect lines can be modeled as transmission lines. It is explained in [7] that any two uniform parallel conductors that are used to transmit electromagnetic energy—for example, the signal and its return—can be considered transmission lines. The return can be a ground plane, a ground conductor, or a mesh of ground and power lines on many layers interconnected with vias. Transverse electromagnetic mode (TEM) or quasi-TEM wave propagation is ensured if the effective cross-section is much smaller than the wavelength [6], [7]. Inductive effects are important for lines that behave as transmission lines. Such lines have lengths that are comparable to the wavelength or have delays comparable to the rise time. Since the length is much larger than the effective cross section, 2-D analysis is adequate. This is why transmission-line analysis is performed in terms of the characteristic line parameters, namely, R, L, C, and G, which are defined as the per unit length resistance, inductance, capacitance, and conductance, respectively. The 2-D versus 3-D inductance model question can also be viewed as a question of whether the return current paths (and hence the current loops) are known a priori. If the return current paths are both unknown and three-dimensional, 3-D partial inductance (or susceptance) models are needed to model inductive effects. If, however, the current loops are known to be two-dimensional, the frequency-dependent behavior of long interconnects can be obtained from 2-D analyses. With this work, the frequency dependence can be approximated with lumped-element circuit models for both uncoupled and coupled lines. The resulting series impedance circuit models can be used in lumped circuit transmission-line models. Because the question of 2-D versus 3-D models centers around the issue of current loops, this paper begins with a discussion of partial and loop inductances. The background section describes the conversion of partial to loop inductances for two, three, and parallel wires when driven at their ends

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by Thevenin sources. The 3-D partial inductances of the two-wire example are shown to reduce to the 2-D wire-pair loop inductance when a long loop is examined. It is also shown for the two- and three-wire examples that the loop inductance and loop resistance can be combined with wire-to-wire capacitances to form common-ground lumped-element circuit transmission-line models. The background section is concluded by describing the frequency-dependent characterization of multiple signal wires with multiple ground wires where each wire has been cross-sectioned multiple times to capture skin effect. In this paper, we will use signal wire and interconnect lines interchangeably. The background presented here explains how 2-D partial inductance models can be manipulated to form crude circuit models for VLSI interconnect analysis. Section II defends the 2-D modeling approach. A large VLSI interconnect example is modeled with sparse 3-D models to show that the necessary conditions for 2-D loop inductance modeling exist. The most critical of these conditions is that the nearby power distribution currents run parallel and are equal and opposite to the interconnect currents. In this section, the differences between return current flow in RC and RLC models are presented and discussed. This paper then solves two of the remaining problems with VLSI inductive-interconnect analysis. First, a novel 2-D partial inductance extraction approach using conformal maps is described. It effectively incorporates distant coplanar ground planes into the frequency-dependent 2-D loop impedance characterization first described in [29]. Finally, a novel synthesis technique is described that approximates the frequency-dependent behavior of transmission-line series impedances with compact circuit models. Similar to moment matching, this synthesis method can create compact circuit models for both coupled and uncoupled lines to capture skin effect, edge effects, and proximity effects. II. BACKGROUND This section will discuss partial and loop inductances and show how 3-D partial inductances can be folded into 2-D loop inductances when signal and return current are equal and opposite. The equivalence between 3-D and 2-D partial inductances for long interconnects is also discussed.

Fig. 1. Two circular wires with radius and center-to-center separation d.

a property of closed loops. Heaviside, for example, advocated the exclusive consideration of closed circuits, and as a means of securing external continuity, he proposed artificial return paths that would radially diverge from the positive terminal and radially converge on the negative terminal [17]. Krauter and Pileggi formulated stable, sparse partial inductance matrix approximations by shifting and truncating partial inductances [20]. Although their approximation affected every nonzero element in the matrix, it had little or no effect on the high-frequency loop inductances observed in subsequent circuit simulation. When a multiconductor problem is described by a set of partial inductances, the sum of the partial self and partial mutual inductances along any closed loop path will yield the total loop inductance of the path. The partial mutual inductances are, of course, appropriately weighted by either 1 to account for the relative orientation of segment currents [23]. The same holds true for systems of more than one loop. The mutual inductance between two loops can be obtained via the appropriate sum of partial mutual inductances between loops. Furthermore, when individual conductor segments are broken up into multiple parallel conductor segments, high-frequency phenomena such as skin effect, edge effects, and proximity effects can be analyzed [29]. III. CREATING LUMPED-ELEMENT CIRCUIT MODELS USING 2-D PARTIAL INDUCTANCES The relationship between partial and loop inductances and the creation of lumped-element circuit models from two-dimensional partial inductances can be demonstrated with a few simple examples. Consider the two circular wires depicted in Fig. 1. (We chose circular cross-sections in this first example, even though VLSI wires are rectangular, because exact 3-D partial inductance equations are available and all subsequent approximations can be presented.) With radius , center-to-center separation , and length , the three-dimensional partial self ( ) and partial mutual ( ) inductances [25] are

A. Partial and Loop Inductances Partial inductances were defined long before the introduction of microelectronics and integrated circuits. Rosa published several reports for the Bureau of Standards in the early 1900s (one relevant report on linear conductors can be found in [25]), and Grover provided a comprehensive summary of partial inductances in 1946 [15]. Partial inductances were used primarily in power engineering until 1972, when Ruehli introduced them into the world of integrated circuits [26]. An abbreviated derivation of 2-D partial inductances is presented in [22]. Partial inductances are useful when the induced current return paths are unknown. Although partial inductances stencil into circuit graphs like conventional loop inductances, partial inductances have no physical meaning because inductance is

(1)

(2) Note that neither (1) nor (2) is a linear function of the wire length .

KOPCSAY et al.: 2-D INDUCTANCE MODELING APPROACH FOR VLSI INTERCONNECTS

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Fig. 2. Single-segment RLC model of two wires in Fig. 1 when driven at one end by a Thevenin source.

Fig. 4. Single-segment RLC model for a three-wire system driven by two Thevenin sources. The inductances are either 3-D partial inductances or 2-D partial inductances multiplied by the wire length. Furthermore, the three wires form a cutset.

Fig. 3. Single-segment common-ground pi model of the two wires in Fig. 1 when the wire pair is driven at one end by a Thevenin source.

If the two wires in Fig. 1 are driven at one end by a Thevenin source, a single-section frequency-independent RLC model of the circuit would be given by that in Fig. 2. In this schematic, is the Thevenin source resistance, is one-half the wire-to-wire is the wire resistance, and there exists only capacitance, one global ground. Because interconnect analysis is interested only in the local capacitor potentials, and the two wire currents are equal and opposite, we can treat one wire as a reference lead and fold its series impedance into that of the other wire [32]. In Fig. 3, the ground return wire was selected as the reference lead and its series impedance combined with that of the signal wire to create a single-section common-ground transmission-line model. And in the course of this conversion, something else interesting happened. The loop inductance 2 is given by

(3) When [25]

Note that this approximation linearly depends on wire length and is equal to the 2-D loop inductance times the wire length . Furthermore, if the bandwidth of the single pi section model in Fig. 3 is too limited, its bandwidth can be improved by simply dividing it into more segments [32]. The same rule Bakoglu [1] offers for deciding when inductive effects are necessary (5) is the rise time of the signal and is the transmiswhere sion-line time-of-flight delay, can also be applied to model segments for deciding when to further divide these segments. We now extend this to a three-wire system. The partial inductance model composed of two signal wires and one ground return wire can also be transformed into a common-ground model. But in this case, the common ground model contains two wires. These wires are capacitively, inductively, and resistively coupled. The circuit model in Fig. 4 depicts a single-segment RLC model for a three-wire system driven by two Thevenin sources at one end of the wires. Because our ground reference lead elimination will create 2-D loop inductances when the wires are long, the partial inductances in this schematic can be either 3-D partial inductances or 2-D partial inductances that have been muland equal the Thevenin tiplied by the wire length . , , and equal one-half the various source resistances; wire to wire capacitances; and again, there exists only one global ground. Because interconnect analysis only deals with local capacitor potentials and the three wires form a cutset, making the sum of the two signal wire currents and equal and opposite to the ground return current , we can treat the ground wire as a reference lead and fold its series impedance into that of the other two wires. The conversion, which is described in [32] for the general across case, goes as follows: the branch voltages , , and the three wires in Fig. 4 are given by

, this loop inductance can be approximated by

(4)

(6)

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where , , and are the branch currents. Furthermore, because these wires form a cutset, the ground current is equal and opposite to the sum of the two signal wire currents and

(7)

where is the nonsquare matrix defined in [32]. If we denote the node voltages on the left and right sides of the wires as and , the capacitor potentials on the left side of Fig. 4 are given by

(8)

and on the right side by

(9)

Now consider the common ground model in Fig. 5. The and across the “remaining” two wires branch voltages in Fig. 5 are given by the difference in the left- and right-side capacitor potentials from Fig. 4. That is (10) By using the previous equations, we can manipulate (10) to define effective inductance and resistance matrices that relate the and to the branch currents and . For branch voltages the three wires in Fig. 4, this manipulation yields (11), shown at the bottom of the page and

Fig. 5. Single-segment common ground RLC model for a three-wire system driven by two Thevenin sources.

Note that the two voltage sources given by and in Fig. 5 represent the mutual ground resistance shared by the two wires. That is, switching activity in either line will produce a common-mode voltage drop in the other line independent of the inductive coupling. The conversion of 2-D partial inductances and series resistances to loop impedances can be extended to handle multiple signal and return wires. Frequency-dependent behavior can be captured by subsectioning these conductors [29]. The extended procedure starts by combining any parallel wires and multiple wire cross-sections into single series elements. ground wires Consider the signal wires and parallel depicted in Fig. 6(a). The signal and ground wires are indicated with the subscripts and , respectively. For a given parallel ground wires frequency , the signal wires and 1 complex impedance matrix can be converted into an . Consider the circuit in Fig. 6(b). The branch can be related to the 1 voltage sources voltages by (13) where is the incidence matrix. When (13) is combined with , we the constitutive branch equations obtain

(12)

(14)

(11)


(a)

n

m

signal wires and parallel ground wires

n

Fig. 6. Conversion of signal wires and series impedance model.

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common power rail be justified in light of these apparent 3-D complexities? The following paragraphs will discuss the approximations inherent in 2-D inductance modeling. We will show that orthogonal wiring can be ignored, power and ground rails can be commoned, the power distribution currents close to the interconnect are equal and opposite to that of the interconnect, the voltage drop along the power distribution is both small and equal in both the power and ground rails, and longitudinal inductive coupling can be ignored. As a part of this discussion, a complex VLSI interconnect model is studied to demonstrate some of the necessary conditions for 2-D inductance modeling. (b) circuit to convert into wires

n+1

A. Why Orthogonal Wiring Can Be Ignored

m parallel ground wires into an n+1

By using Kirchoff current law, , the branch currents in (14) can be combined to find the voltage source currents (15) that Finally, we can define a complex impedance matrix relates the paralleled branch voltages to the sum of the paralleled branch currents (16) can be characterThe frequency-dependent behavior of ized by evaluating (16) at several discrete frequencies over the frequency range of interest. Equation (16) can also be evaluated at a single frequency and the results applied using (11) and (12) to produce a commonground circuit like that shown in Fig. 5 for three wires. This procedure, however, yields a single frequency model and not one suitable for time-domain analysis. Producing a lumped-element circuit model suitable for time-domain analysis, that is, one that captures the frequency-dependent behavior of multiple signal wires, is problematic. Although Wheeler’s seminal work on skin effect in 1942 [30] led to a host of lumped-element circuit model approximations for single wires [18], [21], [31], a general-purpose synthesis technique for coupled wires was not previously available. IV. THE VALIDITY OF 2-D INDUCTANCE MODELING The use of a 2-D inductance model implies that a whole host of approximations have been made concerning return currents, eddy currents, power distribution voltage drops, and power-to-ground impedance. While the focus of this paper is to efficiently incorporate the effects of distant returns in 2-D inductance models and then synthesize compact circuit models suitable for time-domain analysis, some discussion is needed concerning the validity of the 2-D approximations. VLSI chips have complex meshes of orthogonal power and ground wires, and circuits pull their switching currents out of a single power rail at a time. How can the 2-D modeling approach with a

Orthogonal wiring can modify the inductive properties of long interconnect wires, but the change is a second-order effect. When an interconnect wire perpendicularly crosses a wide power bus, its self and mutual inductances are lowered due to eddy currents in the orthogonal power bus. This lowering, however, is only measurable over the wide orthogonal power buses, and wide power buses are rapidly disappearing in VLSI designs. Today’s metal density rules to prevent metal thinning during chemical-mechanical planarization encourage the use of narrower but more frequent power-distribution rails to both maximize dc power distribution conductivity and suppress ac common-mode noise. B. Why the Power and Ground Rails Can Be Commoned While one can build a 2-D-based model that includes both the power and ground rails, most 2-D models common these rails. Given that a VLSI CMOS chip already looks like a big capacitor between power and ground [27], and most designs since [10] deliberately add decoupling capacitors, this seems like a reasonable approximation. The example in Section IV-C will examine this approximation and show that it is indeed a reasonable approximation. C. Equal and Opposite Return Currents in the Power Distribution Because the existence of equal and opposite return currents in the nearby power distribution rails is such a critical, and highly questioned, 2-D modeling approximation, we built a large 3-D example to demonstrate this behavior. Depicted in Fig. 7(a)–(c), our example has three long interconnect wires embedded in a large two-metal-layer VLSI power distribution mesh. The three interconnect wires are placed in the center of the power grid between the centermost power and ground rails. The interconnect wires are 2.0 m wide, and wire-to-wire spacing is 2.5 m. The orthogonal power/power (and ground/ground) rails are resistively connected and the orthogonal power/ground rails connected via an RC circuit to model the inherent and added power-ground decoupling capacitance. The physical details of the model are depicted in Fig. 7. When studying return current behavior, we examined the power distribution currents that run parallel to the interconnect lines along cross-sections perpendicular to these lines. Because every perpendicular cross-section of power distribution wires,

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(a) overall dimensions

Fig. 8. Near- and far-end behavior of lines 1, 2, and 3 in Fig. 7 and near-end power-supply disturbance for common-mode switching pattern. (b) Cross-section of three lines and adjacent power/ground wires

(c) Added coupling capacitors and power supply connections Fig. 7.

3-D example used to demonstrate 2-D model behavior.

when taken over the entire model, forms a cutset with the three interconnect lines, a sum of these power distribution currents will always be equal and opposite to a sum of the interconnect currents. The issue at hand, however, is just how close the power distribution return currents follow the interconnect wires. Because the large number of inductors would make a full 3-D RC partial inductance modeling intractable, we built sparse models using the window-based extraction technique in [3]. Our densest model had 15 880 self and 371 071 coupling terms, term. Our or approximately 46 coupling terms per self sparsest model, an RC model, neglected inductance entirely. We RC model with 62 897 coupling terms. Along had a second the interconnect line, we added wire-to-wire, wire-to-power, and wire-to-ground capacitances. Between power-to-power and ground-to-ground crossings, we added a resistor to represent the parallel via resistance. Between power-to-ground crossings, we added an RC circuit to represent the typical impedance seen between power and ground, which takes into account added decoupling capacitors, quiet circuit capacitance, device well capacitances, and of course the less significant power-wiring to ground-wiring capacitance. Finally, we modeled our switching circuits with Norton sources. RC models using the speWe simulated the sparse cial-purpose simulator described in [33]. Because the nodal-analysis equations are symmetric and the RC model is provably symmetric positive definite, this simulator employs a powerful Cholesky-based sparse matrix solver [12] to model large circuits. We studied the current flow and the voltage drops along the power and ground meshes for a number of different switching patterns. The following paragraphs describe the results of our common-mode analysis.

Fig. 9. Interconnect and return currents in the nearest six parallel-power distribution wires at 100 and 1500 m away from source for L RC model with 371 071 coupling terms.

In our analysis, all three interconnect wires were driven using 50- Norton sources with 5-ps rise times. (We used Norton sources to keep the circuit equations symmetric positive definite.) Fig. 8 shows, for our densest model, the near-end and far-end response and the near-end power-supply disturbance for a 1-V supply. Figs. 9–11 qualitatively address the issue of how close the reRC turn currents follow the interconnect lines in RC and models. In Figs. 9 and 10, the sum of three interconnect currents is compared to a sum of the return currents in the nearest six parallel-power distribution wires at 100 and 1500 m away RC models. In these figfrom the driver source for the two ures, the signal and return currents are defined to be oppositely directed to facilitate the comparison. Because the nearest six power distribution wires include the three closest returns on either side of the interconnect wires, the outside power wires were 50 m away from the middle interconnect wire. RC model with 371 071 In Fig. 9, which represents the coupling terms, the nearest six power distribution wires carry 88% and 83% of the peak return current at 100 and 1500 m RC model is made more sparse by down the line. When the


Fig. 10. Interconnect and return currents in the nearest six parallel-power distribution wires at 100 and 1500 m away from source for L RC model with 62 897 coupling terms.

discarding the smallest coupling terms, the power distribution RC return currents spread out. Fig. 10 shows, for the second model with 62 897 coupling terms, that the nearest six power distribution wires carry less peak return current: 73% and 65% at 100 and 1500 m, respectively. Moreover, when inductance is discarded entirely, producing an RC model, the return currents spread out almost uniformly across the power grid. This spreading-out behavior is depicted in Fig. 11, where the RC models power distribution return currents for the two and the RC model are plotted as functions of their position along the power grid perpendicular to the interconnect lines. Note that these current distributions were plotted as continuous curves only to make Fig. 11 more readable. Because the power grid was composed of discrete wires, a bar-graph representation would be technically more accurate. These current-versus-power grid position snapshots were taken 5 and 20 ps into the simulation and at the respective positions of 100 and 1500 m away from the driver circuits. Clearly, as inductive couplings are discarded, the power-distribution RC analyses return currents spread out. Also note in the that the power-rail current immediately to the left of the interconnect lines is only slightly greater than the ground-rail current immediately to the right of the wires. Although the interconnect lines are switching from low to high, meaning that the three drivers pull their switching currents out of the power rail, the return currents are carried almost equally on both rails—even 100 m down from the driver circuits. The RC model shows a significantly different behavior at 100 m from the source. Here the closest power-rail current is almost 10 the closest ground-rail current—which is visible from the sharp oscillations in its current distribution. These oscillations reflect large differences in the power- and ground-rail currents. The reader should note that an ideally decoupled power grid with capacitors at each power-to-ground overlap would have given rise to a smooth current distribution even for the RC model. RC model The return current distribution of our densest also starts to resemble that of a perfectly conducting circular wire above a perfect ground plane. Consider the conformal mappings depicted in Fig. 12. The rectangle between the

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(a) Return Current Distribution at 100 microns

(b) Return Current Distribution at 1500 microns Fig. 11. Power distribution current versus power grid location for L RC model with 371 071 coupling terms, L RC model with 62 897 coupling terms, and RC model.

coplanar ground planes in Fig. 12(a) maps to the polygon above the ground plane in Fig. 12(c). By applying these same transformations to our cross-section, we are led to compare RC models to that of the return current distribution of our a conductor above a perfect ground plane. The ground-plane current distribution for a perfectly conducting circular wire of radius with current at a distance above a perfect ground plane is [16] (17) Fig. 13 compares the return current distribution of our RC models at 20 ps and 1500 m away from the drivers to that of a 2.0- m-diameter wire 8.0 m over an ideal ground plane conducting 6.9 mA (6.9 mA is the sum of the three interconnect currents at this time and place). To compare (17) to discrete distributions, (17) is multiplied by the power-disRC model tribution pitch of 20 m. Because the denser distribution looks closer to that of the ideal ground plane, we conclude that a regular, continuous ground mesh behaves approximately like an ideal coplanar ground plane.

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(a) Potential Drops at 100 microns

Fig. 12. Conformal mappings of a rectangle between coplanar grounds to a polygon above a ground plane.

(b) Potential Drops at 1500 microns Fig. 14. Potential drops across 20-m sections of the three interconnect lines and the six nearest parallel power-distribution wires on one side of the interconnect lines.

E. Why Longitudinal Inductive Coupling Can Be Ignored

Fig. 13. Power-distribution current versus power-grid location for L RC model with 371 071 coupling terms and 2.0-m-diameter wire 8.0 m over a perfect ground plane.

A further advantage of 2-D modeling is that it eliminates the unnecessary coupling in the direction of propagation. A full dense 3-D model containing wires segmented times along nm mutual terms. Consider the their length has (1/2) nm filaments from a 3-D model section depicted in Fig. 15. The 3-D partial inductance between these filaments is [15]

D. Equal Drops in the Power Distribution Perpendicular to Interconnect By combining the parallel ground wires in Fig. 6, the potential drops across the nearby power-distribution branches are assumed to be equal. (This also implies that the power-distribution current flow perpendicular to the interconnect lines is zero.) Fig. 14 depicts the potential drop measured across 20- m sections of the interconnect lines and the six nearest power distribution wires on one side of the interconnect lines. The potential drops are measured at 100 and 1500 m down from the driver circuits. These curves show that the potential drops along the parallel power-distribution wires are approximately equal and, furthermore, small relative to the drops along the interconnect lines. Again, this suggests that the gridded mesh behaves like a ground plane.

(18) where

(19)


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Now consider the three parallel filaments L1, L2, and L3 depicted in Fig. 16. The length of each filament is 20 times the separation between filaments L1 and L2. The partial inand are approximately equal regardless ductances of the absolute dimensions of L1, L2, L3, and . That is, if

(20) The equal and opposite currents in conductors 1 and 2 will resemble a dipole and have canceling inductive effects on conductor 3. The 2-D model is much more efficient because it only contains couplings in the transverse direction. The longitudinal couplings contained in 3-D models are only necessary in modeling end effects. V. 2-D INDUCTANCE EXTRACTION WITH COPLANAR GROUND RETURNS The 2-D extraction approach culminating in (11), (12), and (16) is inherently inaccurate at lower frequencies because finite extraction regions are considered. The dc return path resistance is proportional to the width of the region modeled. For in (16) has a nonzero dc example, the impedance matrix resistance in the common return path. While the extraction region can always be made wider to reduce these inaccuracies, wider regions slow the extraction process; more shapes have to be processed, larger matrices have to be computed and inverted, and fewer cross-sections match those that have been previously computed. One way to avoid wide cross-sections yet capture far-field effects is to approximate the far-field return wires as a coplanar ground plane using the conformal transformations in Fig. 12. (It should noted that some designers, in order to model common-mode noise, may actually choose to limit their extraction regions.) In the following paragraphs, we show how a 2-D inductance problem with coplanar ground planes can be transformed to a problem with only wires (i.e., no ideal ground planes). We note, however, that rectangular wires with uniform resistivity in the original problem become nonrectangular wires with nonuniform resistivity in the mapped problem. We then show that the resultant circuit is no more complicated than the same problem without the coplanar grounds (other than the above-mentioned transform anomalies). We then follow with an example that demonstrates both the validity and improved accuracy of the coplanar ground-plane approach. For a given 2-D cross-section with coplanar grounds, we perform the transformations of Fig. 12. (In the later example, we

.. .

.. .

.. .

Fig. 15. Mutual inductance between parallel filaments of unequal length given by (18).

Fig. 16.

Mutual inductance between parallel filaments of equal length.

discuss the positioning of these ground planes for best accuracy.) The box in Fig. 12(a) represents the signal and return wires that we wish to consider as discrete. Any individual wire in this box can be subdivided into multiple cross-sections to capture frequency-dependent behavior. The box in Fig. 12(c) represents those same wires over a conducting plane. Using the method of images [16], these wires and the perfectly conducting ground plane can be represented with two sets of wires (and no ground plane), where the potentials and currents on matching wires are opposite in polarity. The impedance equation for this system is given by (21) at the bottom of the page, which, because the potentials and currents are opposite in polarity, reduces to two sets of redundant equations, the first set being .. .

.. .

.. .

.. . (22)

or (23) where represents the mutual inductance couplings between real wires and image wires. The constraints on this reduced system, however, are not that the currents sum to zero but that the potential across the return elements is zero. This can be seen by taking the case of two signal wires and two returns, represented with the circuit in Fig. 17, where we have applied sources to one end and shorted the other. We note that, due to symmetry, the potential from a to b is zero. We can therefore attach a wire from a to b without affecting the operation of the circuit. We

.. .

.. .

.. . (21)

.. .

.. .

.. .

.. .

.. .

.. .

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Fig. 17. Circuit representation of two signal wires and two ground wires and their images.

Fig. 18. Circuit representation of two signal wires and two ground wires and their images electrically connected by their mutual couplings only.

can then split the problem into two disconnected problems, electrically connected only with mutual couplings, as shown in the new circuit in Fig. 18. This is consistent with applying the constraints that the potential across the ground path is zero are not constrained to sum to zero. while the currents We can apply this constraint to the more general problem described by (23). We invert (23) to obtain (24) We define the transpose of the incidence matrix .. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

.. .

as

Fig. 19.

2-D modeling example for studying coplanar ground approximation.

The equation relating the branch voltages to the total signal currents is then (26)

(25)

where each column represents a signal conductor and each row a cross-section. The columns of ones group the cross-sections of individual signal wires, and the block of zeroes at the bottom applies to the ground-wire cross-sections and implements the constraint that the potential drop across the ground mesh is zero.

While (16) and (26) look similar, they are in fact different. The explicit ground in (16) must be folded away using (11) and (12). On the other hand, (26) is already folded due to the zero potential across the ground wires, and in fact the order of (26) is one less than that of (16). We now consider the example in Fig. 19. Here two coupled are embedded in a ground mesh with wires on metal level power distribution wires running parallel to the signal wires on and . (Level is an orthogonal wiring levels level and can be ignored if the power and ground wires are narrow.) The mesh depicted in Fig. 19 repeats every 20.0 m. This problem was modeled three ways: first, the problem considering the signals with only close returns 30 m on either side; second, the problem considering the signals with returns 250 m on either side; and third, the problem considering the signals with the closer return only but with a coplanar ground plane to account for the other returns. We chose this plane to start at


Fig. 20.

Self and mutual impedances Z

and Z

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for the example in Fig. 19.

the closest edge of the first ignored ground return wire at the top wiring level. We see in Fig. 20 that the first and second cases differ sigfor frequencies as nificantly in the coupling impedance high as 2 GHz, indicating the error obtained by ignoring the farther out grounds. We see, however, that the third case matches the second quite well at these higher frequencies, indicating that the coplanar approach sufficiently accounts for the farther out grounds. VI. FINITE POLE APPROXIMATIONS FOR TRANSMISSION-LINE SERIES IMPEDANCE Sections II–V of this paper discussed the validity of 2-D inductance models for interconnections on a VLSI chip and an extraction algorithm. In improvement to the existing 2-D this section, we will describe how these 2-D impedance representations are used to create an approximate frequency-dependent lossy transmission-line model for analysis of on-chip interconnect performance. As is well known, a transmission-line model can be defined in terms of its series impedance per unit length (27) and its shunt admittance per unit length (28)

When dealing with coupled lines, these per unit length impedances and admittances become matrix quantities with elements that represent the self (diagonal) and mutual (off-diagonal) contributions. Interconnections on a VLSI chip are highly resistive. Thus it is an excellent approximation to neglect dielectric loss and represent the admittance as a frequency-independent capacitance matrix. However, the frequency dependence of the impedance per unit length matrix must be modeled accurately to obtain reliable delay, rise time, and coupling estimates. Since many conventional transmission-line models exhibit convergence and accuracy problems with highly resistive lines, we have chosen to use simple RLC segmented line representations. Due to the relatively short lengths required for on-chip interconnects, only a few subsections are typically required for accurate results. Since high-frequency components of the signal excitation are strongly attenuated on these resistive lines, there is no problem with reflections and ringing, as can occur in low-loss RLC models. These simple models may be rapidly solved using special simulators [24] or a general-purpose circuit simulation program such as Spice. The interconnect model problem has thus been reduced to and finding frequency-dependent representations for the in the impedance per length matrix, which presumably use relatively few physical circuit elements. To accomplish this, as a we approximate each element of the impedance matrix ratio of polynomials in frequency. Thus, given a set of known (precalculated by the techniques discussed in Sections II–V of

706


this paper) complex impedances at frequencies to find an approximate representation

, we wish

(29)

) with a finite number of poles. This approximate (where representation is, of course, only accurate over a limited range of frequency. The intended application for this fitting procedure is to represent the frequency-dependent series impedance of a transmission line derived from (11), (12), and (16). The resulting approximate impedance function can then be used to create a segmented model of a lossy, frequency-dependent transmission line. Since the series impedance per unit length of a transmission line is of the form

(30) and high-frequency we can subtract out the dc resistance before finding an approximation. That is, we inductance just have to represent the frequency-dependent part .

Fig. 21. Foster RL network representation of frequency-dependent impedance.

of stability and passivity to eliminate nonphysical poles from the representation. A modification of this approach is to choose a form for the rational polynomial representation that is suitable for the particular problem of interest. Specifically, the frequency-dependent part of a transmission-line series impedance can be represented as a series connection of parallel RL elements (Foster form), as shown in Fig. 21. This particular choice for the topology of the network is not unique since other forms are equally valid. For example, a ladder network (Cauer form) can easily be derived from the resulting impedance function by a continued fraction expansion. However, the Foster form is convenient since contributions of the various elements to the frequency-dependent impedance are easily visualized. The impedance of the chosen network representation is then given by

(33) A. Rational Polynomial Representation The general fitting problem is a form of model order reduction [11]. The usual procedure is to form a set of equations defined by substituting the known impedances as follows:

(31)

and to solve for the unknown coefficients of the numerator and denominator polynomials. Due to the presence of unknowns in the denominator, these equations are nonlinear. In general, a fit can be obtained by using a constrained nonlinear optimization technique. However, these procedures can be complicated to set up and costly in computer resources. Another well-known solution technique is called the frequency-domain Prony method [5], which is also a subset of the Cauchy technique [19] for interpolating given functional values by rational polynomials (the general Cauchy interpolation technique also allows values given for derivatives to be used in determining the fit). The first step is to multiply through by the denominator to give the following set of linear (in the coefficients) equations (32) These equations are then solved using a matrix linear equation solver or a least squares technique. However, such a solution is often divergent, particularly since these equations become illconditioned as the order of the approximation is increased. Even when the solution converges, it is necessary to apply conditions

. Now the problem is reduced to choosing where and residues that provide a good fit to a set of poles the given impedances. B. RL (Foster Form) Series Impedance Solution Several approaches have been employed to find a set of poles and residues that provide a good fit to the series impedance of various transmission lines. These include nonlinear optimization and prespecification of pole frequencies distributed across the frequency range of interest, followed by linear least squares fitting to determine the coefficients . An alternative approach based on the frequency-domain Prony or Cauchy procedure outlined above is as follows. The impedance function for the Foster RL network shown in Fig. 21 can be rewritten by combining terms over a common denominator

(34)

and are unknown coefficients (replacing and where ). Again multiply through by the denominator to obtain the following linear relation between the coefficients:

(35)


Then substitute the known impedances at the given frequency to form a set of linear equations points

707

Writing this set of equations in matrix form gives

.. .

.. .

.. .

.. .

(36) .. . Rearranging so that the unknown coefficients are all on the left side of the equations gives

(37)

.. .

.. .

.. .

.. .

.. . (41)

Separating into real and imaginary parts results in a set of equations that can be written in matrix form (shown for the example ) as follows: of

(38) Deriving the corresponding set of matrix equations for other values of is straightforward. Note that the number of frequency points must at least equal the number of unknown coefficients, but it is desirable to specify additional points and solve the resulting overdetermined system of linear equations by a least squares algorithm. Also note that the rows of the matrix that were derived from the imaginary part of the original equation contain a common factor . This term could be cancelled by simply dividing these equations by . However, this cancellation would result in a change of weighting to favor a fit minimizing the residual in inductance rather than inductive reactance. The form shown above that gives a best fit to inductive reactance has been found to provide a better overall result, particularly for a small number of poles. Once the above set of equations has been solved for the coefficients and , the poles can be found by determining the roots of the denominator polynomial

(39) can then be found by partial fraction expanThe unknown sion. However, a somewhat better fit can often be obtained by using the pole frequencies determined above in an additional linear and as follows: least squares fit to the given

(40)

.. .

Note that the above set of matrix equations uses both the given resistance and inductance information to determine the best fit. Since the networks are causal, it is only necessary to fit one or the other, assuming that the fit is accurate over a broad enough frequency range. In practice, it is often found that the first half of the above set of equations for fitting the resistance is sufficient to also obtain a reasonable fit to the inductance. However, in general, the full set of equations as given above provides a better overall fit. Also note that although a common factor could again be cancelled from the imaginary parts in this set of equations (lower half of the matrix), in practice it has been found that the above weighting produces a better fit for a small number of poles. The procedure outlined above has the advantage that the fit is determined only by real poles. Assuming that these poles are in the left half of the complex plane (i.e., the are positive), then the resulting network is guaranteed to be stable. However, it is not necessarily passive since the solution in general can result in nonphysical, negative element values. Any right-half plane poles in the solution (possibly due to noise in the measured or calculated input data) are easily identified, and can usually be eliminated without significantly degrading the accuracy of the fit. In practice, the impedances for most passive structures can be fit using only positive elements. However, in some cases, negative elements are needed even though the complete network representation is passive. One approach for eliminating these negative circuit elements is discussed in Section VI-C. The Foster network described above has a particularly simple form that is useful for implementing a discretized equivalent circuit model of the transmission line in a standard circuit solver. Of course, the solution can fail if the chosen network topology is not appropriate for the given data. One example where the Foster RL network must be modified is discussed in Section VI-C. In such cases, a network form with more suitable impedance variation should be chosen; an impedance transform that often results in a useful network topology is described below. Otherwise, a

708

Fig. 22.


Single-pole Foster RL circuit with negative elements.

general model order reduction technique using an arbitrary rational function can be applied to obtain the fit. It should also be noted that, as with other model order reduction techniques, the solution described here can fail due to instability of the linear equations that define the coefficients of the numerator and denominator polynomials, especially as the order of approximation is increased. In practice, this has not been a problem for a variety of lossy transmission-line impedance ele. ment fits, which typically use

Single Foster RC pole in series with negative resistance.

Fig. 24.

Transformed equivalent circuit representation with positive elements.

By comparison with and then rewrite (46) as

C. Avoiding Nonphysical Elements in RL Impedance Representations A problem can occur in applying the procedure outlined in Section VI-B when the chosen network topology is unable to fit the data using physically realizable elements. For example, the Foster RL network representation described in Section VI-B cannot accurately fit a resistance that is not monotonically increasing with frequency without using nonphysical, negative circuit element values, even though the network is passive. To address this problem, a simple impedance transformation is described here that, in many cases, allows a pole associated with negative elements to be converted from an RL to an RC pair and to be realized using positive circuit elements. When this transformation is applicable, it is simpler than using a more general network form (or an arbitrary rational fitting function), where the conditions of stability and passivity must be enforced as constraints on the solution. Consider the single parallel RL circuit shown in Fig. 22, ). Note that where the resistor value is negative (i.e., a stable network has poles only in the left half of the complex plane. This implies that the inductance must also be negative. The series impedance of the single pole circuit in Fig. 22 is given by (42) is positive. where Also consider the impedance of a single parallel RC network, which is given by (43) where

Fig. 23.

. Now we find (44) (45) (46)

in (43), we can identify

(47) Therefore, we can replace the original RL circuit from Fig. 22, which has unrealizable elements, by a series combination of a realizable single-pole Foster RC circuit and a negative resistance, as shown in Fig. 23. Though it seems that the network impedance represented by (47) is still unrealizable (due to the negative resistance), this network is only intended to fit the frequency-dependent part of and the series impedance and must be placed in series with to achieve the final representation. If the magnitude of the , then summing their values negative resistance is less than will leave a positive element value. Physical insight into this transformation can be obtained by comparing the dc and high-frequency limits of the impedance , the real part of the functions in (42) and (43). For in (42) approaches zero since it is effectively impedance , the real part of shorted out by the inductance. For approaches . For , the real part of the impedance in (43) approaches since the capacitor is an open circuit at , the real part of approaches zero since it is dc. For shorted out by the capacitor at high frequency. Thus both impedances exhibit real parts that decrease with frequency in a similar in (44), we have represented part of manner. By adding to the dc resistance in this frequency-dependent circuit. The resulting equivalent circuit is shown in Fig. 24 for the case of a three-pole representation where one pole has negative elements in the original fit. The above transformation has been found useful in eliminating negative element values in many cases where, otherwise, they would have been required to represent the given data. However, for general frequency-dependent data, it is possible that negative element values may be required after this transformation is applied. In such cases, other techniques must be used. It should also be mentioned that the circuit topologies discussed in Section VI for fitting a variety of frequency-dependent impedances with realizable elements are equally applicable with alternate solution methods to determine the element values.


709

TABLE I FREQUENCY-DEPENDENT R AND L FOR STRUCTURE IN FIG. 25

TABLE II THREE-POLE RL FIT TO DATA IN TABLE I

Fig. 26. Table I. Fig. 25.

Modified three-pole circuit (per cm) representation of

Z

data in

Cross-section of coupled lines.

For example, these topologies can also be used with constrained nonlinear optimization to generate realizable equivalent circuit models. D. Coupled Line Example In this example, we generate a fit to the series impedance of a frequency-dependent transmission line consisting of a pair of signal lines separated by a wide return conductor. This example illustrates the use of the impedance transformation in Section VI-C to avoid nonphysical RL elements. The conductor dimensions are similar to those used for on-chip wiring. A crosssection of the structure is shown in Fig. 25. Although lightly coupled, these lines illustrate the type of structure that can require nonphysical elements in an unmodified RL fit. At low frequency, the current flow is determined by the dc resistance; the lines shown in Fig. 25 have the unusual behavior that the inductance for symmetric excitation (even mode) is less than that for antisymmetric excitation (odd mode), resulting in a negative mutual. As the frequency is increased, the

current distribution is concentrated near the edges of the return conductor, and the mutual inductance becomes positive as the usual modal behavior is restored. The element values of the symmetric frequency-dependent and matrices shown in Table I were calculated via the partial element equivalent circuit (PEEC) procedure in [29]. In addition, the high-frequency inductances were calculated as and nH/cm, and the dc resistances and cm. The frequency depenas dence described above can be seen in the sign change of mutual inductance between low and high frequency. A fit generated from these data using the basic procedure described in Section VI-B is shown in Table II. The self-element fit is accurate and realizable using two poles. An accurate mutual element fit requires three poles. However, since this representation contains negative element values, we apply the transformation described in Section VI-C. The resulting equivalent and fits circuit for the mutuals is shown in Fig. 26. The are plotted along with the original data in Figs. 27 and 28. The three-pole fit is excellent, and all element values in Fig. 26 are positive.

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Fig. 27.

Comparison of L

data versus fit for circuit of Fig. 26.

Fig. 28.

Comparison of R

data versus fit for circuit of Fig. 26.

This simple impedance transformation has been found effective for a wide range of CMOS on-chip wiring geometries where negative elements were obtained in an RL fit. In fact, using this transformation, we have been successful in generating realizable circuit models for the large majority of cases where negative elements were encountered. VII. CONCLUSION This paper has reviewed 2-D partial inductance modeling for VLSI interconnect analysis and has shown through a complex 3-D example that the simpler 2-D modeling approach is indeed valid for long interconnect wires. Furthermore, this paper has extended the 2-D frequency-dependent impedance extraction algorithm to efficiently incorporate far-field effects using a coplanar ground approximation. Finally, this paper has described a novel synthesis technique that approximates frequency-dependent transmission-line series impedance with compact circuit models suitable for timing or noise analysis. REFERENCES [1] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990. [2] M. Beattie, B. Krauter, L. Alatan, and L. Pileggi, “Equipotential shells for efficient partial inductance extraction,” IEEE Trans. Computer-Aided Design, vol. 20, no. 1, pp. 70–79, Jan. 2001.

[3] M. Beattie and L. Pileggi, “Efficient inductance extraction via windowing,” in Proc. 1st Design Automation and Test in Europe Conf., Mar. 2001. , “Inductance 101: Modeling and extraction,” in Proc. 38th Design [4] Automation Conf., June 2001. [5] J. N. Brittingham, E. K. Miller, and J. L. Willows, “Pole extraction from real-frequency information,” Proc. IEEE, vol. 68, no. 2, pp. 263–273, Feb. 1980. [6] R. E. Collin, Field Theory of Guided Waves. New York: McGraw-Hill, 1960. [7] A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C. Edelstein, and P. J. Restle, “On-chip wiring design challenges for gigahertz operation,” Proc. IEEE, vol. 89, no. 4, pp. 529–555, Apr. 2001. [8] A. Deutsch, H. H. Smith, and G. V. Kopcsay et al., “Multi-Line crosstalk and common-mode noise analysis,” in Proc. Dig. IEEE 9th Topical Meeting on Electrical Performance of Electrical Packaging, Scottsdale, AZ, Oct 23–25, 2000, pp. 317–320. [9] A. Devgan, H. Ji, and W. Dai, “How to efficiently capture on-chip inductance effects: Introducing a new circuit element K,” in Proc. IEEE Int. Conf. Computer Aided Design, Nov. 2000, pp. 150–155. [10] D. W. Dobberpuhl et al., “A 200-MHz 64-b dual-issue CMOS microprocessor,” IEEE J. Solid-State Circuits, vol. 27, pp. 1555–1567, Nov. 1992. [11] M. Elzinga, K. L. Virga, and J. L. Prince, “Improved global rational approximation macromodeling algorithm for networks characterized by frequency sampled data,” IEEE Trans. Microwave Theory Tech., vol. 48, no. 9, pp. 1461–1468, Sept. 2000. [12] A. Gupta, “WSMP: Watson sparse matrix package,” IBM T. J. Watson Research Center, NY, Tech. Rep. RC 21888 (98472), 2000. [13] K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao, “Inductance 101: Analysis and design issues,” in Proc. 38th Design Automation Conf., June 2001. [14] K. Gala, V. Zolotov, R. Panda, B. Young, J. Wang, and D. Blaauw, “On-chip inductance modeling and analysis,” in Proc. 38th Design Automation Conf., June 2001. [15] F. W. Grover, Inductance Calculations. New York: Dover, 1946. [16] H. A. Haus and J. R. Melcher, Electromagnetic Fields and Energy. Englewood Cliffs, NJ: Prentice-Hall, 1989. [17] O. Heaviside, Electrical Papers London, U.K., 1892, vol. 2. [18] S. Kim and D. P. Neikirk, “Compact equivalent circuit model for the skin effect,” in IEEE MTT-S Int. Microwave Symp. Dig., San Francisco, CA, June 17–21, 1996, pp. 1815–1818. [19] K. Kottapalli, T. K. Sarkar, Y. Hua, E. Miller, and G. J. Burke, “Accurate computation of wide-band response of electromagnetic systems utilizing narrow-band information,” IEEE Trans. Microwave Theory Tech., vol. 39, pp. 682–687, Apr. 1991. [20] B. Krauter and L. Pileggi, “Generating sparse partial inductance matrices with guaranteed stability,” in Proc. IEEE Int. Conf. Computer Aided Design, Nov. 1995, pp. 45–52. [21] B. Krauter and S. Mehrotra, “Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis,” in Proc. 35th Design Automation Conf., June 1998. [22] B. Krauter, S. Mehrotra, and V. Chandramouli, “Including inductive effects in interconnect timing analysis,” in Proc. Custom Integrated Circuits Conf., May 1999. [23] C. R. Paul, Introduction to Electromagnetic Compatibility. New York: Wiley, 1992. [24] C. L. Ratzlaff and L. T. Pillage, “RICE: Rapid interconnect circuit evaluation using AWE,” IEEE Trans. Computer-Aided Design, vol. 13, pp. 763–776, June 1994. [25] E. B. Rosa, “The self and mutual inductance of linear conductors,” Bull. Nat. Bur. Standards, vol. 4, no. 2, pp. 301–344, 1908. [26] A. E. Ruehli, “Inductance calculations in a complex integrated circuit environment,” IBM J. Res. Develop., vol. 16, no. 5, pp. 470–481, Sept. 1972. [27] R. Sechler and B. L. Krauter, “Resonant noise in VLSI CMOS,” IBM, Tech. Rep. 51.0481, 1988. [28] H. Smith, A. Deutsch, and S. Mehrotra et al., “Frequency dependent RLC crosstalk evaluation of a high performance S/390 microprocessor chip,” in Proc. Dig. IEEE 9th Topical Meeting Electrical Performance of Electrical Packaging, Scottsdale, AZ, Oct 23–25, 2000, pp. 317–320. [29] W. T. Weeks, L. L. Wu, M. F. McAllister, and A. Singh, “Resistive and inductive skin effect in rectangular conductors,” IBM J. Res. Develop., vol. 30, no. 6, pp. 652–660, Nov. 1979. [30] H. A. Wheeler, “Formulas for the skin-effect,” Proc. IRE, vol. 30, pp. 412–424, Sept. 1942.


[31] C.-S. Yen, Z. Fazarinc, and R. L. Wheeler, “Time-domain skin-effect model for transient analysis of lossy transmission lines,” Proc. IEEE, vol. 70, pp. 750–757, July 1982. [32] B. Young, Digital Signal Integrity: Modeling and Simulation With Interconnects and Packages. Upper Saddle River, NJ: Prentice-Hall PTR, 2001. [33] H. Zheng, M. Beattie, B. Krauter, and L. Pileggi, “Window-based susceptance models for large-scale RLC circuit analyses,” in Proc. 2nd Design Automation and Test in Europe Conf., Mar. 2002.

Gerard V. Kopscay (S’68–M’69) received the B.E. degree from Manhattan College, Bronx, NY, in 1969 and the M.S. degree from the Polytechnic Institute of Brooklyn, Brooklyn, NY, in 1974, both in electrical engineering. From 1969 to 1978, he was with the AIL Division of Eaton Corp., where he worked on the development of low-noise microwave receivers. In 1978, he joined the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he is currently a Research Staff Member. Since joining IBM, he has worked on the design and analysis of computer packages. His current research interests include the design, measurement, and simulation of interconnects, high-performance computer design, and applications of short-pulse phenomena. Mr. Kopscay is a member of the American Physical Society.

Byron Krauter (M’97) received the B.S. degree in physics and mathematics and the M.S. degree in electrical engineering from the University of Nebraska, Lincoln, in 1976 and 1978, respectively, and the Ph.D. degree in electrical engineering from the University of Texas, Austin, in 1995. Since 1979, he has been with IBM and is presently working in a VLSI CAD tools development group in Austin, TX. His research interests include sparse boundary element method (BEM) techniques for inductance and capacitance extraction and on-chip interconnect analysis.

David Widiger (S’73–M’74) received the B.S. degree in physics and the M.S. degree in electrical engineering from Louisiana State University, Baton Rouge, in 1972 and 1974, respectively, and the Ph.D. degree in electrical engineering from the University of Illinois, Champaign-Urbana, in 1984. He has been with IBM since 1974 and is presently working in a VLSI CAD tools development group in Austin TX. His research interests include extraction and analysis of on-chip interconnects.

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Alina Deutsch (M’83–SM’92–F’99) received the B.S. degree from Columbia University, New York, NY, in 1971 and the M.S. degree from Syracuse University, Syracuse, NY, in 1976, both in electrical engineering. She has been with IBM since 1971 and has worked in several areas, including testing of semiconductor and magnetic bubble memory devices. She has designed unique lossy transmission-line configurations and developed unique high-frequency high-impedance coaxial probes and a novel short-pulse measurement technique for characterization of resistive transmission lines. She is a Research Staff Member currently working on the design, analysis, and measurement of packaging and VLSI chip interconnections for future digital processor and communication applications. Her work involves the three-dimensional modeling, signal integrity and noise simulation, and testing of a large range of package lossy transmission lines from printed circuit boards, cables, and connectors to thin-film wiring on multichip modules and on-chip wiring. She has written 38 papers published in refereed technical journals, has given numerous invited and tutorial talks, and has received ten patents (three pending). She was Technical Program Cochair for the IMAPS Next Generation IC and Package Design Workshop for three years and cochaired the CPMT Society Future Directions in IC and Package Design Workshop for two years. Dr. Deutsch is a member of Tau Beta Pi and Etta Kappa Nu. She was an elected member of the IEEE Components, Packaging, and Manufacturing Technology Society Board of Governors for 2000–2002 and Vice-Chair of the CPMT Society TC-12 Technical Committee. She has received Outstanding Technical Achievement, Research Division, and S/390 Division Team Awards from IBM in 1990, 1993, 1996, 1999, 2000, and 2001. She cochaired for four years the IEEE Topical Meeting on Electrical Performance of Electronic Packaging. She was a Guest Editor of the IEEE TRANSACTIONS ON ADVANCED PACKAGING for five years and is an Associate Editor of IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES.

Barry J. Rubin (S’72–M’74) received the B.E.E.E. degree from the City College of New York, New York, NY, in 1974. He received the M.S. degree from Syracuse University, Syracuse, NY, in 1978 and the Ph.D. degree from the Polytechnic Institute of New York, Brooklyn, in 1982, both in electrical engineering. He joined IBM at its East Fishkill Facility in Hopewell Junction, NY. He has worked on power transistor design, CCD technology, circuit design, and, since 1976, on all aspects of electrical package analysis. In 1986, he transferred to IBM’s T. J. Watson Research Center, where he continues to work on electromagnetic analysis and novel analytical techniques for the accurate and robust calculation of electrical packaging parameters. He is known for his contributions as the primary developer of the commercially available EMSIM analysis tool and has received a number of patents on circuit and package-related devices.

Howard H. Smith (M’02) received the B.S. and M.S. degrees in electrical engineering from the New Jersey Institute of Technology, Newark, in 1984 and 1985, respectively. He joined IBM in 1984 as a Integrated Circuit Engineer at its Semiconductor Development Laboratory in Fishkill, NY, working in the area of high-performance masterslice designs. He is currently a Senior Engineer at IBM’s Server Division in Poughkeepsie, NY, where he is responsible for electrical analysis issues associated with high-density CMOS circuit technology and package-related products. His recent assignments include the development and coordination of on-chip noise verification processes for eServer processor designs. His expertise lies in the area of electrical noise modeling and prediction at systemlevel computer operation. He has coauthored papers in the area of system-level noise prediction, on-chip interconnects, and electromagnetic characterization of connectors and antennas. He also received several patents on circuit designs and methodology techniques related to his area of expertise.