A Comprehensive Optimization Methodology for ...

This is the accepted version of the following article: IEEE ISCAS, pp. 1358 – 1361, 2015, which has been published in final form at http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7168894.

A Comprehensive Optimization Methodology for Designing Charge Pump Voltage Multipliers Toru Tanzawa, Micron Japan, Ltd., 5-37-1, Kamata, Ota-ku, 144-8721 Tokyo, Japan, email: [email protected] 

Abstract—This paper proposes a comprehensive optimization methodology to simultaneously determine the clock frequency, area ratio of pump capacitor to switching circuit, number of stages, and capacitor size of integrated switched-capacitor charge pump voltage multipliers. Power efficiency of the charge pump is also discussed in various views. How the top and bottom plate parasitic capacitance and the threshold voltage of the switching circuit affect power efficiency is reviewed. The optimization methodology is demonstrated. Comparisons of the model with SPICE simulation results are also provided for validation. Index Terms—Charge pump, Optimization, Power efficiency, Switched-capacitor, Voltage multiplier, I. INTRODUCTION multipliers, or charge pumps [1], are used to VOLTAGE generate higher DC voltages from input voltages. Because voltage multipliers do not require inductors—only capacitors and rectifying devices—they are used in integrated circuits (ICs) such as dynamic random access memory (DRAM), Flash memory, power ICs for motor drives, liquid crystal display drivers, and so on [2]. Wireless sensing nodes and implantable microelectronic devices, which have been attracting the interest of researchers and engineers, also use rectifier voltage multipliers for energy harvesting [3]. These applications require low power (typically nothing higher than hundreds of μW) and have small form factors—features that are well-matched with the features of voltage multipliers. Energy sources are categorized into two groups: 1) DC, such as photovoltaic and thermoelectric generators, and 2) AC, such as UHF, vibrating electrostatic, piezoelectric, and radio-frequency generators [3]. Circuit analysis and modeling, with respect to voltage multipliers with DC input power, has been discussed in previous papers; including: steady state [1, 4]; dynamic behavior [5, 6]; equivalent circuit modeling [1, 6]; and optimized circuit design [6–13] under various design constraints. The performance among two-phase DC-DC switched-capacitor multipliers has been compared to identify the optimum topology with the smallest circuit area and has been showed that the Falkner-Dickson cell is the best for integration [11]. An explicit DC-DC Dickson charge pump model has been also proposed, analyzing the effect of the resistance of switching devices on the pump performance [12]. Optimization of charge pump circuits is demonstrated to determine the clock frequency and the area ratio of pump

VIN

VOUT Φ1

Φ2

Φ1

Φ2

(a) VTH

TOFF Φ1

C αT C

Φ

TON

αB C

Φ2

VIN 1/f

(b) (c) Fig. 1. (a) A four-stage charge pump, (b) non-ideal parameters, (c) clock waveform.

capacitor to switching circuit for maximizing the output current. However, power efficiency was not taken into consideration for optimization in [12]. Another optimum design of integrated DC-DC switched-capacitor multipliers has been expanded for minimizing power in a balance with area [13]. However, it assumed that the clock frequency and the area ratio of pump capacitor to switching circuit were given. As a result, to the author’s best knowledge, there is no paper in literature to show a comprehensive optimization methodology for integrated charge pump voltage multipliers which includes all the design parameters such as the clock frequency, the area ratio of pump capacitor to switching circuit, the number of stages, and capacitor size to be determined, not given. The purpose of this paper is to review power efficiency in various views and to propose a comprehensive optimization methodology. The proposed methodology will enable designers to estimate all the circuit parameters which provide required area and power under the condition where the input voltage, output current, and output voltage are given. II. POWER EFFICIENCY OF CHARGE PUMPS Fig. 1(a) illustrates a four stage charge pump. The number of stages is defined by the number of pump capacitors. In a realistic charge pump, each stage has non-ideal parameters such as the threshold voltage VTH of a switching circuit and the top and bottom plate parasitic capacitance ratio αT and αB, as shown in Fig. 1(b). A driving clock has a voltage amplitude of VIN, frequency of f, the time when the switching circuit turns on (TON) and off (TOFF). [12] provides VOUT – IOUT equation (1) when the switching circuit operates in triode regime using a gate boosting technique [14], where the channel resistance is characterized by a parameter R. (1) I OUT  (VMAX  VOUT ) / RPMP where RPMP, VMAX, and



are respectively

1


1 1  2 2 (2) (N  ) 2 fC (1   T ) 1  1  2 N (3) VMAX  VIN (  1) 1  T TON (4)   exp(  ) RC (1   T ) [13] provides IIN – IOUT equation (5), which is valid regardless of a value of VTH . RPMP 

N  I IN  (  1) I OUT  ( T   B ) fNCVIN 1  T 1  T

(5)

From (5), one can have the relation between power efficiency η vs. IOUT given by (6). fNCV IN   1 VIN  N (6)  (    1)  ( T   B )  VOUT  1   T 1  T I OUT  In an ideal case where αT = αB = 0, (6) is reduced to (7) [15, 16]. (7)   (VOUT / VIN ) /( N  1)  VOUT / VMAX Fig. 2 (a) shows an equivalent circuit [1], which describes (1). Input and output power are respectively given by VMAX IOUT and VOUT IOUT. As a result, η is given by the voltage ratio as shown in (7) in an ideal case. Fig. 2 (b) shows power expressed by the area of rectangles, where the base is IOUT and the height is VOUT for POUT and VMAX for PIN. When VOUT is closed to 0V, IOUT is closed to its maximum, as illustrated in the left most of Fig. 2(b). VMAX RPMP

η IOUT

η = VOUT / VMAX

1

IIN = (N+1) IOUT + fαBNCVIN

IOUT

VOUT RLOAD

Because the power loss is closed to 100%, η has to be closed to 0. As VOUT increases, η improves. When VOUT is closed to VMAX, IOUT is closed to 0. Even though POUT is closed to 0, η is closed to 1, as shown in Fig. 2 (c). Thus, power efficiency of an ideal charge pump is very analogue to that of a liner regulator, which is also determined by the ratio of the output voltage to the input voltage, because the equivalent circuit is the same. Fig. 3 provides a different view on how power efficiency is determined. POUT is given by the product of IOUT and VOUT. As shown by (1), IOUT is a first order equation of VOUT. As a result, POUT is a second order equation of VOUT. POUT has the maximum at VMAX/2, as shown in Fig. 3(a), where RLOAD = RPMP. This fact is known as impedance matching. IIN is proportional to IOUT in an ideal case where αT = αB = 0, as suggested by (5). As a result, PIN is a first order equation of VOUT, as shown in Fig. 3(b). Therefore, as shown in Fig. 3(c), η is given by a line with a slope of one, as shown by (7). Fig. 4 shows how the bottom plate parasitic capacitance affects power efficiency. αB does not affect VOUT – IOUT because it is not included in (2) and (3). On the other hand, IIN increases by the last term of (5), which does not have a factor of VOUT. Therefore, αB shifts IIN, i.e. PIN, in the vertical direction. As a result, η is affected at high VOUT most. Especially, η approaches zero at VOUT = VMAX rather than one in the ideal case. Thus, a finite αB creates the maximum point in η. Similarly, Fig. 5 shows how the top plate parasitic capacitance and the threshold voltage of the switching circuit affect power efficiency. The

VOUT VMAX

IOUT (a)

VOUT X

VOUT

VMAX

÷

X

VOUT

VOUT VMAX/2 VMAX

VMAX

η

VOUT VMAX

VMAX

VIN VOUT

VMAX POUT

VOUT VMAX

(a) (b) (c) Fig. 3. Characteristics of an ideal charge pump with no non-ideal parameters: (a) IOUT, VOUT, POUT, (b) IIN, VIN, PIN, (c) POUT, PIN, η

VOUT

÷

X

VOUT

1

POUT VOUT

X

VOUT PIN

VOUT VMAX

IIN

VOUT

VMAX

PIN

VIN

IIN = IIN(IOUT, αT>0, VTH>0)

VOUT

VMAX

X

POUT

VOUT VMAX

(a) (b) (c) Fig. 4. Characteristics of a charge pump with a finite αB: (a) IOUT, VOUT, POUT, (b) IIN, VIN, PIN, (c) POUT, PIN, η

IOUT

VOUT

VOUT

1

VOUT

POUT

IIN

VMAX

η

VMAX

(b) Fig. 2. (a) Equivalent circuit of a charge pump, (b) power expressed by the area of rectangles, (c) η vs. VOUT

÷

VMAX

VOUT PIN

POUT_MAX

IOUT

IIN = (N+1) IOUT

PIN

VOUT POUT

POUT

VOUT

X VIN

η = POUT / PIN

PLOSS

IOUT

VOUT VMAX

VOUT

VMAX

VOUT

POUT

VMAX

(c)

PIN = POUT + PLOSS

IIN

PIN VOUT η

PIN VOUT VMAX

VMAX

VMAX

1 VOUT VMAX

VOUT VMAX

(a) (b) (c) Fig. 5. Characteristics of a charge pump with a finite αT and VTH: (a) IOUT, VOUT, POUT, (b) IIN, VIN, PIN, (c) POUT, PIN, η

2


As discussed in [12], optimum clock frequency and optimum area ratio of pump capacitor to switching circuit can be determined so as to maximize the output current under a given technology. Now that power efficiency is expressed by (6) as a general form, one can expand upon [12] to have a comprehensive optimization methodology to take both power efficiency and area into consideration for determining the clock frequency, area ratio of pump capacitor to switching circuit, number of stages, and capacitance per stage at the same time. To demonstrate the methodology, design and device parameters [17] shown in Table I were used for model calculation and SPICE simulation. Fig. 7 shows IOUT and η as a function of R under the condition where the number of stages and the total capacitance CTOT are

Thus, capacitance per stage decreases as the size of switching circuit increases. In Fig. 8(a), the clock frequency is varied while the area ratio of pump capacitor and switching circuit is unchanged. When the frequency is low, IOUT is relatively small and η is relatively large. As the frequency increases, IOUT increases while η does not change significantly. When the frequency is as high as 100M-Hz, both IOUT and η become too low. It is difficult to determine the optimum frequency from this behavior. In Fig. 8(b), the area ratio of pump capacitor and switching 0.4

2.0E-04

Model 12.5MHz 0.3

1.0E-04

η

III. COMPREHENSIVE OPTIMIZATION METHODOLOGY

assumed to be 10 and 63pF, respectively. The errors in the data points with the model from the SPICE simulation were within 20%. Based on the results as shown in Fig. 7, trajectories for IOUT – η are plotted in Fig. 8. The top plate parasitic capacitance CT is determined by the size of the switching circuit, which is specified by the channel resistance R, via (9), where a technology-dependent parameter tRCT is assumed to be 1.4ns. (9) CT  tRCT / R Thus, the top plate parasitic capacitance is inversely proportional to the channel resistance. Then, capacitance per stage is provided by (10) because CTOT includes both area for pump capacitor and switching circuit. (10) C  CTOT / N  CT

Iout [A]

maximum attainable voltage VMAX is given by (8) when VTH is not zero [1]. N (8) VMAX  (  1)VDD  ( N  1)VTH 1  T In order to keep VMAX as high as the case where VTH is zero to have the same IOUT, one needs to increase N. Independently, as αT increases, N needs to be increased for compensation. To keep RPMP, which is given by (2), when N needs to be increased, one also needs to increase C. As a result, both first and second terms of the right hand side of (5) increases whereas IOUT is unchanged. Fig. 5(b) shows that IIN shifts in vertical direction due to the second term of (5) and its slope has to be steeper due to the first term. Thus, η is degraded even in a low voltage range, as described in Fig. 5(c). Fig. 6 shows simulated VOUT – η curves. The charge pump is designed to have η of 80% at VOUT = 12V in the ideal case. When αB of 10% is included, η is reduced by 25% at 12V. In addition, when VTH increases to 0.5V, N needs to be increased from 7 to 10. As a result, η is reduced to 40%. Thus, the parasitic components significantly affect power efficiency.

Model 25MHz

Model 50MHz

0.2

SPICE 12.5MHz 0.1

SPICE 25MHz SPICE 50MHz

0.0E+00 0.0E+00

2.0E+03 R [ohm]

0.0 0.0E+00

4.0E+03

2.0E+03 R [ohm]

(a) (b) Fig. 7 (a) IOUT and (b) η as a function of R. N = 10, CTOT = 63pF. 0.4 Model 2k-ohm

Power efficiency

Ideal w/ αB = 0 & VTH = 0

0.8

αB

0.6

η

0.3

1.0

Model 1k-ohm

Model 666-ohm

0.2

N=7 Vt=0V αB=0

0.1

N=7 Vt=0V αB=0.1

0.0 0.0E+00

SPICE 2k-ohm SPICE 1k-ohm SPICE 666-ohm

VTH

0.4 0.2

N=10 Vt=0.5V αB=0.1

0.0 5

10 Vout [V]

15

1.0E-04 2.0E-04 Iout [A]

3.0E-04

(a)

20

0.4

Fig. 6. Simulated VOUT – η curves in an ideal case and two realistic cases. VIN = 2.0V, VOUT = 12V, IOUT = 60μA, f = 10M-Hz, C = 10pF TABLE I: DEVICE AND CIRCUIT PARAMETERS

Model 12.5MHz 0.3

Model 25MHz Model 50MHz

η

0

0.2

SPICE 12.5MHz

USED FOR VERIFICATION

Parameter f R N VIN VOUT IOUT CTOT

4.0E+03

Max

Min

100M-Hz 10M-Hz 4k-ohm 250-ohm 14 8 2.5V 15V 270μA 63pF

Parameter CSTG tRCT CT C αT αB TOFF

Value CTOT/N 1.4ns tRCT/R CSTG - CT CT/C 0.22 2.0ns

SPICE 25MHz

0.1

SPICE 50MHz 0.0 0.E+00

1.E-04 Iout [A]

2.E-04

(b) Fig. 8 Comparisons of the model with the SPICE simulation. Variables are (a) the clock frequency and (b) the area ratio of pump capacitor to the switching circuit. N = 10, CTOT = 63pF.

3

0.4

0.4

0.3

0.3

0.2

η

η


8stg 10stg 12stg 14stg

0.1 0.0 1

2

3 4 Area [a.u.]

summarizes the methodology. IV. CONCLUSION

0.2 8stg 10stg 12stg 14stg

0.1

5

0.0 1

2

3 4 Area [a.u.]

5

(a) (b) Fig. 9 Area vs. power efficiency by SPICE simulation (a) and model calculation (b). TABLE II: OPTIMIZATION METHODOLOGY 1. 2. 3. 4.

5. 6. 7. 8.

IOUT, VOUT, VIN, given Technology and switching circuit selected Basic parameters of tRCT, TOFF, αT and αB determined Calculate IOUT and η using (1)-(6) by varying f under various the area ratios of pump capacitor to switching circuit per N. Area is assumed to be given. Determine the optimum area ratio to have the maximum IOUT and η per f per N. Calculate required area for each optimum area ratio per f per N to meet target IOUT using (11). Plot area vs. η per N. Select the best point which determines f, area ratio, N, and C, simultaneously.

REFERENCES [1]

[2]

[3] [4]

[5]

circuit is varied while the clock frequency is unchanged. When the area ratio of pump capacitor to switching circuit is large, the pump is in a state where the charge transfer is incomplete under a given frequency. As a result, IOUT is relatively small. When N and f are given, (6) suggests that η is a function of IOUT mainly because C is a weak function of the area ratio, and contribution of αB and αT is minor. Therefore, η is also relatively small when IOUT is small. As the area ratio decreases, more amounts of charges can be transferred in a half clock period. As a result, IOUT increases, thereby η also increases through the second term of (6). Thus, it is much easier to determine the optimum area ratio by clock frequency, at which both IOUT and η are maximized. Then, the required total pump area (CTOT_REQ) is calculated to output a targeted IOUT (IOUT_TAR) of 270μA in this demonstration using (11).

CTOT _ REQ  CTOT _ ASS  I OUT _ CAL / I OUT _ TAR

A comprehensive optimization methodology is proposed and validated by comparing the model calculation with the SPICE simulation. The proposed methodology will enable designers to estimate all the circuit parameters which provide required area and power under the condition where the input voltage, output current, and output voltage are given.

(11)

By doing the similar procedure for different number of stages, one can plot the optimum points in a single area – η plane, as shown in Fig. 9. The area is normalized by the minimum among the data points. Fig. 9(a) and (b) respectively show the results using SPICE simulation and model calculation. Both plots show that 1) power efficiency is about 20% when the charge pump is designed so as to have the minimum area, i.e., N = 14, f = 100M-Hz, and R = 700ohm, 2) power efficiency improves to about 30% when the area is allowed to be twice as large as the minimum, i.e., N = 10, f = 25M-Hz, and R = 2k-ohm, and 3) power efficiency is saturated at larger area. Discrepancy of the model from the SPICE result was about 40% in an extreme case where the number of stages was as small as 8, which barely generated 15V, but was within 20% in nominal cases where the number of stages is 10 or larger. As a result, it is validated that the model can provide the initial values for the circuit parameters when the design specification is given. Table II

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15] [16]

[17]

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