A Comprehensive Survey of Electrostatic Discharge Protection ■ James Chu
E
dited by Dr. Juin J. Liou in collaboration with Krzysztof Iniewski and 20 other editors, Electrostatic Discharge Protection: Advances and Applications brings together a team of experienced and well-respected researchers and engineers from around the world, representing universities and semiconductor industries, with expertise in electrostatic discharge (ESD). This book truly represents the hall of fame of ESD. Chapter 1, “Introduction to Electrostatic Discharge Protection” by Juin Liou, briefly introduces the fundamentals of ESD, including its mechanisms, standards, protection design principles, and testing methodologies. It focuses on application-specific integrated circuit (ASIC) protection design at the input and output (I/O) terminals. Quasi-static I–V operation with nonsnapback and snapback ESD protection is also explained. Chapter 2, “Design of ComponentLevel On-Chip ESD Protection for Integrated Circuits” by Charvaka Duvvury,
James Chu (
[email protected]), IEEE Senior Life Member, is with Kennesaw State University, Marietta, Georgia, United States. Digital Object Identifier 10.1109/MMM.2016.2564658 Date of publication: 11 July 2016
August 2016
Electrostatic Discharge Protection: Advances and Applications by Juin J. Liou ISBN 978-1-4822-5588-1 © 2015 CRC Press 304 pages US$149.95, hardcover
lists 14 ESD protection strategies, in cluding the local clamp approach and rail clamp design, and discusses how to protect the input of an ASIC from gateoxide damage and the output from
transistor junction breakdown. This chapter introduces an isolation resistor to limit the ESD current into the I/O devices and describes how to provide the voltage drop to trigger the primary protection device of a two-stage protection strategy. Chapter 3, “ESD and EOS: Failure Mechanisms and Reliability” by Nathaniel Peachey and Kevin Mello, focuses particularly on the conceptual framework and analysis of the entire scope of ESD and electrical overstress (EOS) failures. It includes a systematic presentation of the failure mechanisms and related reliability issues associated with ESD and EOS events. Elements of semiconductors that can be affected by ESD are oxides, junctions, and metals, all of which this chapter discusses. The authors also point out that N-type metal-oxidesemiconductor (NMOS) devices are typically more vulnerable to junction failure than P-type metal-oxide-semiconductor transistors are. Chapter 4, “ESWD, EOS, and Latchup Test Methods and Associated Reliability Concerns” by Alan W. Righter, covers the primary test methods used to evaluate integrated circuits’ robustness to ESD, transient overstress, and latch-up events. Additionally, reliability issues relating to these short-duration
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electrical events are discussed, and the failure mechanisms of GaNmany test standards (such as IEC based transistors for RF and power 61000-4-4, JEDEC, and SJ-002) are applications and of advanced lightemitting diodes for application also covered. Chapter 5, “Design of Power- in the general lighting field. The Rail ESD Clamp Circuits with Gate- chapter also summarizes the curLeakage Consideration in Nanoscale rent status of developments in ESD CMOS Technology” by Ming-Dou protection structures based on GaN Ker and Chih-Ting Yeh, provides and related technologies and their a comprehensive overview of the associated problems. Chapter 8, “ESD Protection Cirdesign of power-rail ESD clamp circuits in nanoscale complemen- cuits Using NMOS Parasitic Bipotary–metal-oxide-semiconductor lar Transistors” by Teruo Suzuki, (CMOS) technology. The authors describes a case in which an NMOS indicate that the power-rail clamp parasitic bipolar transistor is used circuit will continue to be an impor- in ESD protection circuits. The ESD tant design task for on-chip ESD stress application is discussed in protection as the process is further two parts—power supply or ground pin and between scaled down. power supply pin Chapter 6, “ESD and ground pin. Protection in Auto- The book Chapter 9, “ESD motive Integrated includes charts, D ev e lopme nt i n Circuit Applications” tables, test Foundry Processes” by Javier A. Salcedo by Jim Vinson, cova nd Jea n-Jacques procedures, ers how to manage Hajjar, focuses on and standards, the foundry and automotive electro making it a foundry selection, nics circuit protecproviding an samtion devices and must-have ple list of requiresystems and reviews for every ESD ments submitted to the design considdesigner. a foundry for quoerations and solut at ion, as wel l as tion approaches for these circuit applications operat- a foundry checklist. The author ing in such a harsh environment. indicates that the integrated cirAutomotive electronics are subject cuit development team should to a wider range of stress condi- not assume the foundry has tions, such as wide operation volt- adequate ESD just because the age, extreme temperatures, and acronym “ESWD” appears in the high-energy disturbances. A table documentation. An extensive evallisting the conductive disturbance uation of foundries’ ESD capability test standards, a summary of the is needed. Chapter 10, “Compact Modelkey parameters, and a second table listing the typical process technolo- ing of Semiconductor Devices for gies used for automotive integrated Electrostatic Discharge Protection circuit applications are features Applications” by Zhenghao Gan that will be useful to the circuit and and Waisum Wong, discusses compact models for diffusion and metal system designer. Chapter 7, “ESD Sensitivity of resistors, STI/gated diode, ggMOS, GaN-Based Electronic Devices” and vertical bipolar junction tranby Gaudenzio Meneghesso, Mat- sistors under ESD high-current teo Meneghini, and Enrico Zanoni, injection. Using these models in a reviews the main issues related to SPICE simulation program, one can the ESD instabilities of electronic evaluate a given circuit performance and optoelectronic devices based on under ESD stress prior to fabrication gallium nitride (GaN). It describes and testing.
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Chapter 11, “Advanced TCAD Methods for System-Level ESD Design” by Vladislav A. Vashchenko and Andrei A. Shibkov, introduces the simulation method of ESD design. Only numerical simulations can offer adequate accuracy for reducing the amount of time and resources spent on experiments to a reasonable limit. In addition to a pure empirical approach, the numerical simulation becomes the only realistic alternative to help ESD device and circuit engineers. A technology computeraided design (TCAD) method and mixed-mode simulation methods are introduced. Chapter 12, “ESD Protection of Failsafe and Voltage-Tolerant Signal Pins” by David L. Catlett, Jr., Roger A. Cline, and Ponnarith Pok, defines failsafe, pseudo-failsafe, and non-failsafe. The authors point out that I/O designers and ESD development engineers are working from the same set of topology definitions; a table is provided that summarizes these. In addition, a checklist listing integration challenges early in the development cycle is given, along with I/O performance and cost. Chapter 13, “ESD Design and Optimization in Advanced CMOS SOI Technology” by You Li, discusses silicon-on-insulator (SOI) transistors that, having thinner gate-oxide thickness and shorter channel length, are more susceptible to ESD stress, making the design of robust ESD protection solutions more challenging. In this chapter, two types of primary ESD protection devices used in SOI technology—the ESD diode and siliconcontrolled rectifier—are discussed, and optimization methodologies are also proposed. This book is an A-to-Z complete guide for the ASIC ESD designer; it includes charts, tables, test procedures, and standards, making it a must-have for every ESD designer.
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