A Constructive Approach for Threshold Logic. Circuit Synthesis. Augusto Neutzling1; Mayler G. A. Martins2; Renato P. Ribas1,2, André I. Reis1,2.
A Constructive Approach for Threshold Logic Circuit Synthesis Augusto Neutzling1; Mayler G. A. Martins2; Renato P. Ribas1,2, André I. Reis1,2 1
PPGC / 2PGMICRO, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil. {ansilva, mgamartins, rpribas, andreis}@inf.ufrgs.br
Abstract – In this paper, a novel method to synthesize circuits based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS integrated circuits due to its suitability to emerging technologies, such as tunneling diodes, memristors and spintronics devices. A constructive process is applied to generate optimized TLG networks taking into account multiple goals and design costs, including gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits have shown an average gate count reduction of circa 32%, reaching up to 54% in some cases, in comparison to related approaches. Keywords – Digital circuit, logic synthesis, threshold logic, functional composition, threshold networks, TLG.
I. INTRODUCTION The limits of MOS transistor scaling have motivated investigations about new alternative devices, such as spintronics, resonant tunneling devices (RTD), quantum cellular automata (QCA), single electron transistor (SET) and memristors [1]-[3]. In this new scenario, it has been verified that threshold logic gates (TLG) are more suitable to implement digital integrated circuits (ICs) based on these new technologies, differently from the standard AND/OR based CMOS circuit design [4][5]. However, specific CAD tools must be available for developing TLG based ICs. In this sense, one critical task is to obtain efficient network built using TLGs to implement a specific Boolean function. In [5], Zhang et al. proposed a recursive partition of a logic function that is not threshold and merge nodes respecting fan-in restrictions. Unfortunately, the quality of results is very sensitive to the initial Boolean network. On the other hand, the method presented by Subirats et al., in [6], is based on the truth table description of the function. The algorithm compute an ordering of variables using information of on-set and off-set, performing Shannon decomposition up to find threshold logic functions (TLF). However, this approach provides as output a two-level threshold network, without fan-in restriction, being more suitable for neural networks than for IC design. In [7], Gowda et al. used a factorized tree to generate a network of threshold gates. The method recursively breaks the given initial expression tree into sub expressions, identifying sub-tree that are TLFs and assigning the input weights. It is appropriate for IC synthesis using several TLGs, but represents a very time consuming process and presents a strong dependence to the initial expression structure, including the ordering of the initial tree.
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In this paper, an algorithm is proposed to synthesize threshold networks aiming to (1) minimize threshold networks taking into account other costs besides threshold gate count, like logic depth and number of interconnections, (2) generate more than one effective solution, considering a design cost order, and (3) eliminate the structural bias dependence in order to improve the quality of results. It is based on a constructive synthesis [8]-[10], which associates simpler sub-solutions with known costs in order to build more complex networks, allowing the optimization of different cost functions other than just the TLG count. The algorithm uses a novel AND/OR association between threshold networks to reduce the total number of TLGs in the circuit. The rest of this paper is organized as follows. In Section II, some fundamentals are briefly presented for a better understanding of our approach. Section III describes the algorithm proposed to synthesize threshold logic networks. Section IV provides the experimental results, whereas the conclusions are outlined in Section V. II. PRELIMINARIES First of all, basic concepts of threshold logic are briefly reviewed for a better understanding of the proposed method. A. Threshold Logic Gate Differently from the traditional logic gate design, the threshold logic gate (TLG) implements Boolean function considering weight values for inputs (function variables) and a gate threshold value to be attained. If the sum of weights of activate (‘1’) inputs is equal to or higher than the given threshold value, then the output logic level of the TLG is high (‘1’). Otherwise, the gate output is at low level (‘0’). Such operating principle can be expressed as follows: 1 if f 0
n
w x i
i
T
i 1
(1)
, otherwise
where xi and wi represent the logic value and weight of each input, respectively, and T is the threshold value [11]. B. Threshold Logic Function Threshold logic function (TLF), also called linearly separable function, is a Boolean function that can be implemented into a single TLG. TLF can be completely represented in a compact vector format such as [w1,w2,…,wn;T]. For instance, the function ƒ = x1.x2 + x1x3 can be represented as ƒ = [2,1,1;3].
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In this paper, we adopt a graphic representation of TLG, writing the threshold value inside the node and the input weights at the edges, as illustrated in Fig. 1 for the Boolean function ƒ = [2,1,1;3].
Figure 1 - Representation of threshold logic gate (TLG).
C. Threshold Logic Identification A TLF can be a complex function, such as g = x1.x2 + x1.x3 + x2.x3.x4 + x2.x3.x5 which corresponds to the TLG g = [4,3,3,1,1;7]. For this reason, an important advantage of threshold logic is the reduction in the number of gates, decreasing the circuit area and power consumption. By definition, all TLF are unate functions, but not all unate functions are necessarily TLF [11]. Therefore, if a function presents binate variable(s), it is not a TLF, i.e., it cannot be implemented into a single TLG. Function h = x1.x2+x3.x4 is an example of unate function that is not TLF. The threshold logic identification process corresponds to the task responsible to determine if a Boolean function is TLF (or not), and compute the input weights and the gate threshold value. In this work, we have adopted the identification process proposed in [12] because it is faster than integer linear programming, used in previous methods [5][6], and provides effective results. III. PROPOSED METHOD The description of our method has been roughly divided into four main parts. First of all, the adopted data structure is shown. Next, it is demonstrated a generic method to perform AND/OR association in TLGs without increasing the number of gates. A method to obtain optimal fanout-free threshold networks of Boolean functions, having up to 4 inputs, is then discussed. And finally, these functions are used to compose heuristically functions up to 6 inputs. A. Threshold bonded-pair Some works in logic synthesis exploit a bottom-up approach to synthesize circuits as shown in [8] and [9]. In this work, we use a constructive approach named functional composition [10]. This approach allows great flexibility to manipulate threshold networks due to use of bonded-pair. a 0 0 1 1
b 0 1 0 1
f 0 1 1 0
f =a !b + !a b
f = T[a(1),b(-1),T[a(1),b(-1);1](2);1]
Figure 2 - Bonded-pair representation for threshold networks.
The bonded-pair representation comprises the tuple {function, threshold network}. The function can be represented as an integer array or the root node of a BDD,
whereas the threshold network can be represented by a subject graph or a particular expression that represents a threshold logic tree. Fig. 2 shows an example of bonded-pair representation using an expression related to the corresponding logic tree. B. Threshold bonded-pair association The bonded-pair association may guarantee the equivalence between both functional and structural representations. A trivial and naïve way to associate two threshold gate structures is to create a new TLG with 2 inputs, having the input weights equal to ‘1’ and the gate threshold value equal to ‘2’ for AND operation and equal to ‘1’ for OR operation. Fig. 3(a) illustrates such a naïve approach. However, the main drawback of this approach is the instantiation of a TLG to each AND/OR association, becoming too expensive and even unfeasible the implementation of several complex Boolean functions.
(a) (b) (c) Figure 3 - Different approaches to associate threshold networks: (a) a naïve solution, (b) an improved way and (c) the proposed one.
An alternative solution to reduce the overhead introduced by the naïve approach is to store the last operation used to synthesize the functions. Consider that AND and OR threshold gates have all n-input weights equal to ‘1’, and the threshold value equal to ‘n’ and to ‘1’, respectively. It is easy to take advantage of this characteristic using the top operation of each TLG to avoid the overhead of generating an extra TLG for each operation, as depicted in Fig. 3(b). However, this approach does not eliminate completely such overhead in the generated threshold network. When the top operation is different from the current operation, the naïve approach is performed in order to compose a new threshold network. An optimized method to associate bonded-pairs, avoiding such an extra TLG in the resulting implementation, is required to reduce the gate count. In [5], Zhang et al. proposed a simple and efficient OR association. The following theorem is related to perform AND association using a general n-input TLG. Theorem: If a Boolean function f(x1, x2, ... , xn) is a threshold logic function, then h(x1, x2, ... , xn+1) = f(x1, x2, ... ,xn) ^ xn+1, being ^ the OR operation, is also a threshold function, where the threshold value Th is defined as Th = ∑(w1,w2, ... ,wn) and the input weight wn+1 of input xn+1 is defined as wn+1 = Th – Tf. Proof: Without loss of generality, assume f has only positive unate variables. There is an input weight-threshold vector [w1,w2, ... ,wn;; T] for f , since f is a threshold logic
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function. Considering h = f(x1, x2, ... ,xn) ^ xn+1, the output of the function h is ‘0’ when xn+1 is assigned ‘0’. Therefore, the threshold value Th must be greater than ∑(w1,w2,… ,wn). If xn+1 is equal to ‘1’, then the function h is equal to f. Therefore, wn+1 is the difference between Th and Tf threshold values. To illustrate the theorem, let f1(x1,x2,x3) = x1x2 + x1x3 that is a TLF represented by [2,1,1;3]. Then, h1(x1, x2, x3, x4) = (x1x2 + x1x3) ^ x4 is also TLF represented by [2,1,1,2;5], since Th = 1+∑(w1,w2,w3) = 5 and w4 = Th – Tf = 2. C. Optimal 4-input threshold network generation In order to speed-up the synthesis process of threshold networks, an approach using a lookup table (LUT) containing TLGs represents an effective solution. Optimal TLG implementations containing all functions up to 4 inputs can be easily generated with a straightforward procedure. This approach is interesting for a mapping point-of-view, since it is necessary only one execution to generate a full library, and the results are stored for posterior reuse, so avoiding the matching task. The set used to store bonded-pairs is called bucket. The direct and negated variables are stored in bucket 0, since they do not have gate implementation costs. The next task is generating all functions that can be implemented as a single TLG. All unate functions up to n variables (n
