A Course of Study in Computer Hardware Architecture

A Course of Study in Computer Hardware Architecture Report of the IEEE Computer Soacety Task Force On Computer Architecture

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Module

0

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George E. Rossmann Palyn Associates, Inc. Michael J. Flynn Stanford University Samuel H. Fuller Carnegie-Mellon University

Preface

The subject of computer architecture as currently taught in most computer engineering and computer science programs is a mixture of architectural principles, organizational strategies, and implementation techniques. This blurring of the hierarchy of system levels that characterize the structure of a computer has made it very difficult for students (and. often instructors as well) to determine what were the forces that led to the design decisions they have seen reflected in machines. Guidance for the development of courses in computer architecture has come from the ACM Curriculum Committee on Computer Science [ACM681 and the COSINE Committee of the Commission on Engineering Education [COS68]. In 1968 these committees both proposed syllabuses for a course in computer organization. The ACM committee also proposed the content for an advanced course in computer organization. The material in these courses is characterized by the confusing mixture of topics we have already mentioned. The courses also suffer other shortcomings. They contain sketchy topic outlines rather than detailed specifications. They pay insufficient 44

C. Gordon Bell Digital Equipment Corporation Frederick P. Brooks, Jr. University of North Carolina at Chapel Hill Herbert Hellerman State University of New York at Binghampton

attention to the fact that to a user the essential part of any computer system is its visible facilities: language processors, operating system, and other software. Therefore, they do not support the integration of hardware and software design that is required to create computer systems which satisfy the user. Finally, computing environments and basic technologies have changed significantly since the ACM and COSINE committees made their recommendations, and these changes need to be reflected in a computer architecture course description. In view of these circumstances, a task force was established by the IEEE Computer Society to prepare a detailed specification for a course of study in computer architecture for students whose major interest is in computer engineering or computer science. The members of the task force were: George E. Rossmann, chairman, Palyn Associates, Inc.; C. Gordon Bell, Digital Equipment Corporation; Frederick P. Brooks, Jr., University of North Carolina, Chapel Hill; Michael J. Flynn, Stanford University; Samuel H. Fuller, Carnegie-Mellon University; Herbert Hellerman, State University of New York at Binghampton.

COMPUTER

Plan of the Report The structure of this report has been motivated by three considerations. First, the report is concerned primarily with computer hardware architecture. Second, the course of study is intended for students for whom computer architecture supports their interest in computer engineering or computer science. These people need to be familiar with all of the topics discussed here. This course of study is not sufficient, however, for the training of the professional computer architect. The introduction to Module 1 explains why. Third, the universities using this report will vary considerably with respect to plans' for packaging this material into academic courses, instructor capability, student ability, and student preparation. The first and second considerations determined what material should be included, and the third consideration determined how it should be organized. The material presented has been restricted to those topics which we feel every computer engineer and computer scientist ought to know and to those computer systems which have been in the mainstream of commercial equipment. As a result, topics such as the early history of computers; parallel, pipeline, associative, and array processing; the effectiveness of various' machine structures in performing various computations; implementation details including busing structures and interfacing conventions; and switching structures have been conciously excluded from this course of study. We have organized the material presented into 11 modules, each dealing with' a fundamental aspect of computer hardware architecture. The modules are: Module No. 1 2 3 4 5 6

7 8 9 10 11

Title Introduction and Meta Representation Data Representation Instructions and Addressing Interpretation and Control Memory Hierarchies Protection Mechanisms and Hardware Aids to Supervision Specialized Processors

Multiple Computers Performance Evaluation Reliability System Design Evaluation

The packaging of these modules into academic courses is up to individual instructors. However, they must generally be taught in the order indicated. The material in modules 1 and 11 may be interspersed throughout the course of study rather than being treated as separate items. We have tried to help by suggesting the amount of time which should be devoted to each module and its sub-topics, and by precise specification of the references which support each topic. One grouping of the modules we have found effective is: Module 1: Meta Representation Modules 2-5: Classical Processor/Memory/Switch Aspects of Computer Architecture Modules 6-8: Aspects of Systems Architecture Modules 9-11: Evaluation Methods 7nd Analysis. December 1975

In addition, depending upon the composition of the class, whether computer engineers or computer scientists, the instructor may choose to emphasize, respectively, the hardware implementation or software engineering consequences of various architectural decisions. We believe that it is possible within the scope of this course of study to undertake term projects that involve design. However, it was unfeasible for us to offer guidance in this area. Instructors will have to define projects based on their resources and the abilities of their students. There is, of course, a temptation to do a machine sketch, but the committee does not encourage such a project because we feel that the essence of the design process lies in probing deeper than the sketch level to understand the interrelations between various design decisions. The only textbooks currently available that cover a reasonable amount of the material proposed in this course of study are: Computer Structures: Readings and Examples, C. G. Bell and A. Newell [BEL7 1]; Digital Computer System Principles, H. Hellerman- [HEL73]; and Introduction to Computer Architecture, H. Stone'(ed.), [ST075].

Background To be prepared for this course of study in computer architecture the student should have a good understanding of (1) programming in both assembly language and higher-level languages, and (2) how at least one simple computer works. The necessary experience in programming can be obtained from any -course that introduces the notion of computing through the use of an algorithmic language such as FORTRAN, ALGOL, or PLI. Familiarity with assembly language programming' and the organization of a simple machine can be obtained fro'm a course based on a text such as [ST072] or [GEA74]. It is desirable for the student either to have had a course in logic design or to have been exposed to logic design in either of the prerequisite courses just described. However, since many students interested in computer architecture may be engaged in software engineering programs, we have arranged this course so that logic design is not an essential prerequisite. Some of the modules require additional prerequisites such as elementary statistics and probability, and depend on an understanding of preceding modules. Such dependencies are indicated in the introductions to the individual modules.

Module 1 - Introduction and Meta Representation (2 Hours) Introduction (1 Hour) What is computer architecture? A number of definitions have been advanced. Architecture describes the attributes of a system as seen by a programmer-i.e., the conceptualstructure and functional behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation. Architecture is the study of those aspects in the analysis and design of computers which specifically relate their structure and their 45

function. Computer architecture is the discipline devoted to the design of highly specific and individual computers from a collection of common building blocks. We decided not to adopt any of these definitions. Instead we defined computer architecture by deciding what professional architects are supposed to do. The committee determined that the computer architect's task is to define computer systems that use hardware and software technologies so as to best satisfy all the users' needs, including function, economy, reliability, simplicity, and performance. In carrying out this task, the architect must develop an understanding of the potential applications of each system and then bring to bear extensive knowledge of the material in this course of study, operating systems principles [COS71], implementation details, component technologies, and many other things to accomplish its design. Computer hardware systems are complex. There are at least five levels in any implementation of a computer system: a. processor/memory/switch (PMS) level b. programming level which includes operating systems c. register transfer level d. switching circuits level e. circuit or realization level

construction. For example, in the case of microprograms, programs translate the descriptions from the syntax of an assembler or compiler language into a form for construction, simulation, and verification. There has also been considerable interest in translating the formal description of each system level in a computer structure into a realization of that level automatically. For the high-level block diagrams that represent the components of computer systems (e.g., central processors, primary memories, and secondary memories), there is a need for precise descriptions simply to permit novices to understand them readily. Such notations also permit comparisons. Descriptions that show the connectivity of a structure lay the foundation for the automatic generation of models for performance and reliability calculations. A formal representation permits automatic verification and construction of configurations. That is, a specific computer system can become the basis for a variety of configurations each of which depends on the number and type of components that are used to form it. It is generally quite difficult to verify that each such configuration will be viable when realization considerations such as power, floor space, interconnection cable lengths, input-output bandwidths, reliability, etc., are accounted for.

Each level arises from abstractions of the levels below it and is characterized by a distinct language for representing its components, its modes of combination, and its laws of behavior. The first three levels of this hierarchy are the proper study of the computer hardware architect, because the architect must decide how to distribute the complexity inherent in a computer system among them. Not much will be said about software and operating systems directly, but their influence on hardware architecture will permeate all the modules. Moreover, we have tried to show how the boundaries between these levels keep changing and how this impacts design.

of:

Meta Representation (14 Hours) The general problem addressed in this submodule should be discussed briefly to introduce the student to the need for formal description. Specific notations can then be introduced naturally when the need for them arises. Therefore, the time allotted to this submodule should be distributed throughout the course of study. In order to communicate about machines, one must have suitable languages. Communication dialogues include user-vendor, vendor-system designer, system designerprogrammer, student-teacher, etc. The earliest communications concerning machines took the form of standard prose and conventional mathematics (including standard and Boolean algebra) and used ad hoc diagrams and flowcharts to describe the structure and operation of the object being built. As machines evolved into complex structures, however, it became important to use more precise languages in order to communicate the designs exactly but simply. The formality of contemporary descriptions also implies that they can be understood by machines. It is useful to have machine-readable descriptions of machines so that they may be simulated and hence verified prior to their actual 46

Some aspects and uses of notations include description

(a) The functional specifications of a system with conventional prose. At the topmost level of system description, users must express their needs and work with computer architects to refine these expressions into meaningful specifications through the medium of conventional prose. (b) The physical structure of a particular computer system including its various processors, memories, peripherals, and their interconnection. (c) The instruction set with its interpretation and the definition of data-types and operations on these data-types. Such a description may be used in lieu of standard programming reference manuals. Currently, most machines are described in conventional prose, but also contain an informal register transfer notation description of the behavior of each instruction. Nearly all machines have a simulator written in a high-level language that runs on another machine. (d) The physical organization of a particular processor, including its registers, data operators, data flow, and control. Usually this is ad hoc on a functional diagram basis. The behavior of such a system is specified using register transfer languages and conventional programming languages. The outcome is a description suitable for simulation. For microprogrammed machines the behavior is expressed as an assembly language listing and/or flowchart. (e) The syntax and semantics of data structures. In currently evolving hardware structures, especially communication links, more complex data structures are being directly interpreted. The interconnection of computer components (computer-computer, computer-terminal, etc.) depends on complex communications protocols. These message protocols are expressed in Backus-normal form, state diagrams, flowcharts, and timing diagrams. (f) Combinational and sequential logic with logic diagrams and Boolean algebra. Such descriptions enable gate and circuit level simulation of the objects.

COMPUTER

Module 1 - Topic Outline Prose and Informal Diagrams Initial functional specifications of a system. Computer reference manuals [e.g., CDC66; DEC10; IBM70]. Block Diagrams (Two-Dimensional) to Represent System Structure Computer components. Processors, memories, controllers, transducers (I/O equipment), links, switches (buses). [BEL71, Ch. 2 (PMS); system block diagrams from any computer reference manual] Register transfer level block diagrams. Combinational and sequential logic. Block Diagrams (Two-Dimensional) to Represent System Behavior Flowcharts and/or state diagrams for sequential circuits, microprograms, and communication link protocols.

Languages (One-Dimensional, Formal, Machine Interpretable) Instruction set definition. [FAL64; BEL71, Ch. 2 (ISP); CHU72; HIL73] Number representation: mathematical notation and conventions. Register transfer and logic behavior including microprograms. APL and APL-derivatives. [HEL73; HIL73] ALGOL-like. [BEL7 1, Ch. 2 (ISP)] FORTRAN-like. [CHU72] Logical design: Boolean algebra for combinational logic and time difference equations for sequential circuits. Communication-message formats (syntax and semantics) for communication links. [Backus-normal form]

In summary, to understand, analyze, synthesize, and generally communicate with one another and with machines about machines requires various informal and formal representations. As one considers each aspect of computer architecture, representation is the basis for understanding.

Module 2

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Data Representation (5 Hours)

Computers exist to manipulate information. Therefore, designing the ways in which the information is to be represented is a first and central step in computer architecture. The set of operations to be performed follows from the set of data types to be manipulated. Since one wants the operations for manipulating program information to be as much as possible like other data operations, the selection of data representations creates strong biases as to the formats and representations of instructions. A good way to teach this module is to lead students through a decision tree representing the data representation design decisions for a general-purpose or special-purpose computer. December 1975

The objectives of the module are: (a) To teach a rather general point of view about representation, since creativity with respect to new representations and, a sharp awareness of existing ones lead to innovative program and machine design. (b) To show the numerous and sometimes subtle considerations affecting each representation decision. (c) To show how representation decisions interact, thereby introducing the student to the notion of system design, which requires optimizing a set of tightly coupled decisions. General references: [ST075, Ch. 2; BEL71, Ch. 3; BRO69, Sec. 6.2; KNU68, Ch. 2].

The Notion of Representation (1/2 Hour) Representation of concepts by language elementsnumbers, letters. Representation of language elements by bits. Allocation of a set of bits. Encoding of values by a bit configuration. Centrality of representation to architectural process. Structure of the Representation Space (1/2 Hour) Resolution What will be the smallest named and manipulable element? For example: 1 bit - IBM Stretch, Burroughs Bi 700, CDC Star 6 bits - Univac 1108, Honeywell 6000 8 bit byte - IBM S/360, DEC PDP-1 1 18 bit halfword - DEC PDP-10 36 bit word-IBM 7094.

Data Element Sizes Systems require consistency among the several sizes. Consider the representation families of some systems: IBM S/360: 4, 8, 16, 32, 64 bits. [AMD64] Univac 1108: 6, 9, 12, 18, 36, 72 bits. Burroughs B6700: 4, 6, 8, 48, 96 bits. CDC 6600: 60, 120 bits. [THO70, Ch. 5]

Data Formats (4 Hours) Data types are derived from architectural and applications requirements.

Fixed Point Numbers Choice of base: binary, decimal (IBM 650, IBM 1401). Sign representation: IBM 7094, CDC 6600, IBM S/360. Mixed Fixed Numbers Scaling. [MCR57, Ch. 4; STE72, Ch. 7]

Floating Point Numbers General reference: [BUC62, Ch. 8; STR74] . Location of radix point. CDC 6600, IBM S/360, Burroughs B5500. Mantissa base and sign representation. [BRW69;

COD73]

47

Exponent base and sign representation. Precision, significance, significance alarms and measures. [BRE73; KUK73]. Normalization, guard digits, rounding. [KAN73] Character Strings Encoding of characters: ASCII, EBCDIC, BCD. [BUC62, Ch. 6] Distinctions between internal and external representation of characters. Inherent length variability arises from applications. Various methods exist for accommodating variable length fields and for specifying lengths. IBM 1401, IBM S/360, Burroughs B5500. [BUC62, Ch. 4] Bit Strings If bits are independent and re-orderable by the designer, they really form a set represented as a vector. Special operations for bit vectors [IVE62, Ch. 1]; for bit strings [BUC62, Ch. 17]. Burroughs B1700, IBM Stretch, CDC

Star.

Higher Structures Complex numbers. Vectors. CDC Star. Chained representations of vectors, FIFO, LIFO (stacks). Burroughs B5500. [BAR61] Matrices, trees. Both of these map neatly onto vectors, hence processors with vectorial memories. ILLIAC IV, STARAN. [IVE62, Sec. 1.23; BER71] COBOL, PL/I structures: trees of inhomogeneous elements. Lattices, graphs, and nonplanar nets: representation by chained structures. [MCA60; ROS6 1 Data flags: embedding control information in data. Burroughs B5500. [IL168, Ch. 2-3; BUC62, Sec. 7.9; FEU72; FEU731

Module 3- Instructions and Addressing (5 Hours) In all electronic computer technologies up to now, memory speeds have been at least as slow as, and usually much slower than, operation speeds. Therefore, the performance of a computer can be first-order approximated by the memory bandwidth, the number of bits per second delivered (or accepted) by the memory, running continuously. For most applications, regardless of the machine, about half of the bandwidth is used for data, about half for

instructions.

The architect, therefore, tries to improve the costperformance ratio of his design by utilizing the memory bandwidth efficiently, in Shannon's sense. The design of data representation has been treated in Module 2. This module treats the design of instruction representations. Whereas many decisions about data representation are almost dictated by the characteristics of the data from intended applications, instruction representation gives wide scope for design differences. Indeed, the most striking differences in computer architectures have historically been concentrated here. 48

An instruction consists of the specification of (usually) a

single operation and the operands for it. The design decisions, therefore, are:

* What set of operations shall be allowed? * How shall a particular operation be specified? How shall the operands be specified (addressed)? How shall all the specifications be fitted together into an instruction format?

The objectives of the module are: (a) To teach the student to think of the bit as his raw material and its efficiency of use as a first-order estimator of goodness of design. (b) To survey the wide variety of techniques that have

been used in instruction specification, particularly the efficient specification of addresses. (c) To show the tight interaction among representation decisions enforced by the necessity to make instruction formats commensurate with data formats, which enforces a

bit-budget.

General references: [BEL71, Ch. 3; GEA74, Ch. 2;

HEL73, Ch. 8,9].

Operation Sets (2 Hours)

What to include? Frequency of use the chief test. [FOS71; CON70;

WIN73]

Fewness of operands an important test. (WIR68 and ANA73 discuss operation-set shortcomings of the IBM S/360). Operations determined by data types selected. [BEL71, Ch. 3]

Housekeeping. [FLY741 Processor state changes: Loads and stores. Operations on addressing and indexing mechanisms. Movement of data, partitioning, shifting.

Arithmetic. +,-,X, ., shifting. [CHU62; STE72; ST075, Ch. 1; HEL73, Ch. 7]. In either this section or in Data Formats (pp. 47), algorithms which implement the common arithmetic operations +,- X, -, and shifting should be discussed. These algorithms, of course, depend on the method of representing data. The advantages and disadvantages of various forms of data representation should be discussed. Square root, radix conversion and other options.

[CHU62]

Floatinig point. [SWE65; STE72; STR74] Comparisons and tests.

Sequencing. Branching. Subroutine linkage.

Operations on sequencing mechanisms such enabling/disabling interrupts.

as

Synchronization of concurrent activities. Input-output operations.

Addressing (2 Hours) Name-Space Structure (Main and Secondary) Numeric names. (IBM 604 Electronic Calculating Punch, circa 1948, had arbitrary names.)

COMPUTER

Associative (stored name) - MU5 vs. geometric (built-in

name). Vectorial (most machines) vs. matrix (STARAN, ILLIAC IV) vs. tree ([MCA 60]-LISP) vs. network (Burroughs B6500-segmentation) name structure. Number of independent name spaces. [DEN65; ARD66; DEG70; RAN69] Overlapping name spaces. General purpose registers are addressable memory locations. DEC PDP-10, Univac 1108

Operand Specif cation Within the Name Space Full address in instruction. DEC PDP-10, IBM 7094 Abbreviated addresses. Necessity due to large memories and program locality (nonuniform-access distributions). [AMD64] Bank Registers-The contents of a bank register are concatenated to the left end of the displacement field to enlarge the effective address. DEC PDP-8, HP 2100 Base Registers-The contents of a base register can be added to a displacement field (IBM S/360) or used in relative addressing (Univac 1108). Descriptors or control words, referenced by short address. Burroughs B5500 and B6500, MU5. [IL168; KIL68] Effective address calculation. [BLA59] Index registers. IBM S/360, CDC 6600, DEC PDP- 11, DEC PDP- 10, Univac 1108 Indirect addressing. Single level. IBM 7094, DEC PDP-1 1 Multilevel. HP21 00, DEC PDP-10 Programmed-Indirection achieved through Load Address instruction. IBM S/360 Descriptors-A Special form of indirect address. Burroughs B5500 Immediate Address-Direct implementation of operand in instruction. IBM Stretch

Formats (1 Hour) [LAW68; KIL68] Importance of Frequency Arguments in Format Design CDC 6600 NOP's waste bandwidth. Format Components Format Specifier. Operation Code: fixed vs. variable length vs. extensions. Addresses (including abbreviated ones). Address Modification Specifications.

Sequencing.

Format Sizes Size must be commensurate with data representation and subfields must be commensurate with readily-accessible data units. 16, 32, 48 bits: IBM S/360 15, 30 bits: CDC 6600 8, 16,..., 96 bits: Burroughs B6500 36,72, 108, 144 bits: Honeywell 6000 December 1975

Operation Code Specification Fixed-size. IBM S/360, CDC 6600 Variable-size. DEC PDP-1 1 Huffmann-coded. IBM Stretch, Burroughs B1700 Direct bit-significance. DEC PDP-8 Number of Addresses Examples: 1+1 1 0 IBM 650 IBM 7094 Burroughs B5500 3+ 1 2 3 EDVAC IBM S/360 CDC 6600 Stacks as a mechanism for eliminating addresses. [BAR61; BRO63; BAR69; AMD64; ST075, Ch. 71 Accumulator, multiplier registers as implicit second, third addresses. IBM 7094, IBM S/360, Univac 1108 Multiple accumulators for abbreviated second, third addresses. IBM S/360, CDC 6600, DEC PDP- 1. IBM S/360 fixed and floating point registers distinguished by operation code. Next instruction address. IBM 650, EDVAC. Explicit sequence specification is rare because redundancy is so high.

Module 4- Interpretation and Control (6 Hours) The writing of interpretive routines is usually taught independently and separately from the notions of instruction execution and interrupt handling. This module attempts to stress the unity of these ideas. Interpretation is the assignment of meaning to an expression applied to specific data, whether the expression is in a high-level, assembly, or low-level (so-called microprogram) language. It is invoked by a control mechanism which selects a series of operations to be performed at the (virtual) machine level that implements the interpretation (execution). The control mechanism then makes the next expression ready for interpretation (sequencing). The emphasis of this module will be on control within an interpretive routine and control between

interpretive routines. For example, if the expressions are assembly language instructions, the control mechanism selects a sequence of register transfer level operations to decode and execute the operation; specified in an instruction. The control mechanism then either fetches the next instruction for interpretation or, if an external event (interrupt) has been signaled, initiates an interpretive routine to handle the interrupt. One way to intrk duce this module would be to discuss the interpretation of assembly language macroinstructions. Have the students program a small number of short interpretive routines in assembly language and then show them how to link and sequence through these routines. The macro sequence should include setting and testing conditions, branc-hing, and executing the interpretive routines. One interpretive routine should be devoted to the handling of interrupts. Some of the concepts of Module 3 49

could also be brought out during these exercises: passing of parameters, generation of addresses, representation of an instruction, operation sets, etc. After this introduction, a detailed treatment of assembly language instruction interpretation should follow. Sequencing between instructions should be discussed. The definition of the conditional. branching mechanism should be especially stressed because it plays such an important role in hardware/software interaction. The original "IF" and "DO" specifications of FORTRAN represent the effects of attempting to build a language in which programs would be as easy as possible to translate into IBM 704 machine language. They were direct descendants of the IBM 704 compare and TIX instructions. There are numerous converse examples of machine- designers mapping higher level language artifacts into hardware. The treatment of conditional operations should also include a discussion of the modifications that can be made once a test is complete. That is, once one control path is selected, exactly how is a new instruction address determined? The role of metainstructions such as REPEAT and EXECUTE, which are themselves interpretive routines, should be discussed. Sequencing within instruction interpretive routines is a direct extension of the foregoing discussion on sequencing between them. The additional material to be discussed is related to physical timing of a system. It is important to introduce the student to the notion of a register state transition (internal cycle) as being a fundamental quantum of timing in the system. Concepts such as I and E cycles, the general decoding process, control points and data paths, as well as simple and iterated execution cycles (multiply, translate, etc.), should be discussed. Hardware decoders involving rings, counters, and logic blocks should be introduced and a discussion of microprogramming should follow. General references: [BRO69, Ch. 8; KNU68, Sec. 1.4.3; CHU72; ST075, Ch. 10].

Introduction to Interpretation (1/2 Hour) [KNU68, Sec. 1.4.3; BEJ73] Sequencing and execution of interpretive routines

Sequencing Between Instructions (2 Hours) Sequence Determined by Instruction Action In-line. Explicit control. IBM 650 Sequence Determined by Instruction and Result Data Conditions and testing. IBM S/360, DEC PDP-11, IBM 7094

Branching action.

Hardware-software implementations of conitrol structures: IBM 7094-FORTRAN, Burroughs B5500,

Sequence Determined by External Signals-Interrupts IBM S/360, DEC

PDP-1,1, DEC PDP-8, CDC 6600. [CHU72] Types. Priority and levels. Methods of handling.

Sequencing Within Instructions, Execution, and Microprogramming (31/2 Hours) [RO169; CHU72; ST075, Ch. 10;

IBB721

The student must fully understand the basics of instruction fetching, decoding, and execution and be able to time out the interpretation of an instruction in a simple machine.

Concepts [FLY67] Cycle-as a state transition in a finite state machine. Data paths and control points. Control timing and data path timing. Control finite state machines. Execution finite state machines. Decode of an operation.

Gating descriptions.

Sequencing. Execution. I and E cycles. [LOR72; AND67]

Simple- execution. Iterated execution cycles (e.g., MULTIPLY, TRANSLATE).

Concurrent execution. [TOM67; THO701

Implementation [WIK53; R0169; HUS70] Hardwired. [GSC67, Ch. 8; R0169] Timing rings, counters, and decode logic. Microprogramming. [ROI69; HUS70; TEC71; TEC74; CHU72; DAV72; FUR74; ST075, Ch. 10; TUC67] The subject of microprogramming, although strictly speaking an implementation topic, has had much greater significance in computer architecture over the past ten years than a narrow view of implementation would have admitted. Rosin [ROI74] credits this to the notion that "microprogramming is the implementation of hopefully reasonable systems through interpretation or unreasonable machines." This point should be discussed in terms of how well computer systems have met their users' needs. Read only storage. [HUS70] Emulation. [ROI69; TUC65; WEB67J Read-write microstorage. [WIL72a] Contemporary microprogrammed processors: Burroughs B1700, Nanodata QM-1, Data Saab

FCPU.

MU5-ALGOL. [LIN68]

Modification of instruction sequence. Methods of address generation for branch target: relative, skip, absolute, etc. Meta Instructions Univac

[BRO60]

50

1108-REPEAT,

IBM

S/360-EXECUTE.

Module 5- Memory Hierarchies (8 Hours) This module deals with the architecture and structure of the memory system. The fundamental reason for using memory hierarchies in computer systems is to reduce the system cost. Computer architects must balance the system cost savings accruing from a memory hierarchy against the COMPUTER

system performance degradation sometimes caused by the hierarchy. The architecture of a memory hierarchy defines the logical memory structure available to a program (process). There is a strong interaction between this structure and the design of an operating system for a machine.

Properties of Memory Reference Patterns (1 Hour) An effective analysis or design of a memory hierarchy requires an understanding of the dynamic behavior of a program in execution. For the purposes of memory hierarchy analysis, it is useful to abstract the execution of a process to derive the "reference string" from an executing program. The reference string is simply the ordered sequence of memory references made by the process. The properties of the reference string have a significant impact on the performance of the memory hierarchy. The most important property of real reference strings is their locality-the tendency for almost all references to be directed to a limited region of the address space. General references: [BEY66; COF68; BRA68; SIS69; MAT70; JOS70; SAL74a]. Memory Components (4 Hours)

Overview of the Memory Hierarchy The memory hierarchy includes cache memory, main memory, on-line secondary storage units such as drum and disk, and bulk and off-line storage such as a magnetic tape library. The primary parameters of a memory hierarchycapacity, access time, and bandwidth at each level of the hierarchy-are often the most important determinants of a computer system's performance. Therefore, it is not surprising that the readings dealing with memory hierarchies are largely concerned with performance. General references: [KUC70; BEL71, Ch. 3; ANC69; ST075, Ch. 5]. Cache Memories and Other High-Speed Memory Buffers These memory buffers are an important implementation technique that has a major impact on the performance of central processors. They form a level in the memory hierarchy that is between the main memory and the processor. This level differs from the other levels (i.e., main, secondary, and bulk storage) in the important respect that it is not visible nor available for direct manipulation by the programmer. Instruction Buffers. [THO70; AND67] Cache Memories. [KIL62; GIB67; LIP68; COT69; MEA70; KAP72; BEJ74] Main Storage [THO70, Ch. 4; BOL67] Name space vs. real memory space size. Marketing considerations in specifying maximum memory capacities for various IBM S/360 models.

[BEL71, Ch. 44]

Bandwidth. Low order interleaving. [BOL67; BUR70] Memory reconfiguration. . High order interleaving. Univac 1108

December 1975

Secondary Storage Extended main storage. [THO70, Ch. 4; BOL671

Fixed head disk or drum. [COF73, Sec. 5.3; FUR75] IBM 2305 Drum Storage-[IBM23] Moving head disk. [COF73, Sec. 5.4; TEO721 IBM 2314 Direct Access Storage Facility. [IBM24] IBM 3830 Storage Control and 3330 Disk Storage,

[IBM33]

Mass Storage [DAM68; HOA72; JOH75J IBM 3850 Mass Storage System. [IBM38]

Address Translation Mechanism (3 Hours) One of the most significant developments in computer architecture has been the distinction between the virtual address space (or name space) of the processor and the physical address space of memory. A range of mechanisms have been developed for mapping one to the other. The following references discuss the more important ones. General references: [KIL62; ARD66; RAN68; DEG70]. Base Register Relocation Single. CDC 6600 (THO70, Ch. 4] Double. Univac 1108

Paging IBM S/370. [KIL62; JOS70; SAL74]

Segmentation Burroughs B5500/B6500. [DEN65; HAU681 Implementation of Dynamic Address (DAL68; LAV71; IBM70; IBM68]

Translations.

Virtual Machines. (GOL73]

Module 6 - Protection Mechanisms and Hardware Aids to Supervis'ion (4 Hours) Prerequisite: Module 5 Modern computer systems are often designed for shared use of their resources by several concurrently executing processes (program jobs). The most vital protection mechanism is one designed to ensure that no job's execution can possibly interfere with the information used by any other job. This storage protection is, however, only one important aspect of a general class of supervision functions concerned with signaling, response, and assignment activities required for efficient computer resource allocation and acceptable response times. A judicious combination of software and hardware is used to implement supervision functions. Hardware is needed for sequences that occur with high frequency. This module and Module 5 are the areas of greatest interaction between computer architecture and the principles of operating

systems.

51

General Discussion of Protection and Supervision (1/2 Hour) General references: [DEG71; HEL73; NEE72] Motivations for Shared Use of Storage and Processor.

Timesharing of the CPU. [WIK72]

Module 7 - Specialized Processors (5 Hours) A number of functionally specialized processors have been developed. These processors are defined primarily by the data types which they can process. They do not interpret general programming languages. This module deals with some of the more common specialized processors.

Space-Sharing of Main Storage Register and stored key protection.

Read/write protection.

Interprocess Communication (2 Hours) General references: [LAM69; HEL73; HAN73; ORG73] Interrupt Principles Saving and restoring system states. RCA Spectra 70 had four operating states: program, executive, interrupt, and machine; whereas the IBM System/360 has only two, program and supervisor. CDC 6600 exchange jump. Interrupt Signaling Categories Clock (timer), I/O condition, address violation, operation invalidity, external signals, explicit program call, etc.

Semaphores. [DIJ68]

Privileged Mode (1/2 Hour) General references: [CLA64; HEL73; IBM70]. Storage Protection

Input/Output Processors (2 Hours) An input/output processor specializes in the management of peripherals. It controls the details of transmission of information between secondary memories or terninals and main inemory. An input/output processor does not usually alte; information; it is merely an interpreter for moving information. Computational capability is only required if recoding and reformatting of information is necessary, or if operations are to be carried out between second memories without central processor intervention. General reference: [ST075, Ch. 6]. Copy Logic, Buffers and Direct Memory Access Capability DEC PDP-8, HP2100, DEC PDP-11. [GSC67, Sec. 8.4] Channels IBM 1800 Special Data Channels. [BEL7 1, Ch. 33] IBM 7607 and 7909 Data Channels. [BEL71, Ch. 41] Selector and Byte Multiplexer Channels. [PAD64] Block Multiplexer Channel. [BRZ72]

Peripheral Processors CDC 6600 PPUs. [THO70, Ch. 7 and 8] CDC 7600 PPU's. [CDC76, Ch. 5] Univac 1108 I/O Processor.

Interrupt Handling

Mode-Change Mechanisms

Hardware-Operating System-Problem Program Interactions Virtual Memory Mechanisms for Protection (1 Hour) General references: [DEN66; DAL68; ORG72; NEE72; SCH72; IBM701.

Typical Major Examples -to Illustrate Module Topics Although almost every system has its distinct features, the following can illustrate most principles and many variations found in actual practice. The asterisks denote virtual storage systems. CDC 6600 DEC PDP-I 1 DEC PDP-10 IBM System/360

Burroughs B5500/B6500* [ORG73]

IBM System/370* Multics* [DAL68; ORG72; SAL74b] 52

Microprocessors and Microprocessor Applications (2 Hours) Over the 30 years in which computers have existed, several thousand species of machines have been built by a variety of organizations for a variety of functions. The implementations of these machines were based on available semiconductor and magnetic technologies. Currently, semiconductor technology is such- that a small stored program processor can be fabricated on a single silicon die. These processor-on-a-chip devices, when executing a fixed program, form the basis for hand-held calculators, appliance and automotive controllers, and simple terminals. They also form the basis for many programmable products: point-of-sales terminals, instruments, factory data collection terminals, display terminals, etc. The important aspect of nearly zero cost processoron-a-chip computers is that they will be applied on a wide scale in nearly all man-made objects. Though these computers are revolutionary in functional ability, their architectural development has been strictly evolutionary. All of the topics discussed in this report are relevant to their design. General references: [COM74a; COM74b; LAP72; HOT74].

COMPUTER

Terminal Computers Terminals of this type include CRT-keyboards v uses range from programming to order entry, point-of factory data collection, communications control, etc.

Calculators [BEL71, Ch. 20; STO75, Ch. 3] Electronic calculators (especially the hand-held vers iions) are excellent examples of specialized processors. The y are characterized by decimal rather than binary arithl metic units, a spartan simplicity dictated by strict price constraints, and a very primitive I/O system.

Display Processors (1 Hour) A display processor is a complex system that manipulates information for display terminals. It must perform a substantial number of local operations on a sset of specialized data types which are representations of connplex graphical objects. These representations typically in clude character strings, points and vectors to be displayed and control structures which define pictures. General references: [WAT69; NEW74; BEL71, Ch. 25].

structures will be based on communications links with processes being assigned to specific processors on a functional basis.

Multiprocessor Computers (2 Hours) General references: [BEL7 1, Part 5; HEL73; ENS74]. Systems:

Burroughs D825. [BEL71, Ch. 36]

Burroughs Interpreter. [DAS72] Carnegie-Mellon University C.mmp. [WUL72] Bolt, Beranek and Newman. [HEA731 Univac 1108. [STN67] IBM System/370 Model 168 MP. [MAC741

Switching and Interconnection Structure.

DAS72]

[BLA64b;

Performance as a Function of the Number of Processors.

[LEH66;WUL72] Sharing and Resource Contention. [SK169]

Reliability.

Module 8 - Multiple Computers (4 Hours) Various forms of multiple computers have been desiigned as a means of (1) increasing the reliability and impr4 oving the performance of computer systems, and (2) distrib ,uting computing according to physical location needs to re-duce communication link costs. Two standard forms areE the multiprocessor computer (which consists of two or more processors that share a common memory) and geog raphically distributed computer networks (which are usui ally a

collection of physically separated computers). Multiprocessor computers which share the same ph3ysical memory and addressing space but have only a few processors have existed for some time. Systems are now being built with a large number of processors, th4 ough. Although some of the multiprocessor's problems are sitill in the research domain, the system designer must be awaire of the issues of reliability and performance (e.g., conflicts;arise when multiple processors access a common resource ) and the mechanisms for intercommunication which permiit the processors to share common resources. Understanding computer networks requires an u nderstanding of their constituent components (the iinterconnection links, the computers, and their oper*ating systems) and the tasks which are to be distributed armong them. Computer network analysis is similar to the an;alysis of other networks in which multicommodities are transferred among links and nodes on a dynamic Ibasis. Many of the studies that have been carried out tfor telephone communication (especially switching) apply. Finally, there are ad hoc, tightly coupled comlputer structures which are neither interconnected via staradard communications links nor share the same mennory. Examples of these structures include IBM's Attaiched Support Processor system, communications front ends ,and specialized ffle, array, and display processors. The advent of microprocessors clearly forces the growth of various multiple computer structures. The sir iplest December 1975

Computer Networks (2 Hours) General references: [BEL71, Ch. 40; IEEE73; COM73; BEL74].

Structures'and Analysis [ROB70;FRA71;0RN72] Communication Links and Message. [MAR72] Facilities and Use. [ROB73; KLE74] Module 9 - Performance Evaluation (9 Hours) Prerequisites: Modules 2, 3, 5, and 6, plus a basic course in probability. [FEL68]

The performance evaluation of a computer system consists of deriving indices of its quality, such as speeds, storage capacities, and efficiencies of resource use. This assessment requires an understanding of the purposes the system is to serve as well as the hardware and software components that constitute it. These purposes are given explicit definition in the selection and representation of workloads and performance indicators. Performance evaluation is frequently concerned with more than just producing the values of a few performance indicators such as bandwidth, throughput,.response time, and resource utilization for a given configuration. It must determine the dependence of these indicators on various parameters of the system so as to help designers choose among a rather large collection of alternative configurations and options in their efforts to meet user's specifications. Different types of performance studies (e.g., different levels of detafl) are appropriate to various classes of computer professionals such as architects, hardware and software engineers, installation managers, system programmers, problem programmers, etc. Despite the different 53

needs of these groups, they all use the same basic classes of evaluation tools: (1) mathematical analysis, (2) simulation techniques, and (3) measurement. All of these are introduced in this module in various contexts, and some time should be spent comparing their strengths and weaknesses. General references: [CAL67; SM168; LUC71; BEL71, Ch. 3; FRE72; DRU73; HEL75; ST075, Ch. 1 1].

Main Storage I/O Devices and Subsystems. [HEL70] Disk and Drum. [TE072; FUR75]

Printer.

Nature of Computer Performance Evaluation.

Computing System Performance (3 Hours) [HEL75] The references cited for system studies are only suggestions. Actual studies may involve components, subsystems, or systems. Batch Systems.

Evaluation Classes (Hardware, Software, Systems).

Multiprogramming Systems. [ONE67; CAN68; STU7 1]

Definition of Performance Measures such as Bandwidth, Throughput, Response Time, Resource Utilization, etc.

Timesharing Systems. [SCE67; MCK69; DOH70; BAD71; NIE71; SHE72]

Measurement Techniques. Hardware. [ROE69; BON69; DRU73; IBM70 (Program Event Recording)] Software. [CAM68; CHN69; SED70; BAD71; LUC71]

Virtual Memory Systems. [SAL70; ORG72; SCE73; HEL75]

Overview (1 /2Hours)

Introduction to Techniques of Analysis (21/2 Hours) Elementary Queueing Theory When the information necessary to evaluate a computer system's performance exceeds the values of simple parameters of the hardware structure, performance evaluation must address the underlying stochastic nature of operating a computer system. Requests for service arriving at processors within a computer system often can only be modeled as a random process. References: [KLE75, Ch. 3-4; ST075, Ch. 1 1; HEL75, Ch. 5]. Simulation Theory There are instances when a more detailed analysis of system behavior is needed than can be obtained from queueing models, and instances when a system to be analyzed cannot be adequately approximated by known analytical methods. In these cases, simulation techniques are the most appropriate tools available to the analyst.

References: [NIE67; MCD68; GOR69].

Workload Selection and Characterization (1 Hour) [FER72;

WIN73]

Total System Load. [FRM68; WAL67]

Benchmarks. Synthetic Workloads. [BUC69; SRE74]

Components and Subsystems Performance (1 Hour) [DRU73; HEL75] Central Processor. [MUR70; BEL71, Ch. 3; S0L66] Kernels. [CAL67] Mixes. [RA164; GIS70] 54

Module 10 - Reliability (5 Hours) Reliability affects everyone connected with computer systems, from machine designer to end user. As more complex systems are designed and fabricated, their designers must exercise greater care during design in order to ensure that the systems they develop operate with an acceptable level of reliability. The material in this module helps the student to understand and determine various reliability parameters of a system, given knowledge of its constituent parts, and to design (or configure) systems for increased reliability. Basic Measures and Calculations (2 Hours) Attempts to evaluate a computer system quantitatively require an understanding of the fundamental measures of reliability (e.g., mean-time-to-failure, mean-time-to-repair, expected-system lifetime). In addition, there are a few elementary computations that are useful when attempting to estimate system reliability. General references: [ESA62; BOU71; MAH71; HEL73, pp. 443-452]. Codes for Error Detection and Error Correction (1 Hour) An essential basis for any computer system that must operate with a high degree of reliability is an error detection, and possibly an error correction, scheme for transmission and storage of data. In memory systems, redundant error detection and/or correction information is held in the memory. Different codes are often required for distinct levels in the memory hierarchy, and each memory technology may impose different demands on its code. Similarly, communication links are not error-free, and thus additional information must be transmitted with a message to ensure its integrity. Another area in which error detection and correction plays an important part is the use of arithmetic codes for the detection and correction of errors in. the results produced by arithmetic operations. General references: [HIL68, Ch. 8; AVI71b;-PET72; RA074].

COMPUTER

Module 11 -System Design Evaluation (6 Hours)

Diagnostic Procedures (1 Hour) Diagnostic procedures are the set of programs that exercise each of the components of a computer system to validate that it is working correctly or that help isolate the component that is failing. The frequency with which diagnostic procedures are unable to detect failures when a system is known to be malfunctioning underscores the need to discuss the principles of testing. The student should comprehend the impossibility of exhaustive testing, the need to understand the structure as well as the function of the component under test, and the concept of "boot$trapping" diagnostics-i.e., validating a small "core" of hardware and then using the core to test the remaining facilities. General references: [BAT70; CHA70; JON7 1].

System Reliability and Serviceability (2 Hours) As computer systems continue to be applied to an increasing variety of real-time environments, stringent demands are made on the computer system's availability and serviceability. The increasing complexity of large computer systems also requires the inclusion of more sophisticated machine-checking capabilities. General references: [CAR64; FOX75; ORN75]. Machine Checking Techniques. Error Logging and Recovery. Fault Tolerant Techniques. [AVI71a].

Introduction To appreciate how the architectures of computer systems develop, one must analyze complete systems. Since formal techniques for the analysis of these systems do not yet exist, there is no substitute for studying some existing systems closely. The purpose in doing this is to try to deduce the reasons for various design decisions and to see how design decisions in some aspects affect those in others. Moreover, these studies provide the opportunity to compare the techniques adopted by different systems for solving fundamental problems. The instructor may prefer to introduce such studies gradually throughout the course of study rather than treating them as a comparative analysis at the end. The subject matter to be covered is best represented by a matrix of systems and concepts (Figure 1). The horizontal dimension compares different techniques for solving the same fundamental problems, and the vertical dimension shows how solving one of the problems in a particular way constrains the solution of other problems. Each of these dimensions is to be evaluated in as quantitative a manner as possible. Two points are to be stressed here: environment and technology. The first is dealt with because it is imperative that the student develop an understanding of the user environments for which these systems were actually intended. By environment we mean the complete set of users' specifications: the functional capabilities that were

COMPUTER SYSTEMS Large Systems

Medium Systems

Minicomputers

Microcomputers

Data Representation

Instruction and Addressing Interpretation Memory Hierarchy

0.E Protection Mechanisms and Hardware Aids 0~ to Supervision

Input/Output Facilities for

Multiprocessing

Reliability Performance

Figure 1.. System design evaluation matrix

December 1975

55

expected, the relative cost of the system (relative to others of its day) [SHA69], the language processors and operating systems that were expected, and the reliability of the system in its environment. The second is addressed because it is impossible to compare systems without considering their technological base. The instructor should normalize these considerations whenever possible, but also call attention to them when they represent technical constraints in the system designer's environment. For example, the availability of different memory elements and the relative cost of circuits frequently affect architectural decisions.

George E. Rossmann is on the staff of Palyn Associates, where he has been involved with the

design and evaluation of medium and large scale processors, the design and evaluation of memory hierarchies, and the evaluation of soft nmachine architectures. He has worked for IBM in the areas of advanced technology, circuit design, and large systems architecture. From 1971-1973 he was an assistant professor at the

WN,

~ University of Delaware. He received the BS degree in electrical engineering from Lafayette College, the MS from Penn State University, and the Ph.D from Syracuse University. Dr. Rossman served as chairman of the Workshop on Education and Computer Architecture in 1973. He has published a number of papers in technical journals and holds one patent.

K_

Computer Systems The systems selected for comparison should include an interesting disparity of environments as well as some similarity. The selection must be influenced, of course, by the availability of reference materials and the students' and instructor's familiarity with specific systems. Here are some suggestions.

C. Gordon Bell is vice president of engineering for Digital Equipment Corporation. On leave as professor of electrical engineering and computer science at Carnegie-Mellon University, he was previously manager of Computer Design for Digital from 1960-1966. During that time he was responsible for DEC's PDP-4, -5, and -6 computers. He consulted for DEC in 1966-1972 while working at CMU on various computers and products including the

Large Systems a. IBM System/360 and System/370 in general and System/370 Model 158 [IBM581 or Model 168 [IBM68] in particular. b. DEC PDP-10. c. CDC 6600. d. Burroughs B6500. e. Univac 1108.

PDP-1 1. His work in the computer field covers computer architecture, modularity of design, multiprocessors, and applications. His publications include Computer Structures (McGraw Hill) and Designing Computers and Digital Systems (Digital Press) and several papers. In addition to his industrial interests, Bell has served as a member of three COSINE committees of the National Academy of Sciences on computer engineering education, and has served the National Science Foundation, Office of Computing Activities. He is a department editor for CACM, and is a Fellow of the IEEE.

Medium Systems a. Burroughs B1700. b. IBM System/370 Model 145 [IBM451. c. DEC PDP-1 1/45. d. Honeywell Series/60 level 64.

Frederick P. Brooks, Jr. is Kenan professor and chairman of the Computer Science Department at the University of North Carolina in Chapel HilL He is best known as the "father of the IBM System/360," having served as project manager for its development and later as manager of the Operating System/360 software project during its design phase. Earlier, he was an architect of _1 _ the IBM Stretch and Harvest computers. At Chapel Hill, Dr. Brooks has participated in the establishment and guiding of the Triangle Universities Computation Center and the North Carolina Educational Computing Service. He has published Automatic Data Processing, the System/360 Edition of Automatic Data Processing, and chapters in several other books. His most recent work is The Mythical Man-Month: Essays on Software Engineering.

Minicomputer Systems a. DEC PDP-8. b. HP2100andHP21MX. c. Microdata 1600. d. Data General Nova. e. IBM System/32.

Microcomputer systems a. Intel 8080. b. National IMP- 16.

Acknowledgements The committee would like to express its appreciation to Professor E. J. McCluskey of Stanford University, who was instrumental in establishing the task force, and to the distinguished group of computer architects who served as referees for this report. Their constructive comments were extremely influential in the preparation of the final version of this report. The committee would also like to thank Ms. Patricia Stoaks of Palyn Associates who typed all the drafts of this report. o 56

a

_

Michael J. Flynn is a founder and vice-president of Palyn Associates and is now the senior -5 consultant for the corporation. He is also a professor of electrical engineering at Stanford University. He joined IBM in 1955 and, over a 10-year }ui 7 _ tenure there, worked in the areas of circuit development and computer organization and design. At IBM he was a designer and manager of prototype versions of the IBM 7090 and 709011. Later, as manager, he was responsible for design and development of the 360 Model 91 Central Processor. Dr. Flynn joined the faculty of Northwestern University in 1966 and later was professor of computer science at The Johns Hopkins

University. A vice-president of the IEEE Computer Society, Flynn has

served as chairman of the IEEE Technical Committee on Computer Architecture and as associate editor of the IEEE Transactions on Computers He has published over thirty papers in technical journals and holds two patents. He received his BSEE from Manhattan College, his MSEE from Syracuse University, and his PhID from Purdue University.

COMPUTER

Samuel H. Fuller is an associate professor of computer science and electrical engineering at Carnegie-Mellon

University.

His

research

interests include topics in computer architecture

and

the

evaluation

performance

of'

computer systems.

He is currently involved in the measurement and evaluation of C.mmp, a

multi-miniprocessor computer system, and the design of new multiprocessors based on the j g ll emerging microcomputer technology. XQ S Dr. Fuller received the BSE degree in electrical engineering from the University of Michigan in 1968, the MS and PhLD degrees from Stanford University in 1969 and 1972, respectively. He is the author of Analysis of Drum and Disk Storage Units (Springer-Verlag), and a co-author of Introduction to Computer Architecture (SRA). Dr. Fuller is an editor of the Computer Systems Department of CACM and is a member of the ACM and the IEEE Computer Society. He is also a member of Tau Beta Pi, Sigma Xi, Phi Kappa Phi, and Eta Kappa Nu. Herbert State

since

HeUerman

Earlier,

engineering faculties

he at

served

We have tried to identify a minimum set of references which, in our opinion, represent the best path through the material in the course of study. These references have been marked with asterisks. The remairiing references have been selected because they simplify and broaden the path established by the first set. [ACM68] "Curriculum 68," CACM, 11, 3, March 1968: 151-197.

at

on

Binghamton

the electrical

Syracuse University and

the University of Delaware. Dr.

Hellerman

Amdahl, G. M., G. A. Blaauw, and F. P. Brooks, "Architecture of the IBM System/360," IBM Journal of R&D, 8, 2, April 1964: pp. 87-101.

[ANA73] Anagnostopoulos, P., G. M. Stabler, and A.

van Dam, "Computer Architecture and Instruction Set Design," AFIPS Proc. NCC, 42,1973: pp. 519-529.

[ANC691

Anacker, W., and C. P. Wang, "Evaluation of Computing Systems With Memory Hierarchies," IEEE Trans. on Computers, EC-16, 6, Dec. 1967: pp. 764-773.

was

System Divisions for 10 years where he

with the IBM Yorktown Research and

Development worked on the architecture and performance of multiprogrammed, timeshared, and multiprocessor systems. He is the author of several books. His current computer work centers on hardware/software performance, operating systems and computer system education. He received his undergraduate degree at Purdue University and the Ph.D from Syracuse University.

*[AND671

Anderson, D. W., F. J. Sparacio and R. M. Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling," IBM Journal of R&D, 11, 1, January 1967: pp. 8-24.

*[ARD66] Arden, B. W., B. A. Galler, T. C. O'Brien and F. H. Westervelt, "Program and Addressing Structure in a Time Sharing Environment," JACM, 13, 1, Jan. 1966: pp. 1-16.

activation record

DO YOU SPEAK OUR LANGUAGE?

block structured coercion

display extensible flow analysis garbage collection halting problem infix operator Jensen's device keyword LR(k) grammar meta-language non-terminal optimization

parse

tree

quadratic rehash recursive descent semantics

TWS up-level VDL Warshall's algorithm XPL yo-yo list zero address December 1975 'December

pp.

*[AMD641

professor at the

has been a

University of New York 1969.

Bibliography

Intel Corporation, the world's foremost microcomputer manufacturer, has a unique commitment to high-level programming languages. We believe that the microcomputer revolution provides a singular opportunity to introduce the tools of modern programming to

a

vast,

new

generation

of users and programmers. Tools for building the diverse applications of microcomputing power in the decade to

come.

new tools, we need people with exceptional skill and ingenuity. People thoroughly familar with the concepts of modern programming languages and the design of state-ofthe-art compilers.

To build these

Applicants should have

an

MS

or

PhD in

computer science, or equivalent background in language and compiler

design. For immediate consideration, please contact Professional Employment, Intel Corporation, 3065 Bowers Avenue, Santa Clara, CA 95051. An Equal Opportunity Employer M/F. 57

57

Atkinson, *[ATK741 Honeywell

T., "Architecture of Series/60 Level 64," Computer Journal, 8, July 1974: pp. 94-106.

*[AVI71aJ

Avizienis, A., et. aL, "The STAR (Self Testing and Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design," IEEE Trans. on Computers, C-20, 11, Nov. 1971: pp. 1312-1321.

[AVI71bJ Avizienis, A., "Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design," IEEE Trans. on Computers, C-20, 11, Nov. 1971: pp. 1322-1330.

[BAD711

Bard, Y., "Performance Criteria and Measurement for a Time Sharing System," IBM Systems Journal, 10, 3, 1971: pp. 193-217.

*[BAN681 Barnes, G. H., R. M. Brown, M. Kato, D. J. Kuck, D. L.

Slotnick and R. A. Stokes, "The ILLIAC IV Computer," IEEE Trans on Computers, C-17, 8, -Aug. 1968: pp. 746-757. Reprinted in [BEL71].

[BOU711 Bouricius,

W. G., W. C. Carter, D. C. Jessep, P. R. Schneider and A. B. Wadia, "Reliability Modeling for Fault Tolerant Computers," IEEE Trans. on Computers, C-20, 17, Nov. 1971: pp. 1306-1312.

[BRA681 Brawn, B., and F. Gustavson, "Program Behavior Paging Environment," AFIPS Proc. FJCC, 33, 1968: 1019-1032.

in a pp.

[BRE731 Brent, R. P., "On the Precision Obtainable with Various Floating Point Number Systems," IEEE Trans. on Computers, C-22, 6, June 1973: pp. 601-607. [BRO60] Brooks, F. P., "The EXECUTE Operation:

A Fourth Mode of Instruction Sequencing," CACM, 3, 3, March 1960: pp.

168-170.

[BRO63] Brooks, F. P., "Recent Developments in Computer Organization," Advances in Electronics, 18, 1963: pp. 45-65.

[BRO69] Brooks, F. P. and K. E. Iverson, Automatic Data Processing, System/360 Edition, Wiley, 1969.

[BAR611 Barton,

[BRW691 Brown, N.

*[BAR69] Barton, R. S., "Ideas for Computer Systems

*[BRZ721 Brown, D., R. Eibsen and C. Thorn, "Channel and Direct

R. S., "A New Approach to the Functional Design of a Digital Computer," AFIPS Proc. WJCC, 19, 1961: pp. 393-396.

Organization," Software Engineering, COINS III, VoL 1, Julius

Tou, Ed., Academic Press, 1970.

[BAT701

Bartow, N. and R. McGuire, "System/360 Model 85 Microdiagnostics,"AFIPSProc. SJCC, 36, 1970: pp. 191-197.

[BEJ731

Bell, J. R., "Threaded Code," CACM, 16, 6, June 1973: pp. 370-372.

[BEJ74J Bell, J. R., D. Casasent and C. G. Bell, "An Investigation of Alternative Cache Organizations," IEEE Trans. on Computers, C-23, 4, April 1974: pp. 346-351. * [BEL701 Bell, C. G., R. Cady, H. McFarland, B. Delagi, J. O'Laughlin, R. Noonan and W. Wulf, "A New Architecture for Minicomputers-the DEC PDP-11," AFIPS Proc. SJCC, 36, 1970: pp. 657-675.

*[BEL71] Bell,

C. G., and A. Newell, Computer Structures: Readings and Examples, McGraw Hill, 1971.

* [BEL74] Bell, C. G., "More Power Spectrum, Feb. 1974: pp. 40-45.

by Networking," IEEE

[BER711 Berkling, K.,

"A Computing Machine Based on Tree Structures," IEEE Trans. on Computers, C-20, 4, April 1971: pp. 404-418.

* [BEY66] Belady, L. A., "A Study of Replacement Algorithms for a Virtual Storage Computer," IBM Systems Journal, 5, 2, 1966: pp. 78-101.

[BLA591 Blaauw, G. A., "Indexing and Control Word Techniques," IBM Journal of R&D, 3, 2, July 1959: pp. 288-301. Reprinted in [BUC621.

*[BLA64a]

Blaauw, G. A., and F. P. Brooks, Jr., "The Structure of System/360, Part 1-Outline of the Logical Structure," IBM Systems Journal, 3, 2, 1964: pp. 119-135. Reprinted in [BEL71].

[BLA64b] Blaauw, G. A., "The Structure of System/360, Part 5-Multisystem Organization," IBM Systems Journal, 3, 2, 1964: pp. 181-195.

[BOL67] Boland, L. J., G. D. Granito, et. aL, "Storage System," IBM Journal of R&D, 11, 1, Jan. 1967: pp. 54-68.

[BON69] Bonner, A. J., "Using System Monitor Output to Improve Performance," IBM Systems Journal, 8, 4', 1969: pp. 290-299.

58

S. and P. L. Richman, "The Choice of Base,"

CACM, 12, 10, Oct. 1969: pp. 560-562.

Device Architecture," IBM Systems Journal, 11, 3, 1972: pp. 186-200.

*[BUC62J Buchholz, W., Planning Hill, 1962.

a Computer System, McGraw

[BUC691 Buchholz, W.,

"A Synthetic Job for Measuring System Performance," IBM Systems Journal, 8, 4, 1969: pp. 309-3 18. [BUG17] Burroughs Corp., Burroughs Bi 700 Systems Reference Manual, Pub. No. 1057155, Burroughs Corporation, Detroit, Michigan.

[BUG55] Burroughs Corp., Burroughs BSS00 Info. Processing Systems Ref. Manual, Pub. No. 1021326, Burroughs Corporation, Detroit, Michigan.

[BUG651 Burroughs Corp., Burroughs

B6500 Info. Processing Systems Ref Manual, Pub. No. 1043676, Burroughs Corporation, Detroit, Michigan.

[BUR70] Burnett, G. J., and E. G. Coffman, Jr., "A Study of Interleaved Memory System," AFIPS Proc. SJCC, 36, 1970: pp. 467-474.

* [CAL671 Callingaert, P., "System Performance Evaluation-Survey and Appraisal," CACM, 10, 1, Jan. 1967: pp. 12-18.

[CAM681 Campbell,

D. J. and W. J. Heffner, "Measurement and

Analysis of Large Operating Systems During Systems Development," AFIPSProc. FJCC, 33, Part 1, 1968: pp. 903-914.

[CAN681 Cantrell, H. N., and A. L. Ellison, "Multiprogramming System Performance Measurement and Analysis," -AFIPS Proc. SJCC, 32, 1968: pp. 21 3-221. [CAR64] Carter, W. C., et al, "Design of Serviceability Features for the IBM System/360," IBM Journal of R&D, 8, 2, April 1964: pp. 115-126.

[CDCOO] Control Data Corp., Control Data STAR-100 Computer Systems Reference Manual, Pub. No. 60256000, Control Data Corp., Arden Hills, Minn.

[CDC66] Control Data Corp., Control Data 6600 Computer System Reference Manual, Pub. No. 60100060, Control Data Corp., Arden Hills, Minn.

[CDC76] Control Data Corp., Control Data 7600 Computer System Reference Manual, Pvb. No. 60258200, Control Data Corp., Arden Hills, Minn.

COMPUTER

[CHA70] Chang, H. Y., E. G. Manning and G. Metze, Fault Diagnosis of Digital Systems, Wiley, 1970.

[CHN69]

Cheng, P. S., "Trace Driven System Modeling," IBM Systems Journal, 8, 4, 1969: pp. 280-289.

[CHU62] Chu, Y., Digital Computer Design Fundamentals, McGraw Hill, 1962. * [CHU72]

Chu, Y., Computer Organization and Microprogramming, Prentice HalL 1972.

00

-

( IM:p i

t Remington gives you:

[CLA64] Clayton, B. B., F. K. Dorff and R. Fagen, "An Operating System and Programming System for the 6600," AFIPS Proc. FJCC, 26, 1964: pp. 41-57.

P/M performance with a new twist.

P/M parts of Remington's astounding HD-3050 steel are so ductile you can bend them around a corner. Or even tie them in a knot. Send for a sample and try for v yourself.

[COF68] Coffman, E. G., and L. C. Varian, "Further Experimental Data on the Behavior of Programs in a Paging Environment," CACM, 11, 7, July 1968: pp. 471-475.

[COF73] Coffman, E. G., and P. J. Denning, Operating System Theory, Prentice Hall, 1973. and Dynamic Numerical Characteristics of Floating Point Addition," IEEE Trans. on Computers, C-22, 6, June 1973: pp. 598-601.

[COD73] Cody, W. J., "Static

P/M magnetic alloys with pull in the right places.

[COM73] Computer, August 1973. Computer Networks.

Very high densities and sintering at ultra-high temperatures, in the driest atmospheres, give Remington P/M magnetic parts excellent magnetic properties. In highpurity iron, silicon steel, ferro-nickel alloys and other high-performance materials.

[COM74a] Computer, July 1974. Microprocessor Architecture. [COM74b] Computer, August 1974. Microprocessor Applications. [CON70] Connors, W. D., V. S. Mercer and T. A. Sorlini, "S/360 Instruction Usage Distribution," IBM Tech. Report TROO-2025, IBM Corp., Poughkeepsie, New York, May 1970.

[COS681 COSINE Task Force Report II, "An Undergraduate Electrical Engineering Course on Computer Organization," National Academy of Engineering, Washington, D. C., Oct. 1968.

P/M stainless steel with strength to spare.

COSINE Task Force Report VIII, "An Undergraduate Course on Operating Systems Principles," National Academy of Engineering, Washington, D. C., June 1971. Reprinted in Computer, 5, 1, Jan. 1972: pp. 40-60.

*[COS711

Many companies can make these shapes in 316L stainless steel. But that's not enough. Remington R&D has come up with the sophisticated processing and special equipment to give P/M stainless steel parts superior tensile strength, ductility and impact resistance.

*[COT69] Conti,

C. J., "Concepts for Buffer Storage," Computer Group News, 2, 3, March 1969: pp. 9-13.

Creech, B. A., "Architecture of the B-65 00," Software *[CRE70] Engineering, COINS III, VoL 1, Julius Tou (ed.), Academic Press, 1970.

And P/M parts that stand up to shock and stress.

[DAL68] Daly, R. C., and J. B. Dennis, "Virtual Memory, Processes and Sharing in MULTICS," CACM, 11, 5, May 1968: pp.

306-312.

Our HD-2108 air-hardening steel combines high tensile strength with good elongation. It's an impact-resistant material tough enough to use for impact wrenches, chain saw sprockets and other severe applications.

jDAM68] Damron, S., et al, "A Random Access Terabit Magnetic Memory,"AFIPSProc. FJCC, 33, 1968: pp. 1381-1387.

[DAS72] Davis, R. L, S. Zucker and C. M. Campbel, "A Building Block Approach to Multiprocessing," AFIPS Proc. SJCC, 40, 1972: pp. 685-703. [DAV72] Davies, P. M., "Readings in Microprogramming," IBM Systems Journal, 11, 1, 1972: pp. 16-41.

Not to mention this FREE P/M pocket screwdriver. If you have a P/M parts problem-of any kind-call

[DEC05] Digital Equipment Corp., PDP-1 1/05/10/35/40 Processor Handbook, Digital Equipment Corp., Maynard, Mass.

[DEC8E] Digital Equipment Corp., PDP8/E Processor Handbook, Digital Equipment Corporation, Maynard, Mass.

[DEC10] Digital Equipment Corp., DEC System 10 Assembly Language Handbook, Chap. 1, Ordercode: DEC 10, NRZC-D, Digital Equipment Corp., Maynard, Mass..

December 1975

Reader Service Number 1226

or

write to Remington. We'll send you a good solution and a great pocket screwdriver made with our HD-2108 steel. Remington Arms Company, Inc., Powder Metal Products Division, Ilion, NewYork 13357. (315) 894-8639.

I

L

PiffnMoon., 4m 1%.,

%..P

-

[DEC45] Digital Equipment Corp., PDPI11/45 Processor Handbook, Digital Equipment Corporation, Maynard, Mass.

*[DEG701

Denning, P. J., "Virtual Memory," Computing Surveys, pp. 153-190.

2, 3, Sept 1970:

*[DEG711

Denning, P. J., "Third Generation Computer Systems," Computing Surveys, 3, 4, Dec. 1971: pp. 175-216.

*[DEN651

Dennis, J. B., "Segmentation and the Design of Multiprogrammed Computer Systems," JACM, 12, 4, Oct. 1965: pp. 5 89-602.

[DEN66] Dennis, J. B., and E. C. Van Horn, "Programming Semantics for Multiprogrammed Computations," CACM, 9, 3, March 1966: pp. 143-155.

[DGC71] Data General Corp., How to Use the NOVA Computers, Data General Corp., Southboro, Mass., 1971.

[DIJ681

Dijkstra, E. W., "The Structure of 'THE'Multiprogramming System," CACM, 11, 5, May 1968: pp. 341-347.

[DOH70] Doherty, W. J., "Scheduling TSS/360 ness," AFIPS Proc. FJCC, 37, 1970:

pp.

97-111.

for Responsive-

[DRU731

Drummond, M. E., Evaluation and Measurement Techniques for Digital Computer Systems, Prentice Hall, 1973.

[FRM681 Freeman,

D. N., and R. R. Pearson, "Efficiency vs. Responsiveness in a Multiple Services Computer Facility," ACM National Conf. Proc., 1968: pp. 25-34.

[FUR741 Fuller,

S. H., V. R. Lesser, C. G. Bell and C. Kaman, "Microprogramming and Its Relationship to Emulation and Technology," Proc. 7th Workshop on Microprogramming, Oct 1974: pp. 151-159.

*[FUR751

Fuller, S. H., and F. Baskett, "An Analysis of Drum

Storage Units," JACM, 22, 1, Jan. 1975: pp. 83-105.

[GEA741 Gear,

C. W., Computer Organization and Programming, Second Edition, McGraw Hill, 1974.

[GIB671 Gibson,

D. H., "Considerations in Block Oriented Systems Design," AFIPS Proc. SJCC, 30, 1967: pp. 75-80.

[GIS701 Gibson,

J. D., "The Gibson Mix," IBM Tech. Report TROO.2043, IBM Corp., Poughkeepsie, New York, June 1970.

[GOL73] Goldberg, R. P., "Architecture of Virtual Machines," AFIPS Proc. NCC, 42, 1973: pp. 309-318.

[GOR69] Gordon, G., System Simulation, Prentice Hall, 1969. [GSC67] Gschwind, H. W., Design of Digital Computers, Springer-Verlag, New York, 1967.

[HAN731 Hansen, Hall, 1973.

*[ESA621

Esary, J. D., and F. Proschan, "The Reliability of Coherent Systems," in Redundancy Techniques for Computing Systems, R. Wilcox and W. Mann (eds.), Spartan Books, 1962: pp.

47-61.

*[ENS74] Enslow, P., Multiprocessors and Parallel Processing, Wiley, 1974.

[FAL641

Falkoff, A. D., K. E. Iverson and E. H. Sussenguth, "A Formal Description of System/360," IBM Systems Journal, 3, 3, 1%4: pp. 198-261.

[FEL681

Feller, W., An Introduction to Probability Theory and Its

Applications, Vol. 11, Wiley, 1966.

P. B., Operating Systems Principles, Prentice

* [HAU68]

Hauck, J., and B. Dent, "B6500/B7500 Stack Mechanism," AFIPSProc. SJCC, 32, 1968: pp. 245-25 1.

*[HEA73]

Heart, F. E., S. M. Ornstein, W. R. Crowther and W. B. Barker, "A New Minicomputer/Multiprocessor for the ARPA Network," AFIPS Proc. NCC, 42, 1973: pp. 529-5 37.

[HEL70] Hellerman, H., and H. J. Smith, "Throughput Analysis of Some Idealized Input/Output and Compute Overlap Configurations," Computing Surveys, 2, 2, June 1970: pp. 111-118.

* [HEL731 Hellerman, H., Digital Computer System Principles, McGraw Hill, Second Edition, 1973.

*[HEL751

Hellerman, H., and T. Conroy, Computer System

Performance, McGraw Hill, 1975.

*[FER72]

Ferrari, P., "Workload Characterization and Selection in

Computer Performance Measurements," Computer, 5, 4, July/Aug. 1972: pp. 18-24.

[FEU72] Feustel, E. A.,

"The Rice Research Computer, a Tagged pp. 369-377.

Architecture," Proc. AFIPS SJCC, 40, 1972:

*

[FEU731

Feustel, E. A., "On the Advantages of Tagged Architecture," IEEE Trans. on Computers, C-22, 7, July 1973: pp. 644-656.

[FLY671

Flynn, M. J., and M. D. MacLaren, "Microprogramming Revisited," ACM National Conf. Proc., 22, 1967: pp. 456-464.

*[FLY741

Flynn, M. J., "Trends and Problems in Computer

Organization," IFIPS Congress Proc., 1, 1974: pp. 3-8.

[FO71] Foster, C. C., R. H. Gouter, and E. M. Riseman, "Measures of Opoode Utilization," IEEE Trans. on Computers, C-20, 5, May 1971: pp. 582-5 84. [FOX75 ] Fox, J. L., "Availability Design of the System/370 Model 168 Multiprocessor," Proc. Second USA-Japan Computer Conference, 1975: pp. 52-57.

[FRA71] Frank, H., and I. T. Frisch, Communication, Transmission and Transportation Networks, Addison-Wesley, 1971.

[FRE721

Freiberger, W. (ed.), Statistical Computer Performance Evaluation, Academic Press, 1972.

60

[HIL681 Hill, F. J., and G. R. Peterson, Introduction to Switching Theory and Logical Design, Wiley, 1968.

*[HIL731

Hill, F. J., and G. R. Peterson, Digital Systems: Hardware Organization and Designs, Wiley, 1973.

[HOA72] Hoagland, A. S., "Mass Storage-Past, Present, and Future," AFIPSProc. FJCC, 41,1972: pp. 985-991.

[HOT74] Holt, R.,

and M. Lemas, "Current Microcomputer Architecture," Computer Design, 13, 2, Feb. 1974: pp. 65-73.

[HPG21] Hewlett-Packard Corp., HP2100 Microprogramming

Guide, Manual No. 5951-3028, Hewlett-Packard Corp., Cupertino, Calif.

[HPP21] Hewlett-Packard Corp., A Pocket Guide-to the HP2100A

Computer, Manual No. 5951-4423, Hewlett-Packard Corp., Cupertino, Calif.

[HPS21] Hewlett-Packard Corp., HP2100 Microprogramming Software Manual, Manual No. 02100-90133, Hewlett-Packard Corp., Cupertino, Calif.

[HPX211

Hewlett-Packard Corp., HP-21MX Operating and Reference Manual, Manual No. 02108-90008, Hewlett-Packard Corp., Cupertino, Calif.

COMPUTER

[HUS70] Husson, S. S., Microprogramming: Principles and Practices, Prentice HalL 1970.

[IBB721

Ibbett, R. N., "'The MU5 Instruction Pipeline," The Computer Journal, 15, 1, Feb. 1972: pp. 45-50.

[IBM23] IBM Corp., IBM 2835 Storage Control and IBM 2305

Fixed Head Storage Module Ref: Manual, Manual GA261-1589-2, IBM Corp., San Jose, Calif.

[IBM24] IBM Corp., IBM System/360 Component Descrip-

tions-2314 Direct Access Storage Facility and 2844 Auxiliary Storage Control, Pub. No. GC28-65 15-8, IBM Corporation, Poughkeepsie, New York.

[IBM321

IBM Corp., IBM System/32 Functions Reference Manual, Pub. No. GA21-9176-0, IBM Corp., Rochester, Minn.

[IBM381 IBM Corp., IBM 3830 Storage Control and 3330 Disk Storage, Form No. GA26-1592-1, IBM Corporation, Poughkeepsie, New York.

[IBM45] IBM Corp., System/370, Model 145

1. A Guide to the IBM System/370 Model 145, Pub. No. GC20-1734-3, IBM Corp., White Plains, New York. 2. Functional Characteristics, Pub. No. GA24-3357-6, IBM Corp., Poughkeepsie, New York.

[IBM58] IBM Corp., System/370, Model 15 8

1. A Guide to the IBM System/370 Model 158, Pub. No. GC20-1754-1, IBM Corp., White Plains, New York. 2. Functional Characteristics, Pub. No. GA22-7011-2, IBM Corp., Poughkeepsie, New York.

[IBM601

IBM Corp., IBM System/360 Principles of Operations, Form GA22-5821-7, IBM Corp., Poughkeepsie, New York.

[IBM68] IBM Corp., System/370, Model 168

1. A Guide to the IBM System/370 Model 168, Pub. No. GC20-1755-1, IBM Corp., White Plains, New York. 2. Functional aaracteristics, Pub. No. GA22-7010-1, IBM Corp., Poughkeepsie, New York.

[IBM701IBM Corp., System/370 Prnciples of Operation, Manual No. GA22-7000-3, IBM Corp., White Plains, New York.

[IBM941

IBM Corp., IBM 7094 Principles of Operation, Form A22-6703-3, IBM Corp., Poughkeepsie, New York.

[IEE73] IEEE Computer Society, "Computing Networks from Minis through Maxis-Are They for Real?" COMPCON 73 Digest of Papers, Feb. 1973.

[IL168] Iliffe, J. K., Basic Machine Principles, MacDonald-Elsevier, 1968.

[IVE62] Iverson, K. E., A Programming Language, Wiley, 1962.

[INT801

Intel Corp., Intel 8080 Assembly Language Programming Manual, Intel Corp., Santa Clara, Calif.

[JOH75] Johnson, C. T., "IBM 3850/Mass Storage System," AFIPS Proc. NCC, 44, 1975: pp. 509-5 15.

[JON711 Johnson,

A. M., "The Microdiagnostics for the IBM System/360 Model 30," IEEE Trans on Computers, C-20, 7, July 1971: pp. 798-803.

[JOS701 Joseph, M., "An Analysis of Paging and Program Behavior," The ComWuter Journal, 13, 1, Feb. 1970: pp. 48-54. [KAN731 Kaneko, T., and B. Liu, "On Local Round-Off Errors in

*

Floating Point Arithmetic," JACM, 20, 3, July 1973: pp.

391-398.

[KAP72] Kaplan, K. R., and R. 0. Winder, "Cache Based Computer Systems," Computer, March 1973: pp. 30-37. December 1975

*

* [KIL621 Kilburn, T., D. Edwards, M. J. Lanigan, and F. H. Summer, "One Level Storage System," IRE Trans. on Computers, EC-1l, 2, April 1962: pp. 223-235. Reprinted in

[BEL711. *[KIL68J Kilburn, T., D. Morris, J. S.

Rohl and F. H. Sumner, "A System Design Proposal," IFIPS Congress Proc, 2, August 1968:

pp. 806-811.

*[KLE741

Kleinrock, L., and W. E. Naylor, "On Measured Behavior of the ARPA Network," AFIPS Proc. NCC, 42, 1974: pp. 767-780.

[KLE751 Kleinrock, L., Queueing Systems/Vol. 1: Theory, Wiley, 1975.

*[KNU681

Knuth, D., The Art of Computer Programming: Vol. 1, Addison-Wesley, 1968.

* [KUC701 Kuck, D. J., and D. H. Lawrie, "The Use and Performance of Memory Hierarchies: A Survey," Software Engineering, COINS III, VoL 1, Julius Tou (ed.), Academic Press, 1970.

[KUK731

Kuki, H., and W. J. Cody, "A Statistical Study of the Accuracy of Floating Point Number Systems," CACM, 16, 4, April 1973: pp. 223-230.

*[LAM69J

Lampson, B. W., "Dynamic Protection Structures," AFIPSProc. FJCC, 35, 1969: pp. 27-38.

* [LAP721 Lapidus, G., "MOS/LSI Launches - the Low Cost Processor," IEEE Spectrum, Nov. 1972: pp. 3 3-40.

[LAV71] Lavington, S., "An Experimental Paging Unit," Computer Journal, 14, 1, Feb. 1971: pp. 55-60.

*[LAW681

Lawson, H. W,, "Programming Language Oriented Instruction Streams," IEEE Trans. on Computers, C-17, 5, May 1968: pp. 476-485.

[LAW73] Lawson, H. W., and B. Malm, "A Flexible Asynchronous Microprocessor," BIt, 13, 2, June 1973: pp. 165-176.

*[LEH661

Lehman, M., "A Survey of Problems and Preliminary Results Concerning Parallel Processing and Parallel Processors," Proc. IEEE, 54, 12, Dec. 1966: pp. 1889-1901. Reprinted in [BEL71].

[LIN68] Lindsay, C. H., "Making the Hardware Suit the Language," Proc. ALGOL 68 Implementation Conf:, J. E. L. Peck (ed.), North Holland Publishing Co., 1968: pp. 347-365.

[LIP681 Liptay, J. S., "The Cache," IBM Systems Journal, 7, 1, 1968: pp. 15-21.

[LOR72] Lorin, H., Parallelism in Hardware and Software: Real and Apparent Concurrency, Prentice-Hall, 1972.

Lucas, H. C., "Performance Evaluation and Monitoring," Computing Surveys, 3, 3, Sept. 1971: pp. 79-9 1.

*[LUC711

[MAC74] MacKinnon, R. A., "Advanced Function Extended With Tightly Coupled Multiprocessing," IBM Systems Journal, 13, 1, 1974: pp. 32-60.

[MAH711 Mathur,

F. P., "On Reliability Modeling and Analysis of Ultrareliable Fault-Tolerant Digital Systems," IEEE Trans on Computers, C-20, 11, Nov. 1971: pp. 1376-1382.

[MAR72] Martin, J., Systems Analysis for Data Transmission, Prentice Hall, 1972.

*[MAT70] Mattson,

R. L, J. Gecsei D. R. Slutz and L L Traiger, "Evaluation Techniques for Storage Hierarchies," IBM Systems Journal, 9, 2,1970: pp. 78-117.

61

[MCA60] McCarthy, J., "Recursive Functions of Symbolic Expressions and Their Computation by Machine," CACM, 3, 4, April 1960: pp. 184.194.

*[MCD68] McDougall, M. H., "Computer Systems Simulation: An Introduction," Computing Surpeys, 2, 3, Sept. 1970: pp. 19 1-210.

[MCK69] McKinney, J. M., "A Survey of Analytical Time Sharing

[RA074] Rao, T. R. W., Error Coding for Arithmetic Processors, Academic Press, 1974.

*[ROB70] Roberts, L. G., and B. * [ROB731

1957.

McCracken, D. D., Digital Computer Programming, Wiley,

[MEA70] Meade, R. M., "On Memory System Design," AFIPS Proc. FJCC, 37, 1970: pp. 33-43.

[MIC16] Microdata Corp., Microprogramming Handbook, 2nd Edition, Microdata Corp., Santa Ana, Calif.

Murphy, J. O., and R. M. Wade, "The IBM 360/195," *[MUR701 Datamation, 1970: pp. 72-79.

April

[NAT161

National Semiconductor Corp., IMP-16C Application Manual, Pub. No. 4200021B, National Semiconductor Corp., Santa Clara, Calif.

*[NEE721

Needham, R. M., "Protection Systems and Protection Implementations," AFIPS Proc. FJCC, 41, 1972: pp. 572-578.

[NEW74] Newman, W. M., and R. F. Sproufl, Principles of Interactive Computer Graphics, McGraw Hill, 1973.

[NIE671

Nielsen, N. R., "The Simulation of Time Sharing

Systems," CACM, 10, 7, July 1967: pp. 397-412.

[NIE71] Nielsen, N. R., "An Analysis of Some Time Sharing Systems," CACM, 14, 2, Feb. 1971: pp. 79-90.

[ONE67] O'Neill, R. W., "Experience Using

Time-Shared Multiprogramming System With Dynamic Address Relocation Hardware," AFIPS Proc. SJCC, 30, 1967: pp. 611-621.

*[ORG72]

a

Organick, E. I., The MULTICS System, MIT Press,

1972.

*[ORG73] Organick,

E. I., Computer System Organization: The B5 700/B6 700 Series, Academic Press, 1973.

Roberts, L. G., Network Rationale: A Five Year

Re-Evaluation," COMPOON 73 Digest of Papers, 1973: pp. 3-5 and 39-44.

Models," Computing Surveys, 1, 2, June 1969: pp. 106-116.

[MCR571

D. Wessler, "Computer Network

Development to Achieve Resource Sharing," AFIPS Proc- 5JCC, 36, 1970: pp. 543-549.

[ROE69] Roek, D. J., and W. C. Emerson, "A Hardware

Instrumentation Approach to Evaluation of Large Scale Systems," 24th ACMNat'l. Conf Proc., 1969: pp. 351-367.

*

[ROI691

Rosin, R. F., "Contemporary Concepts in Microprogramming and Emulation," Computing Surveys, 1, 4, Dec. 1969: pp. 197-212.

[RO1721 Rosin,

R. F., G. Frieder, and R. H. Eckhouse, "An Environment for Research in Microprogramming and Emulation," CACM, 15, 8, Aug. 1972: pp. 748-761.

[ROI74] Rosin, R. F., "The Significance of Microprogramming," SIGMICRO Newsletter, 4, 4, Jan. 1974: pp. 24-39.

[ROS611 Ross,

D. A., "A Generalized Technique for Symbol Manipulation and Numerical Calculation," CACM, 4, 3, March

1961: pp. 147-150.

[RUD721 Rudolph,

J. A., "A Production Implementation of an Associative Array Processor-STARAN," AFIPS Proc. FJCC, 41, 1972: pp. 229-241.

[SAL70] Saltzer, J. H., and H. Gintell, "The Instrumentation of Multics," CACM, 13, 8, August 1970: pp. 495-500. [SAL74a] Saltzer, J. H., "A Simple Linear Model of Demand Paging Performance," CACM, 17, 4, April 1974: pp. 181-186.

[SAL74b] Saltzer, J. H., "Protection and Control of Information in MULTICS," CACM, 17, 7, July 1974: pp. 388-402.

[SCE671 Scherr,

A. L., An Analysis of Time Shared Computer

Systems, MIT Press, 1967.

[SCE73] Scherr, A. L, "Functional Structure of IBM Virtual Storage Operating Systems, Part II: OS/VS2-2 Concepts and Philosophies," IBM Systems Journal, 12, 4, 1973: pp. 382-400.

[0RN72] Ornstein, S. M., F. E. Heart, W. R. Crowther, H. K. Rising, S. B. RusseL and A. Michel, "The Terminal IMP for the ARPA Computer Network," AFIPS Proc. SJCC, 40, 1972: pp.

* [SCH72] Schroeder, M. D., and J. H. Saltzer, "A Hardware Architecture for Inplementing Protection Rings," CACM, 15, 3, March 1972: pp. 157-170.

*[ORN75] Ornstein,

S. M., W. R. Crowther, et. aL, "Pluribus-A Reliable Multiprocessor," AFIPS Proc NCC, 44, 1975: pp. 55 1-561.

[SED70] Sedgewick, R., R. Stone and J. W. McDonald, "SPY-A Program to Monitor OS/360,"AFIPSProc. FJCC, 37,1970: pp.

[PAD64J Padegs, A., "Part NV-Channel Design Considerations," IBM Systems Journal, 3, 2, 1964: pp. 165-181.

[SHA69] Sharpe, W. R., Economics of Computers, Columbia

*[PET72J

Peterson, W. W., and E. J. Weldon, Error Correcting

[SHE72] Shemer, J. E., and J. B. Robertson, "Instrumentation of

Pierce, W. H., Fault-Tolerant Computer Design, Academic Press, 1965.

*[SIS69] Sisson, S. S., and M. J. Flynn, "Addressing Patterns and

243-254.

Codes, MIT Press, 1972.

[PIE65]

[RA164J Raichelson, E., and G. Collins, "A Method for Comparing the Internal Operating Speed of Computers," CACM, 7, 5, May 1964: pp. 309-310.

Randell, B., *fR[68] Allocation Systems,"

and C. J., Keuhner,

"Dynamic Storage

CACM, 11, 5, May 1968: pp. 297-306.

[RAN69] RandelL B., "A

Note on Storage Fragmentation and Program Segmentation," CACM, 12, 7, July 1969: pp. 365-370.

62

1 19-128

University Press, 1969.

Time-Shared Systems," Computer, 5, 4, July/Aug. 1972: pp. 39-48.

Memory Handling Algorithms," AFIPS Proc. FJCC, 33, 1968: pp. 957-967.

[SK169] Skinner, C. E., and J. R. Asher, "Effects of Storage Contention on System Performance," IBM Systems Journal, 8, 4, 1969: pp. 319-333.

[SMi68] Smith, J. M., "A Review and Comparison of Certain

Methods of Computer Performance Evaluation," The Computer Bulletin, 12, May 1968: pp. 13-18.

COMPUTER

Solomon, M. B., Jr., "Economics of Scale and IBM System/360," CACM, 9,6, June 1966: pp. 435-440.

*[SOL66]

*[SRE74] Sreenivasan,

K., and A. J. Kleinman, "On the Construction of a Representative Synthetic Workload," CACM, 17, 3, March 1974: 127-133.

*[WIK531 Wilkes, M V., and J. B. Stringer, "Microprogramming and the Design of Control Circuits in an Electronic Computer," Proc. of Cambridge Philosophical Society, Pt. 2, 49, April 1953: pp. 230-238. Reprinted in [BEL711.

*[WIK72] Wilkes, M. V., Time-Sharing Computer Systems, Second Edition, MacDonald/American Elsevier, 1972.

*[STE72J

*[WIL72aJ Wilner, W., "Design of the Burroughs B 1700," AFIPS

[STN671 Stanga,

D. C., "Univac 1108 Multiprocessor System," AFIPS Proc. SJCC, 30, 1967: pp. 67-75.

[WIL72bJ Wilner, W., "B1700 Memory Utilizatiop," AFIPS Proc.

[ST072] Stone, H., Introduction to Computer Organization and

[WIN731 Winder, R. O., "A Data Base for Computer Performance

Stein, M., and W. D. Munro, Introduction to Machine Arithmetic, Addison-Wesley, 1972.

Data Structures, S/360 Edition, McGraw-Hill, 1972. See also PDP-11 edition, McGraw-Hill, 1974.

*[ST075] Stone, H. (ed.), Introduction to ComputerArchitecture,

Proc. FJCC, 41,1972: pp. 489-497.

FJCC, 41,1972: pp. 579-586.

Evaluation," Computer, 6, 3, March 1975: pp. 25-29.

[WIR681 Wirth, N., "PL360, a Programming Language for the 360 Computer," JACM, 15, 1, Jan. 1968: pp. 37-74.

Science Research Associates, Inc., Palo Alto, California, 1975.

[STR741

1974.

Sterbenz, P., Floating Point Computation, Prentice Hall,

*

Wulf, W. A., and C. G. Bell, "C.mmp-A Multi[WUL721 Miniprocessor," AFIPS Proc. FJCC, 41, 1972: pp. 765-777.

[STS641

Stevens, W. Y., "The Structure of System/360, Part II-Systems Implementation," IBM Systems Journal, 3, 2, 1964: pp. 136-143. Reprinted in [BEL71].

[STU711 Strauss, J. C., "A Simple Throughput and Response Model of EXEC 8 Under Swapping Saturation," AFIPS Proc. FJCC, 39, 1971: pp. 39-49.

[SWE6S] Sweeney, D. W., "An Analysis of Floating Point Addition," IBM Systems Journal, 4, 1, 1965: pp. 31-42.

[TEC711

IEEE Computer Society, IEEE Transactions on. Computers, C-20, 7, July 1971. Special issue on Micro-

programming

[TEC74] IEEE Computer Society, IEEE Transactions on

Computers, C-23, 7, July 1974. Special issue on Micro-

programming.

*[TE0721

Teorey, T. J., and T. B. Pinkerton, "A Comparative Analysis of Disk Scheduling Policies," CACM, 15, 3, March 1972: pp. 177-184.

Thorton, J. E., Design ofa Computer-The Control Data *[TH0701Scott Foresman, 1970. 6600, *

Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of R&D, 11,

[TOM671

1, Jan. 1967: pp. 25-33.

[TUC65] Tucker, S. G., "Emulation of Large Systems," CACM, 8, 12, Dec. 1965: pp. 753-761. *[TUC671 Tucker, S. G., "Microprogram Control for System/360," -IBMSystems Journal, 6, 4, 1967: pp. 222-241.

[UNIll] Sperry Rand Corp., Univac 1108 Multiprocessor System

Reference Manual, Processor and Storage, Pub. No. UP4053,

Sperry Rand Corporation, Univac Division, Blue Bell, Pennsylvania.

[WAL67] Walter, E. S., and V. L. Wallace, "Further Analysis of a Computing Center Environment," CACM, 10, 5, May 1967: pp. 266-272.

Computer Systems Summary Burroughs B1700. [WIL72a; WIL72b; BUG17] Burroughs B5000/B5500. [BEL71, Ch. 22; ORG73; BUG55] Burroughs B6500/B6700. [HAU68; CRE70; ORG73; BUG65] CDC 6600. [THO70; BEL71, Ch. 39; CDC66; CLA64] CDC 7600. [CDC76] CDC STAR 100. [CDCOO] Data General Nova. [DGC71] Data Saab FCPU. [LAW73] DEC PDP-8. [BEL71, Ch. 5; DEC8E] DEC PDP-10. [DEC10] DEC PDP-1 1. [BEL70; DEC05; DEC45; ST072 (PDP- 1 1

Ed.)]

Honeywell Series/60 Level 64. [ATK74] HP2100-HP21MX. [HPG21; HPP21; HPS21; HPX21] IBM System/32. [IBM32] IBM 650. [BEL71, Ch. 17] IBM 1401. [BEL71, Ch. 18] IBM 7094. [BEL71, Ch. 41; IBM94]

IBM Stretch. [BUC62; BEL71, Ch. 34] IBM System/360. [BEL71, Pt. 6, Sec. 3; AMD64; BLA64a; BLA64b; STS64, SOL66; BRO69; ST072; HEL73; GEA74; IBM60; CON70; MUR70; HUS70] IBM System/370. [IBM70; IBM45; IBM58; IBM68; SCE73; MAC74] ILLIAC IV. [BAN68] Intel 8080. [INT80; HOT74] Microdata 1600. [MIC16] MU5. [KIL68; LIN68; LAV71; IBB72]

[WAT691

National IMP-16. [NAT 16; HOT74] Nanodata OM-1. [ROI72]

*[WEB671

Staran. [RUD72]

Watson, R. W., T. H. Myer, I. E. Sutherland and M. K. Vosbury, "A Display Processor Design," AFIPSProc. FJCC, 35, 1969: pp. 209-217.

Weber, H., "A Microprogrammed Implementation of EULER on IBM System/360 Model 30," CACM, 10, 9, Sept. 1967: pp. 549-558. Reprinted in [BEL71].

December 1975

Univac 1108. [STN67; UNI1 1; STU71] 63