offer the best performance trade-offs among cost, speed and power. ... size, however, electrical interference through the common substrate is becoming a limiting ...
Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach Henry H.Y. Chan & Zeljko Zilic Microelectronics and Computer Systems Laboratory, Department of ECE, McGill University, Montreal, Quebec, Canada. H3A 2A7 {henry,zeljko}@macs.ece.mcgill.ca Abstract -- On-chip phase-locked loops (PLLs) are critical components for clock generation and recovery in high-speed communication and data processing systems. The presence of partiallycorrelated substrate noise presents a new challenge to predicting PLL jitter. We propose a model that describes the substrate noise-tojitter transfer characteristics for CMOS ring oscillator-based PLLs on epitaxial substrate. The proposed model is verified against jitter simulations.
1. Introduction The main objective in quality electronic design is to achieve performance breakthroughs while ensuring product reliability and low cost. As indicated by the emergence of integrated system-on-a-chip (SoC) designs, single chip solutions often offer the best performance trade-offs among cost, speed and power. With ever-increasing clock rate and shrinking feature size, however, electrical interference through the common substrate is becoming a limiting factor in SoCs. Design, verification and testing strategies must be extended to keep up with substrate noise problems. Phase-Locked Loops (PLLs) are widely used for clock recovery and frequency synthesis. The impact of PLL jitter on system performance is crucial, and low PLL jitter is often the key to achieve high quality designs. High-speed communication circuits solely depend on accurate clock extraction, while data processors require skew-free clock signals to conduct synchronous operations. For instance, signal delay across a die equals 1 clock period [1] in 0.25µm technology. Complex clock distribution schemes are increasingly important for overcoming clock skew problems and clock power consumptions. Such schemes involve distributing multiple PLL units over the entire IC to maintain global synchronization. The migration to SoC environment subjects PLL to a new variety of external interferences. Without detailed coupling information, most designers rely on over-designed guard rings to relieve noise problems. Since extensive guard ring structures around every PLL is infeasible due to high area penalty, sound analysis techniques are needed during clock tree designs to control and minimize substrate noise. To obtain accurate clock extraction, quantitative analysis of the effect of substrate coupling on PLLs is necessary. Traditionally, the majority of jitter analysis has been focused on its internal device noise. Recently, deterministic sinusoidal source has been proposed to model external interference [2], such as substrate coupling. However, substrate noise arises mostly due to impulsive charge injection during gate switching. Therefore, a more accurate model is required to describe the current spikes. In this paper, we present an integrated method to model substrate coupling effects on PLLs. We employ a novel cyclostationary noise model and a layout-aware extraction of multiple
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Fig. 1 Measurement results of PLL Jitter. PLL is influenced by substrate noise from different locations {1,...,6}.
substrate noise paths at PLL. An overview of how PLL is affected by substrate coupling is presented in Section 2. The computation of substrate noise is discussed in Section 3. Coupling mechanisms and the substrate parasitic model generation involved in the computation are also introduced. In Section 4, the PLL jitter due to substrate coupling is derived. The formulated model is verified against circuit simulations in Section 5, followed by the conclusions in Section 6.
2. PLL in Mixed-Signal Systems Time shifts in digital signal transitions are commonly known as jitter. Jitter could be a result of the intrinsic non-idealities of transistor devices and external interference. The former effect is well-studied: Conventional oscillator phase noise analyses have focused on uncorrelated, white or colored [3],[4] noise sources that originate from within devices. In fact, these noise sources are well-characterized and included in standard device models [5] in most circuit simulators. On the other hand, external interference due to the switching noise from neighboring circuits on the same substrate is a tightening problem for SoC designers and EDA tools. The injected noise currents alter the transient characteristics of the delay elements and degrade the oscillator jitter performance at different directions and intensities. Substrate noise is layout-, process- and time-dependent. Experimental measurements repeatedly showed that the degradation is non-monotonic and difficult to compute. Furthermore, when the PLL delay elements are not switching, substrate noise has no effect on them. Switching activity is thus related as well. Fig. 1 shows our jitter measurements of a PLL circuit suffering from substrate coupling from 2 groups of noise sources from 6 progressively shorter distances. The results imply that jitter prediction cannot be achieved using superposition methods. In the next section, we present a scheme that computes PLL jitter due to substrate coupling, based on the circuit layout. Fig.
(i)
(ii)
Fig. 2 Substrate-noise induced jitter signal flow diagram
2 is the signal flow diagram of the substrate-noise induced jitter modeling algorithm. It tightly couples the substrate model with the PLL noise model. The substrate noise ∆i ( t ) injected into the substrate first passes through the substrate model, where the coupling response ∆v ( t ) near the PLL voltage-controlled oscillator (VCO) is computed. The substrate coupling process of ring oscillator VCO is modeled as taking discrete time samples of timing jitter ∆t ( t ) . The sampled phase noise Θ on ( t ) then passes through the PLL system function, and output as accumulated phase noise Θ tot ( t ) . In the next section, our substrateaware PLL jitter evaluation algorithm is discussed in detail.
3. Substrate Modeling In a shared substrate environment, the notion of an ideal unipotential substrate is no longer valid. Noise injected by digital gates is readily amplified by the large number of gates switching simultaneously and the low bulk resistivity substrate in currently popular fabrication technologies. Transient peaks of substrate potentials may reach as high as 0.1V. The injected charges near MOS transistors can alter their drain diffusion voltages, and delay characteristics by modifying the channel conductivities. To determine the optimal amount of protection against substrate coupling so that no area budget is compromised, the jitter performance due to substrate coupling needs to be determined accurately by the following steps: 1. Coupling path identification, 2. Coupling response simulation, and 3. Substrate-coupled jitter evaluation.
3.1 Coupling Path Identification To obtain an accurate model of substrate noise, a substrate parasitic RC network is constructed. First, all dominant substrate noise sources are selected according to transistor sizes and switching activities. Timing and weakly-driven elements susceptible to noise are also identified. In this case, they are the delay elements of the VCO. Using the set of noise sources and delay elements, a substrate parasitic model is generated. The model is then simulated to yield the substrate coupling responses at the substrate terminal of the delay elements. Since the model size can be very large for practical systems using conventional rectilinear discretization schemes, an alternative modeling schem e [6] is used instead to reduce model complexity. The substrate is discretized into a number of equipotential regions (substrate ports) based on the Delaunay triangulation algorithm [7]. Impedance between each pair of adjacent regions are then computed. The resulting RC network is then simplified. The resultant network is the substrate
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Fig. 3 Analysis result from substrate model comparing mean substrate noise levels (in mV) on epitaxial substrate (i)with and (ii)without backplane connections
coupling path model. By generating substrate ports only among noise injection and absorption sites, the size of the substrate model is minimized, and coupling analysis can be substantially simplified without loss of model accuracy. This efficient modeling scheme is detailed in the following subsection.
3.2 Substrate Model and Coupling Response A substrate model for the epitaxial-bulk process is employed. The model consists of an RC network of devices parallel to the substrate surface, and a single bulk-node at the bottom. To handle large circuits, the algorithm uses a Π electrical model, which keep the number of nodes present in the extracted model to a minimal. To further increase the efficiency, the algorithm can be applied to a partial region of the design, by assigning a selection window. Although Π models cannot abstract all possible geometrical layouts [8], we seek model configurations that can give the best approximations. A planar RC network models the resistive (~10Ωcm) epitaxial layer of the substrate. It is generated by the Delaunay triangulation algorithm according to the locations of the substrate and well connections. Edges of the Delaunay graph are then replaced by laterally-oriented devices, where their values are determined by the length of the edges they replace. The highly conductive (~0.01Ωcm) bulk layer of the substrate and well are represented by a single node each, which connects to nodes of the epitaxial network to form the overall substrate model. The extracted model can be used independently to evaluate substrate coupling by any circuit simulators. To accommodate the different needs for accuracy and efficiency, the substrate is modeled in 3 different levels of complexity. They differ from each other in the method used to collect points that represent the footprint of each substrate contact. In the first run-level, only the centroid of the substrate contact is used, and the shape of the contact is lost. At the second run-level, the corner points of the substrate contact are collected, representing the convex hull of the contact. At the third level, a combination of centroids and corner points are used. The geometric shapes are retained. To further increase accuracy, additional points along the edges can be added. Fig. 3 shows the analysis result of a sample circuit layout. It
falling transition rising transition
Fig. 4 Periodic timing jitter obtained by applying (1) to substrate noise simulation results
illustrates the positive effect of backplane connections on the noise level near a the circuit on an epitaxial-type substrate. This reinstate the importance of properly biasing the bulk layer for noise reduction in epitaxial-type substrate [8].
3.3 Timing Jitter Model The modeling of substrate noise depends largely on the correlations among the components which coupling takes place. Substrate coupling between different circuits often appear as wide-band noise because signals and noise sources are uncorrelated. However, substrate noise spectrum typically exhibit distinct frequency components related to the system clock frequency 1 ⁄ T . Substrate noise is often found to possess some definite phase relationships with VCO signals because clockdriven gate arrays switch synchronously. In [2], the noise current is represented by deterministic sinusoids. It is their moments, such as means, variances, rather than the noise samples themselves that should be modeled as periodic. We model the substrate noise ∆v ( t ) as a τ -periodic wide-sense cyclostationary Gaussian process. This assumption implies that while the substrate noise ∆v ( t ) is random, its mean and variance are both periodic in τ . Although the VCO delay elements have non-linear voltagecurrent transfer characteristics, the current-phase transfer function is still linear for all practical purposes [12]. Hence, the change of phase is proportional to the change of potential for small changes at the output nodes ∆t ( t ) ≈ K – 1 ∆v ( t ) . (1) With known jitter sensitivity K – 1 of the circuit, where K is the transition slew rate, timing jitter ∆t ( t ) can be derived from the substrate noise ∆v ( t ) obtained from the substrate model. Therefore, the mean square timing jitter σ 2 ∆t is also τ -periodic, and is linearly proportional to the mean square substrate noise σ 2 ∆v during its rising and falling transitions. Fig. 4 plots the timing jitter due to substrate noise. In the next section, we explore the phase accumulation effect of ring oscillators, which provides an efficient method to predict PLL jitter performance. We shall see that the ratio λ = T ⁄ τ has a direct impact on the amount of substrate coupling perceived by the PLL, and consequently, its jitter performance.
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Fig. 5 PLL jitter response model
4. PLL Jitter Modeling PLL is a time-varying system consists of a VCO and a feedback control circuit which regulates the phase and frequency of the VCO. Mixed-signal coupling simulations showed that PLL jitter performance is relatively insensitive to noise injected by the various components of the PLL itself [11]. Rather, it is more susceptible to noise current injected by peripheral digital circuitry when the PLL is integrated with other components. On the other hand, the typical size of mixedsignal systems does not permit detailed phase noise analysis routinely performed in RF designs. Consequently, a jitter model for external interference that can be evaluated efficiently is crucial, as the noise floor of these operating environments is usually high. In this section, we seek practical jitter models to give estimates of PLL jitter. Fig. 5 shows the block diagram of a ring oscillator PLL, with an additive VCO jitter source Θ n at the VCO output. During the locked state, noise sources arise from the phase detector and the loop filter will be attenuated by the low-pass mechanism before reaching the PLL output. They are thus omitted from the model. Conversely, single-cycle VCO jitter exits at the PLL output before the feedback mechanisms have time to react. This implies that the variance of the long-term PLL jitter is bounded [10] by the closed-loop transfer function, while its short-term characteristic is dominated by Θ n of the VCO. PLL Jitter due to substrate-coupled switching noise falls into the latter category because its influence is transient and its duration is comparable to a clock period. In the following subsections, we focus on analyzing its influence on the VCO to determine the short-term PLL jitter characteristics.
4.1 Cyclostationary Jitter Model Substrate coupling induces noise typically from switching to quiet drain diffusion regions. Body terminals of M OS transistors are also affected by the change of substrate potential, altering their threshold voltages. For PLLs, these effects can be modeled as the transition delay of the ring oscillator delay cell. For CMOS ring oscillator, each delay element is sensitive to substrate coupling only during transitions. The delay cell is susceptible to p-substrate (n-well) coupling during its falling (rising) transition, and there is no impact when the delay elements are not switching. Therefore, the PLL jitter accumu-
lation process can be viewed as taking the sum of discrete time samples of the VCO jitter. For the sake of brevity, we ignore nwell coupling since it can be well-isolated by using separate wells in n-well processes [8]. For an m -stage VCO, the jitter
substrate noise profile
τ
(i)
T
accumulated jitter during the nth VCO clock cycle is m
∆tn =
∑ ∆t ( n – 1 )T + i ---mT
, n≥1
where T is the PLL clock period and ∆t ( t ) is the jitter due to substrate coupling from (1). Let ∆t ( t ) be a cyclostationary Gaussian process with period τ . We now derive the PLL jitter response. We will show later that jitter performance will depend upon the relationship between T and τ . The total n
2 π∆t k
- ( 1 – ε) ∑ -------------T
n–k
, n≥1
(3)
k=1
in the time domain [9]. Equation (3) states that the PLL output jitter is the sum of the jitter from each delay element transition in all past clock cycles. The root mean square (RMS) PLL output jitter is thus
n
n
σ hk ξ hk h = 1 k = 1
2π 2 E [ θ tot ( nT ) ] = -----T
∑∑
1/2
(4)
where σ hk = E [ ∆t h ∆tk ] and ξhk = ( 1 – ε )2n – ( h + k ) . Equation (4) shows that the RMS jitter is the square root of the power series ξ hk with autocorrelation σ hk as coefficients. For uncorrelated ∆t ( t ) ,
(ii) T
VCO output transitions Fig. 6 Substrate noise profile and VCO period relationships for (i) combinational logic λ=1, and (ii) a state machine λ=6.
accumulated jitter at the nth falling transition is θ t ot ( nT ) =
τ
(2)
i=1
computational complexity of (4) is O ( n ) since σ hk = 0
for k ≠ h . For substrate noise interference, σhk is generally non-
can make use of special properties of substrate coupled switching noise in the following subsection to reduce the complexity and memory storage requirement to O ( n ) .
4.2 PLL jitter Prediction Recall from (2) that for an m -stage VCO, each ∆t k is the sum of transition delays of the m delay cells during the clock period. Switching noise periodicity is often related to the VCO frequency, let us consider the significance of the relationship between the noise source ∆t ( t ) ) and the PLL. Since the neighboring digital gates are usually driven by the PLL, the noise period τ is often equal to the clock period T , or a scalar multiple of it (Fig. 6). Let τ = λT , λ a non-negative integer, (2) becomes m
zero, as ∆t ( t ) is temporally correlated. Computational complexity of (4) becomes
O ( n2)
. σhk can be obtained from the
autocovariance matrix of random variable ∆t ( t ) Σ ∆t ∆t = h k
∆t k =
σ h2 ρ hk σ σ k σ hh σ hk h = σ kh σ kk ρ hk σ σ σ k2 k h
,
(5)
where σi , ρhk are the RMS value of ∆t i and the correlation coefficient between ∆t h , ∆tk respectively. In general, the
∑
m
i k–1 - τ + ----------- τ ∑ ∆t ------λ mλ
i τ ∆t k – 1 + ---- --- = m λ
i=1
,
(7)
i=1
where m, k, i, λ are integers and ∆t ( t + iτ ) = ∆t ( t ) . Equation (7) states that, ∆t ( t ) repeats in every mλ time samples, and so the sum ∆tk is statistically identical every λ terms. A phase shift of τ ⁄ λ between ∆t ( t ) and PLL is introduced in each subsequent clock cycle if λ ≥ 2 . Applying (7) to (4) yields that the n × n autocovariance matrix Σ ∆t ∆t among all n time samples h
λ 2
k
distinct terms with a repeating λ × λ
autocovariance matrix is computed for every pair of ∆th , ∆t k
consists of only
from n samples using
pattern for λ ≥ 2 . For example, for substrate noise periodicity λ = 3 , there are 3 distinct time samples, while Σ ∆t ∆t consists
σ h2 = nΣ ( ∆th 2 ) – ( Σ ∆th ) 2 ,
and
ρhk σ σ = nΣ ( ∆ th ∆t k ) – Σ ( ∆t h )Σ ( ∆tk ) h k
h
.
(6)
Evaluating (4) is computationally expensive and correlation coefficients of ∆t ( t ) are unknown in practice. Fortunately, we
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of
3 2
= 6
k
distinct terms and has a 3 × 3 repeating pattern. For
t h e ca se t h at λ = 1 , al l t im e sa m p l es a re i d e nt i ca ll y
(ii)
(i)
(iii)
E [ ∆th ∆t k ] = 0
, ∀k ≠ h . Therefore, the correlation matrix is
non-zero only for its diagonal terms, namely E [ ∆tk2 ] = σ 2 ∆t 2 ( nT ) ] , σ 2 ∆t identically. To obtain a strict lower bound for E [ θ tot
Fig. 7 Autocorrelation Matrices Σ for k=6 time samples containing λxλ−binned pattern for (i) λ=1, (ii) λ=2, and (iii) λ=4.
should equal the minimum value among the diagonal terms. However, we found that using the mean value of the diagonal terms works well and gives a tighter bound. With all the crossterms eliminated, the mean square output jitter in (4) can be simplified as follow 2 4π 2 E [ θ ( n T ) ] = ---------σ 2 ∆t t ot T2 ˜
n
∑ (1 – ε)
2 (n – k )
.
(8)
k=1
Hence the RMS single cycle jitter is 2π 2 2 – 2ε + ε 2 E [ θ ( T ) ] = ------σ T ∆t t ot ˜
,
(9)
and the long-term RMS PLL jitter is [9] lim
n→∞
Fig. 8 Comparison of accumulated PLL jitter for 20 clock periods due to switching noise and white noise ∆t k =
∑ ∆t( iτ ⁄ mλ ) , k = 1, …, n . Fig. 7 illustrates the results. i
In practice, the autocorrelation terms generally attenuate as one moves away from the diagonal in the correlation matrix Σ . This discrepancy is mainly due to two reasons. (i) A different logic state will produce a different switching noise signature, and (ii) the accumulated jitter θtot ( nT ) actually shifts the next
E [θ
Jitter Lower-bound: ∆t(t) Uncorrelated, Stationary In this case, ∆t i at different time instants are uncorrelated,
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.
(10)
The above jitter equations indicate that increasing the loop bandwidth ε increases the PLL cycle-to-cycle jitter (9), while the long-term jitter (10), decreases. Jitter Upper-bound: ∆t(t) Fully Correlated, Stationary Here, all correlation terms are non-zero and identical, E [ ∆th ∆t k ] = σ 2 ∆t , ∀h, k . For an absolute upper bound, σ 2 ∆t equals the maximum value among the diagonal terms. The mean square output jitter becomes 2 4π 2 E [ θ˜ tot ( nT ) ] = ---------σ 2 ∆t T2
n
∑
( 1 – ε ) n – k
k=1
2
.
(11)
The RMS single cycle jitter is
transition tn + 1 in time, thus changes the time when the noise is to be sampled. Nevertheless, equation (7) still provides fundamental insights into the jitter process due to substrate coupling. It suggests that the perceived RMS jitter can be very different from those using a white noise assumption. Fig. 8 computes 10 iterations of the accumulated RMS jitter for 20 clock periods due to switching noise and white noise for a type 1 PLL. The RMS jitter due to white noise begins to settle after 5 periods, while PLL jitter due to switching noise increases linearly. Simulations such as those in Fig. 8 is important for designers to predict the amount of PLL jitter due to substrate noise. For instance, a type 2 or higher filter is needed in this case for good jitter performance. However, constructing the covariance matrix for substrate noise calculations is tedious and sometimes unecessary. The following subsections investigate how approximated jitter calculations can be used to predict timing jitter using only the knowledge of the diagonal terms of the covariance matrix.
2π σ ∆t 2 - ----------------------( nT ) ] = ----T ε(2 – ε ) tot
2π 2 - σ (2 – ε) E [ θ˜ tot ( T ) ] = ----T ∆t
,
(12)
and the long-term RMS PLL jitter is lim
n→∞
2 πσ ∆t 2 E [ θ˜ t ot ( nT ) ] = --------------Tε
.
(13)
Predicted Jitter The predicted RMS jitter is given by 1 2 2 2 + E [ θ˜ tot E [ θtot ( nT ) ] = -( nT ) ] 2 E [ θt ot ( n T ) ]
.
(14)
Equation (14) is verified in the next section.
5. Simulation Results We implemented an integrated substrate extraction and PLL noise model, consisting of three distinct steps. We first extract the dominant switching noise sources, limiting the number of relevant substrate ports. The DNS_EXTRACT pseudocode in Fig. 9 summarizes the algorithm used to search for dominant switching noise. A power estimation algorithm in SIS [13] is used to calculate the noise level indirectly. A substrate model is obtained next. The substrate ports, i.e, noise sources are then connected to the delay cells of a VCO. We extract substrate
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DNS_EXTRACT(logic_network) Calculate switching activity for every gate type foreach logic_function(i) foreach logic_gate(j) in logic_function(i) find gate.noise(j) function.noise(i)=sum(gate.noise) if function.noise(i) < avg_total_noise_threshold discard function(i) else sort gate.noise foreach logic_gate(j) in logic_function(i) if gate.noise(j) < epsilon*max{gate.noise} discard gate(j) else save domina nt switching gate(j)
Fig. 9 DNS_EXTRACT pseudocode searches for dominant noise sources
Fig. 11 Accumulated RMS jitter after 160 transitions
noise model is suitable for substrate-coupling induced PLL jitter estimations when detailed phase noise analysis is impractical. The model captures important transient characteristcs of switching noise. Cascading these models together will provide design guidance that reduces the effect of substrate coupling on monolithically integrated PLLs.
7. References [1]
[2]
Fig. 10 Simulated jitter, predicted jitter, and its upper and lower bounds
noise samples from the substrate response simulations. Substrate-coupled switching noise extracted from Spice circuit simulations are injected into a PLL with loop gain ε ≈ 0.01 . The peak RMS jitter is found to be 24ps. The calculated jitter using (4), the predicted jitter using (14), and its upper and lower bounds are plotted in Fig. 10. Evaluating (4) and (14) for 400 clock cycles require 158.69 and 0.93 seconds, respectively, on a SUN UltraSparc 5 workstation. We also compared the results of our jitter prediction methods with full jitter calculations for 100 sets of switching noise samples with 160 clock transitions each. The RMS jitter for a 3stage VCO PLL is interfered by substrate noise. The initial phase offsets between the switching noise sources and the clock are chosen randomly from a uniform distribution. The accumulated RMS jitter for the 100 trials after 160 transitions are plotted in Fig. 11. The predicted jitter results closely approximate the simulated jitter while spending less than 1% of the time the latter computations needed.
[3]
[4] [5] [6]
[7]
[8]
[9]
[10]
[11]
6. Conclusions The impact of PLL jitter on system performance is crucial for almost all digital systems. We presented a substrate modeling algorithm that provides several extraction complexity levels suitable for different efficiency and accuracy needs. A PLL jitter estimation method is also presented. Our cyclostationary
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[12]
[13]
Gutnik, V.; Chandrakasan, A.P., “Active GHz clock network using distributed PLLs”, IEEE Journal of Solid-State Circuits, Volume: 35 Issue: 11, Nov. 2000 Pg:1553 -1560 Barton, N.; Ozis, D.; Fiez, T.; Mayaram, K., “Analysis of jitter in ring oscillators due to deterministic noise”, IEEE ISCAS, Vol:4, Pg:393 -396, 2002. Kaertner F.X., “Determination of the Correlation Spectrum of Oscillators with Low Noise”, IEEE Trans. on Microwave Theory and Techniques, Vol. 37, No. 1, January 1989. Demir A., “Phase Noise in Oscillators: DAEs and Colored Noise Sources”, ICCAD San Jose CA USA, 1998. HSpice User’s Manual Vol. 2 - elements and Models, Meta-Software inc., Campbell, 1992. Chan, H.H.Y.; Zilic, Z.; “A practical substrate modeling algorithm with active guardband macromodel for mixed-signal substrate coupling verification “, IEEE International Conference on Electronics, Circuits and Systems, 2001, Pg:1455 -1460 vol.3 Wemple, I.L.; Yang, A.T. "Integrated circuit substrate coupling models based on Voronoi tessellation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.14, Pg:1459 -1469, 1995. Aragones, X.; Gonzalez,J.L.; Rubio, A., Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Academic Publishers, Boston, 1999. Kim, B.; Weigandt, T.C.; Gray, P.R., “PLL/DLL system noise analysis for low jitter clock synthesizer design”, IEEE International Symposium on Circuits and Systems,vol.4, Pg:31-34 1994. Weigandt, T.C.; Beomsup Kim; Gray, P.R., “Analysis of timing jitter in CMOS ring oscillators”, IEEE International Symposium on Circuits and Systems, vol.4 Pg:27 -30, 1994. K.H. Kwan, I.L.Wemple, A.T. Yang, “Simulation and Analysis of Substrate Coupling in Realistically-Large Mixed-A/D Circuits,” IEEE Symposium on VLSI Circuits, 1996. A. Hajimiri, T.H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, February 1998. Sentovich, E.M.; Singh, K.J.; et. al., “SIS: A System for Sequential Circuit Synthesis”, Electronics Research Laboratory Memorandum No.UCB/ ERL M92/41, Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, 1992.
