Apr 4, 2006 - 5.4.1 Triac Load. 5.4.2 Full-Bridge Rectifier Load. 5.5 Summary. RESULTS AND ANALYSES. 6.1 Introduction. 6.2 Results of Gate Control and ...
A DEADBEAT CONTROLLER FOR BIDIRECTIONAL HIGH-FREQUENCY LINK INVERTER
TOH LEONG SOON
Universiti Teknologi Malaysia
BAHAGIAN A – Pengesahan Kerjasama* Adalah disahkan bahawa projek penyelidikan tesis ini telah dilaksanakan melalui kerjasama antara ________________________ dengan _______________________ Disahkan oleh: Tandatangan : ………………………………… Nama
: …………………………………
Jawatan
: …………………………………
Tarikh : ………………………
(Cop rasmi) * Jika penyelidikan tesis/projek melibatkan kerjasama BAHAGIAN B – Untuk Kegunaan Pejabat Sekolah Pengajian Siswazah Tesis ini telah diperiksa dan diakui oleh: Nama dan Alamat Pemeriksa Luar: Assoc. Prof. Dr. Soib Bin Taib School of Electrical and Electronic Eng., USM Enginering Campus, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia. Nama dan Alamat Pemeriksa Dalam: Dr. Awang Bin Jusoh Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Johor, Malaysia. Nama Penyelia Lain (jika ada):
Disahkan oleh Penolong Pendaftar di SPS: Tandatangan : …………………………………. Nama
: ………………………………….
Tarikh : …………………….
A DEADBEAT CONTROLLER FOR BIDIRECTIONAL HIGH-FREQUENCY LINK INVERTER
TOH LEONG SOON
A thesis submitted in fulfilment of the requirements for the award of the degree of Master of Engineering (Electrical)
Faculty of Electrical Engineering Universiti Teknologi Malaysia
APRIL 2006
iii
To my beloved parents and sister for their enduring love, encouragement, motivation, and support
iv
ACKNOWLEDGEMENTS
I would like to express my utmost gratitude and appreciation to my supervisor, Assoc. Prof. Dr. Zainal Bin Salam for his advices, motivation and support throughout this project. His consistent encouragement is invaluable in helping me to complete the work. I wish to thank all members of Energy Conversion Department (ENCON). In particular, I wish to acknowledge the Senior Technician, Mr. Yusof Bin Jamil for his support in preparing the necessary research equipments. I would also like to thank my fellow researchers – Nge Chee Lim and Tan Perng Cheng, for the fruitful discussions and sharing. Special thanks to Mr. Mohd. Zulkifli Bin Ramli for the constructive suggestions and experience sharing in hardware implementation, and the Research Assistant, Mr. Muhammad Abu Bakar Sidik for his help in building the hardware. I am also grateful to Prof. Dr. Johari Halim Shah Bin Osman, for his help in verification of several control analyses. I also wish to extend my sincere appreciation to the Technical Support Team of dSPACE for their prompt response towards technical issues of the controller board, and all in contact researchers who have provided assistance at various stages. My heartfelt appreciation also goes to the Ministry of Science, Technology and Innovation (MOSTI) for the scholarship funding. Last but not least, I am indebted to my parents and sister for their encouragement and moral support throughout my journey of education.
v
ABSTRACT
This thesis presents a Deadbeat controller for Bidirectional High-Frequency Link (BHFL) inverter. Deadbeat control technique is applied as it exhibits fast dynamic response. The proposed controller consists of inner current loop, outer voltage loop and a feedforward controller. The feedforward controller, which imposes a gain scheduling effect according to the reference signal, is used to compensate steady-state error of the system. The main property of the controller is that the current loop controller and the voltage loop controller have the same structure, and uses the same sampling period. This simplifies design and implementation of the controller. To improve overall performance of the system, disturbance decoupling networks are employed. The design takes into account the model discretisation effect. As such, accurate disturbance decoupling can be achieved. The robustness of the inverter towards load variations is thus increased. To avoid transformer saturation due to low frequency voltage envelope, an equalised Pulse Width Modulation (PWM) technique is proposed. The performances of the BHFL
inverter
with
the
proposed
controller
are
investigated
using
MATLAB/Simulink. The simulation results are compared with the conventional Proportional-Integral (PI) controller and the multirate digital controller. The feasibility of the controller is further validated by a 1kVA laboratory prototype. The DS1104 Digital Signal Processor (DSP) from dSPACE is used to implement the control algorithm. The results show that the BHFL inverter with the proposed Deadbeat controller has excellent dynamic response and low output voltage distortion (1.5%). It also performs well under cyclic step load variations, and good steady-state response under highly nonlinear loads.
vi
ABSTRAK
Tesis ini menyampaikan pengawal Deadbeat untuk Penyongsang Dwihala Frekuensi Tinggi. Teknik kawalan Deadbeat digunakan kerana ia mempunyai sambutan fana yang pantas. Pengawal yang diusulkan terdiri daripada gelung arus dalaman, gelung voltan luaran dan pengawal suap-depan. Pengawal suap-depan yang mempunyai kesan penjadualan gandaan berdasarkan isyarat rujukan digunakan untuk pampasan ralat sistem pada keadaan mantap. Ciri utama pengawal tersebut ialah pengawal gelung arus dan pengawal gelung voltan mempunyai struktur yang sama, dan menggunakan tempoh sampelan yang sama. Ini memudahkan rekabentuk dan pelaksanaan pengawal tersebut. Demi meningkatkan prestasi keseluruhan sistem, rangkaian nyahgandingan gangguan digunakan. Rekabentuk tersebut mengambil kira kesan pendiskretan model. Dengan ini, nyahgandingan gangguan yang jitu boleh dicapai. Ketegapan penyongsang terhadap perubahan beban turut dapat ditingkatkan. Demi mengelakkan ketepuan pengubah akibat voltan sampul frekuensi rendah, teknik penyamaan modulatan lebar denyut telah diusulkan. Penilaian terhadap prestasi Penyongsang Dwihala Frekuensi Tinggi dengan pengawal yang diusulkan telah dijalankan dengan menggunakan MATLAB/Simulink. Keputusan simulasi telah dibandingkan dengan pengawal Kamiran Berkadaran serta pengawal digit berbilang kadar. Kebolehlaksanaan pengawal selanjutnya disahkan melalui satu contoh dasar ujikaji berkadaran 1kVA. Pemproses Isyarat Digit (DSP) DS1104 dari dSPACE telah digunakan untuk melaksanakan algoritma pengawal. Keputusan menunjukkan bahawa Penyongsang Dwihala Frekuensi Tinggi yang dikawal oleh pengawal Deadbeat mempunyai sambutan fana yang baik, serta herotan voltan keluaran yang rendah (1.5%). Keputusannya juga amat memuaskan bawah perubahan beban langkah berkitar, dan sambutan keadaan mantap yang bagus bawah beban tak lelurus.
vii
TABLE OF CONTENTS
CHAPTER
1
2
TITLE
PAGE
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENTS
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF TABLES
xi
LIST OF FIGURES
xii
LIST OF SYMBOLS
xviii
LIST OF ABBREVIATIONS
xx
LIST OF APPENDICES
xxi
INTRODUCTION
1
1.1 Overview
1
1.2 Objective, Scope and Importance of Research
4
1.2.1 Objective of Research
4
1.2.2 Scope of Research
4
1.2.3 Importance of Research
6
1.3 Organisation of Thesis
7
LITERATURE REVIEW
9
2.1 Introduction
9
2.2 Photovoltaic (PV) Inverter Systems
10
2.3 Transformer Isolated Inverters
12
viii 2.3.1 Line-Frequency Inverters
13
2.3.2 High-Frequency Link Inverters
15
2.3.2.1 High-Frequency Link Inverter with Cycloconverter Output Stage
15
2.3.2.2 High-Frequency Link Inverter with Rectifier Output Stage 2.4 Closed Loop Control Techniques of Inverters
20
2.4.1 Proportional-Integral-Derivative (PID) Control
21
2.4.2 Hysteresis Control
24
2.4.3 Sliding Mode Control
26
2.4.4 Repetitive Control
28
2.4.5 Fuzzy Logic and Neural Network Control
30
2.4.6 Deadbeat Control
34
2.5 Summary 3
18
37
DEADBEAT CONTROLLER FOR BIDIRECTIONAL HIGH-FREQUENCY LINK (BHFL) INVERTER
38
3.1 Introduction
38
3.2 Description of BHFL Inverter and System Operating Principle
4
39
3.3 Modelling of BHFL Inverter
40
3.4 Design of the Proposed Deadbeat Controller
44
3.4.1 Current Loop Controller
45
3.4.2 Voltage Loop Controller
48
3.4.3 Feedforward Controller
51
3.5 Robustness of the Designed Controller
52
3.6 Summary
53
SYSTEM MODELLING AND SIMULATION
54
4.1 Introduction
54
4.2 System Modelling via MATLAB/Simulink
55
4.2.1 Gate Drives
55
ix 4.2.2 BHFL Inverter
57
4.2.3 Feedback Signal Conditioning
58
4.2.4 Multiloop Controller for BHFL Inverter
59
4.2.4.1 Conventional PI Controller
59
4.2.4.2 Multirate Digital Controller
61
4.2.4.3 Proposed Deadbeat Controller
65
4.2.5 Test Loads
5
4.3 Summary
67
HARDWARE IMPLEMENTATION
68
5.1 Introduction
68
5.2 BHFL Inverter
70
5.2.1 Gate Drive Circuit
71
5.2.2 Power Circuit
72
5.2.3 Feedback Circuit
73
5.3 DS1104 Digital Signal Processor (DSP) Board
74
5.3.1 Gate Control Signals Generation
78
5.3.2 Feedback Signal Conditioning
80
5.3.3 Multiloop Controller for BHFL Inverter
87
5.3.3.1 Multirate Digital Controller
88
5.3.3.2 Proposed Deadbeat Controller
90
5.4 Critical Load Test-Rigs
6
66
96
5.4.1 Triac Load
96
5.4.2 Full-Bridge Rectifier Load
97
5.5 Summary
98
RESULTS AND ANALYSES
99
6.1 Introduction
99
6.2 Results of Gate Control and Signal Conditioning
100
6.3 Simulation Results of Conventional PI Controller
106
6.4 Simulation and Experimental Results of Multirate Digital Controller
109
x 6.5 Simulation and Experimental Results of Proposed Deadbeat Controller
113
6.6 Comparison on Performances of Multirate Digital Controller and Proposed Deadbeat Controller
7
116
6.7 Summary
117
CONCLUSION AND FUTURE WORK
118
7.1 Conclusion
118
7.2 Suggestions for Future Work
120
REFERENCES
121
APPENDIX A-C
130
LIST OF PUBLICATIONS
147
xi
LIST OF TABLES
TITLE
TABLE NO.
PAGE
2.1
Fuzzy Rule Table
32
5.1
Function table of JK flip-flop operating as frequency divider
80
Scaling between analogue input voltage and return value of ADCs
81
6.1
Parameters of BHFL inverter
100
6.2
Components of test signal for digital filter
103
6.3
Parameters of conventional PI controller
106
6.4
Performances of BHFL inverter with conventional PI controller
108
6.5
Parameters of multirate digital controller
109
6.6
Parameters of proposed Deadbeat controller
113
6.7
Performances of multirate digital controller and proposed Deadbeat controller
117
5.2
xii
LIST OF FIGURES
TITLE
FIGURE NO.
PAGE
2.1
PV inverter systems (a) stand-alone (b) grid-connected
10
2.2
Four-quadrant operation of inverter (a) block diagram of inverter (b) output waveforms and corresponding modes of operation
11
Block diagram of transformer isolated inverters (a) line-frequency inverter (b) high-frequency link inverter
12
2.4
Half-bridge inverter
13
2.5
Full-bridge inverter
14
2.6
Push-pull inverter
14
2.7
Conventional high-frequency link inverter with cycloconverter output stage
16
2.8
Typical waveforms of cycloconverter
16
2.9
High-frequency link inverter with NCPA control cycloconverter
17
Key waveforms at the principal conversion stages of highfrequency link inverter with NCPA control cycloconverter
17
Conventional high-frequency link inverter with rectifier output stage
18
2.12
Typical waveforms of “dc-dc converter”
18
2.13
High-frequency link inverter with active rectifier output stage
19
Key waveforms at the principal conversion stages of highfrequency link inverter with active rectifier output stage
20
2.3
2.10 2.11
2.14
xiii 2.15
A typical PID control system
21
2.16
Continuous-time PID controller
22
2.17
Discrete-time PID controller
22
2.18
Typical waveforms of hysteresis control
24
2.19
Band shapes of hysteresis controllers (a) fixed-band hysteresis control (b) sinusoidal-band hysteresis control
25
2.20
A 2-D phase plane of typical SMC
26
2.21
Basic configurations of repetitive control system (a) cascaded type (b) feedforward type
29
2.22
Basic configuration of fuzzy logic controller
30
2.23
Triangular shape fuzzy membership functions
31
2.24
Structure of an artificial neuron
32
2.25
Feedforward multilayer neural network architecture
33
2.26
The mapping of s-plane and z-plane
34
2.27
A typical Deadbeat control system
35
3.1
Circuit configuration of the Bidirectional High-Frequency Link inverter
39
Key waveforms at the principal conversion stages of BHFL inverter
40
3.3
Equivalent circuit of the BHFL inverter
41
3.4
Continuous-time model of the BHFL inverter
42
3.5
Discrete-time model of the BHFL inverter
43
3.6
Proposed Deadbeat controller for the BHFL inverter
44
3.7
Current controller (a) current loop (b) simplified current loop
46
Voltage controller (a) voltage loop (b) simplified voltage loop
49
Voltage loop with feedforward controller
51
3.2
3.8 3.9
xiv 3.10
Trajectories of the closed-loop pole with L change
52
4.1
Complete simulation model of closed-loop BHFL inverter
55
4.2
Gate control signals for the BHFL inverter
56
4.3
Detail of “Gate drives” block
56
4.4
Detail of “BHFL inverter” block
57
4.5
Detail of “Active rectifier” block
57
4.6
Detail of “Signal conditioning” block
58
4.7
Conventional PI controller
60
4.8
Detail of “PI controller” block
60
4.9
Multirate digital controller
61
4.10
Inner loop controller (a) current loop (b) simplified current loop
62
Outer loop controller (a) voltage loop (b) simplified voltage loop
64
4.12
Proposed Deadbeat controller
65
4.13
Detail of (a) “Voltage disturbance decoupling network” block (b) “Current disturbance decoupling network” block
66
Test loads (a) resistive load (b) inductive load (c) triac load (d) rectifier load
67
5.1
Photograph of laboratory experimental set-up
69
5.2
Block diagram of overall system configuration
69
5.3
Photograph of BHFL inverter (a) top view – gate drive module (b) bottom view – power circuit module
70
5.4
Block diagram of gate drive circuit
71
5.5
Dead-time generator and its corresponding timing diagram
72
5.6
Connection between sensors and power circuit
73
5.7
DS1104 DSP board
74
4.11
4.14
xv 5.8
Architecture of DS1104 DSP board
75
5.9
Interface panel between DS1104 and BHFL inverter
76
5.10
Flowchart of implementing real-time applications using DS1104 DSP
77
5.11
Complete RTI model of the proposed Deadbeat controller
78
5.12
Gate control signals for the BHFL inverter
79
5.13
JK flip-flop operating as frequency divider (a) circuit configuration (b) timing diagram
79
Digital filter design procedure using bilinear transformation method
81
5.15
Magnitude response of first-order digital filter
82
5.16
Equivalent cut-off specifications of low-pass digital and analogue filter
83
5.17
Magnitude response of the designed filter
86
5.18
Canonical realisation form of first-order IIR filter
87
5.19
Complete RTI model of the multirate digital controller
89
5.20
RTI model of the multirate digital controller
89
5.21
C code programming flowchart of the proposed control algorithm
90
5.22
RTI model of the proposed Deadbeat controller
91
5.23
Timing diagram of vHF (a) before pulse equalisation (b) after pulse equalisation
92
5.24
Timing diagram of equalised pulse PWM generation
93
5.25
Flowchart of equalised pulse generation
94
5.26
Implementation of pulse equalisation in RTI
95
5.27
GUI constructed for experiment in ControlDesk
95
5.28
Photograph of triac load test-rig
97
5.29
Circuit diagram of triac load test-rig
97
5.14
xvi 5.30
Photograph of full-bridge rectifier load test-rig
98
5.31
Circuit configuration of 90MT80KB used as single phase rectifier
98
6.1
Simulation result – gate control signals
101
6.2
Experimental result – gate control signals
101
6.3
Simulation result – gating signals for power switches
102
6.4
Experimental result – gating signals for power switches
103
6.5
Simulation result – test signal before and after digital filter
104
6.6
Experimental result – test signal before and after digital filter
104
Experimental result – frequency spectrum (a) before digital filter (b) after digital filter
105
6.8
Output waveforms under resistive load
106
6.9
Output waveforms under inductive load
107
6.10
Output waveforms under step resistive load change
107
6.11
Output waveforms under rectifier load
108
6.12
Multirate digital controller – output waveforms under resistive load (a) simulation result (b) experimental result
109
Multirate digital controller – output waveforms under inductive load (a) simulation result (b) experimental result
110
Multirate digital controller – output waveforms under step load change (a) simulation result (b) experimental result
110
Multirate digital controller – zoom in view of output waveforms under step load change (experimental result)
111
Multirate digital controller – output waveforms under triac load (a) simulation result (b) experimental result
111
Multirate digital controller – output waveforms under rectifier load (a) simulation result (b) experimental result
112
Proposed Deadbeat controller – output waveforms under resistive load (a) simulation result (b) experimental result
113
6.7
6.13 6.14 6.15 6.16 6.17 6.18
xvii 6.19
Proposed Deadbeat controller – output waveforms under inductive load (a) simulation result (b) experimental result
114
Proposed Deadbeat controller – output waveforms under step load change (a) simulation result (b) experimental result
114
Proposed Deadbeat controller – zoom in view of output waveforms under step load change (experimental result)
115
Proposed Deadbeat controller – output waveforms under triac load (a) simulation result (b) experimental result
115
Proposed Deadbeat controller – output waveforms under rectifier load (a) simulation result (b) experimental result
116
B.1
A single dc-dc converter (gate drive power supply)
135
B.2
Gate driver
136
6.20
6.21 6.22 6.23
xviii
LIST OF SYMBOLS
C
-
Filter capacitor
E, e
-
Error signal
fc
-
Filter cut-off frequency
fnet
-
Transfer function of artificial neuron
fs
-
Sampling frequency
fsw
-
Switching frequency
ic
-
Filter capacitor current
id
-
Current disturbance
idc
-
DC source current
iL
-
Filter inductor current
io
-
Output current
ior
-
Rectified output current
iref
-
Current reference
KD
-
Derivative gain of PID controller
Ki
-
Current loop controller gain
KI
-
Integral gain of PID controller
KP
-
Proportional gain of PID controller
Kv
-
Voltage loop controller gain
L
-
Filter inductor
N1, N2
-
Transformer winding
Oj
-
Output of artificial neuron
Po, po
-
Output power
R, r
-
Reference signal
rc
-
Equivalent Series Resistance of filter capacitor
Rj
-
Net input of artificial neuron
rL
-
Equivalent Series Resistance of filter inductor
xix T, Ts
-
Sampling period
td
-
Dead-time
Ti
-
Current loop sampling period
ton
-
Switch on period
Tsw
-
Switching period
Tv
-
Voltage loop sampling period
U, u
-
Control signal or control variable
vcl
-
Output voltage of cycloconverter
Vd
-
DC link voltage
vd
-
Voltage disturbance
Vdc
-
DC source voltage
vHF
-
High-frequency voltage
vi
-
Input voltage of converter
vo
-
Output voltage
vor
-
Rectified output voltage
vpwm
-
Gate signal for high-frequency PWM bridge
vpwm_rect
-
Rectified PWM voltage
vr
-
High-frequency rectified voltage
vrect
-
Rectified sinusoidal voltage
vref
-
Voltage reference
vs
-
Gate signal for active rectifier
vu
-
Gate signal for polarity-reversing bridge
Wij
-
Weighting elements of artificial neuron
xi
-
Input of artificial neuron
Y, y
-
System output
Z
-
Output impedance
z −1
-
Unit delay
δ
-
Sliding surface or sliding line
θj
-
Bias in artificial neuron
ω
-
Cut-off frequency of low-pass filter
ωo
-
Oscillating frequency
xx
LIST OF ABBREVIATIONS
ADC
-
Analogue-to-Digital Converter
BHFL
-
Bidirectional High-Frequency Link
COA
-
Centre of Area
DSMC
-
Discrete-time Sliding Mode Control
DSP
-
Digital Signal Processor
EMF
-
Electromotive Force
EMI
-
Electromagnetic Interference
GUI
-
Graphical User Interface
IGBT
-
Insulated Gate Bipolar Transistor
IIR
-
Infinite Impulse Response
MOM
-
Mean of Maximum
MOSFET
-
Metal Oxide Semiconductor Field Effect Transistor
MPPT
-
Maximum Power Point Tracking
PI
-
Proportional-Integral
PID
-
Proportional-Integral-Derivative
PLL
-
Phase Lock Loop
PV
-
Photovoltaic
PWM
-
Pulse Width Modulation
RTI
-
Real-Time Interface
SMC
-
Sliding Mode Control
SPWM
-
Sinusoidal Pulse Width Modulation
THD
-
Total Harmonic Distortion
TTL
-
Transistor-Transistor Logic
UPS
-
Uninterruptible Power Supply
VSC
-
Variable Structure Control
VSI
-
Voltage Source Inverter
xxi
LIST OF APPENDICES
APPENDIX A
TITLE
PAGE
Discretisation of Continuous-Time State-Space Equations
130
B
Schematic Diagram of Gate Drive Circuit
135
C
DS1104 DSP Source Code Listing
137
CHAPTER 1
INTRODUCTION
1.1
Overview With the growing energy demand, increasing global environmental issues,
and depleting energy resources (coal, oil and gas), the need to develop and utilise new sources of energy seems inevitable. For these reasons, renewable energy resources such as solar, wind, biomass and geothermal, appear as important alternative energy options. Solar energy, one of the few clean and abundant renewable energy resources, has come into the limelight in recent years. Research in this area is going on progressively, even in countries with limited sunshine days per year. Blessed with year-rounded sunshine, the solar energy is particularly a feasible energy source in Malaysia. It is important to note that the Ministry of Science, Technology and Innovation, Malaysia (MOSTI)1 has classified the solar power for residential application as the high priority energy research area [1]. To harness the solar energy, various energy conversion technologies are required. Photovoltaic (PV) panels, or commonly known as solar panels, are devices used to convert sunlight into electricity. The acronym PV stands for photo (light) and voltaic (electricity), whereby sunlight photons free electrons from the atoms of the panels and creates a voltage difference. Since the PV panels convert sunlight into electricity in the form of direct current (dc), while most electrical devices for residential applications require alternating current (ac), dc-ac power conversion is 1
Formerly known as the Ministry of Science, Technology and the Environment, Malaysia (MOSTE).
2 needed. This can be realised by power converter known as inverter. In solar energy systems, PV inverter is the power converter used specifically to convert the dc power obtained from PV panels into ac power. From the economic point of view, although the cost of PV power is relatively high as compared to other renewable energy sources such as wind and biomass, it has decreased from more than $50/W in the early 1980s to about $5/W today [2]. This can be attributed to the economics of scale and subsidies from the government, as that of Japan and Germany [2], [3]. The future plan from utility providers to “purchase” electricity (“buy back” policy) generated by users, for example the Net Metering System [4], has further encouraged the development of grid-connected PV systems. Besides, the PV panels can be designed as part of the roof structure, replacing the conventional ceramic or concrete-based roof tiles. In view of these advantages, PV is envisaged as a viable economics proposition of the future. As the solar energy for residential application is gaining considerable interest, there have been numerous PV inverter topologies proposed in the literature [5]-[12]. Basically, there are two types of PV inverters, namely the stand-alone PV inverter and the grid-connected PV inverter. In the stand-alone mode, the inverter operates independently of the grid, and is normally equipped with batteries for energy storage. On the other hand, the grid-connected PV inverter operates in parallel with the grid without battery storage. If one were to consider the application of PV for residential, it is desired that the inverter be able to operate in both operation modes, together with the Uninterruptible Power Supply (UPS) features. Furthermore, the future trend of inverter design is high efficiency, light weight, small size and low cost. In order to achieve these requirements, high-frequency link inverters with bidirectional power flow capability have been proposed [13]-[17]. In residential PV applications, the types of loads connected to the PV inverter are rather uncertain. Nonlinear loads such as rectifiers in computer systems could cause intense distortion in the output current and voltage waveform. Therefore, a high performance inverter is required to maintain the desired sinusoidal output voltage waveform over all loading conditions and transients. This is especially important if the PV inverter is operated in the stand-alone mode. Generally, the
3 performance of an inverter is evaluated in terms of its dynamic response over sudden load changes and steady-state output voltage waveform distortion. The requirements can only be achieved by employing closed-loop control. Over the past decades, several control techniques have been proposed for closed-loop regulation of inverters [18]-[40]. Although most of the control techniques were developed based on linefrequency inverters, they can be adopted in high-frequency link inverters. In addition, a complete PV system may be incorporated with Maximum Power Point Tracking (MPPT) controller [8], [11], which is used to transfer maximum available power from the PV panels to the PV inverter. Traditionally, closed-loop inverter systems have been implemented using analogue components, such as resistors, capacitors and operational amplifiers. Today, with the explosive growth and expanding efficiency of digital technology, digital-based inverter system is getting more prevalent over its analogue-based counterpart. Microprocessors and Digital Signal Processors (DSPs) have been used for Pulse Width Modulation (PWM) pulse generation and real-time controller of inverter systems. In fact, digital-based systems have many advantages over analoguebased systems. For instance, digital-based systems are programmable thus offering flexibility in system modifications. In contrast, analogue-based systems depend on the variation of constant condition of parts. Hence, the complicated parameters tuning is avoided in digital-based systems. This makes the design process of closedloop controller for inverter systems much easier, enabling shorter time of system development. Moreover, digital-based systems are robust towards environmental effects and ageing drift, tangibly enhance the system performance. Therefore, adopting digital technique is an extra motivation to the design and development of closed-loop inverter systems.
4 1.2
Objective, Scope and Importance of Research
1.2.1 Objective of Research The objective of this research is to propose, design and implement a digital controller for closed-loop regulation of Bidirectional High-Frequency Link (BHFL) inverter. The BHFL inverter topology was originally proposed by Ramli et al. [17]. The controller scheme chosen is Deadbeat control, to provide fast dynamic response and good steady-state output voltage waveform.
1.2.2 Scope of Research There are many control functions in a PV inverter system, such as inverter voltage regulation, power factor control, phase synchronisation with grid voltage, MPPT, and other protection functions. As the developed BHFL inverter is meant for both grid-connected mode and stand-alone mode with UPS features, a high performance closed-loop controller is needed. The controller must fulfil the stringent requirements of voltage regulation under all loading conditions, particularly in standalone mode. A high performance controller can also be operated in grid-connected mode by incorporating the MPPT controller, Phase Lock Loop (PLL) [8], [41] and islanding function. The scope of this research is limited to the following items for closed-loop regulation of the BHFL inverter: i.
Study of various control techniques for PWM inverters Prior knowledge of control systems, such as design considerations, analysis methods and practical implementation aspects is acquired [42]-[46]. Several previous works on closed-loop control techniques for high performance inverters are reviewed [18]-[40]. The critical loads in residential PV applications are also identified and their characteristics are studied.
5 ii.
Selecting appropriate control technique for the BHFL inverter Deadbeat control technique has been selected as it exhibits fast dynamic performance and good steady-state response of the output voltage.
iii.
Analytical modelling of the BHFL inverter and controller design A dynamic model of the BHFL inverter has been derived using the statespace averaging method [47]. The Deadbeat controller is then designed based on the state-space model.
iv.
Computer simulation To verify the performance of the designed controller, a complete simulation model of the closed-loop BHFL inverter is developed. The computer simulation package used is MATLAB/Simulink2. The system performance is verified under various loads and conditions.
v.
Hardware implementation To validate the feasibility of the proposed control technique, a hardware prototype is constructed. The tasks include selecting the appropriate digital processor, designing the power circuit, gate drivers, feedback and signal conditioning circuits, and implementing the control algorithm. The selected digital processor is the DS11043 DSP board. The critical load test-rigs are also constructed.
vi.
System verification and improvement Laboratory experiments are carried out on the system under various loads and conditions. Necessary modifications and fine-tuning are made to further improve the performance of the system.
2 3
MATLAB is the trademark of The MathWorks, Inc. DS1104 is provided by dSPACE GmbH.
6 1.2.3 Importance of Research The decreasing cost of PV power has been the main impetus of developing PV systems. Looking at the full potential of residential PV system in Malaysia, research and development investment has been made by the government. Some of the
early
PV
systems
are
being
applied
for
rural
electrification
and
telecommunication [3], [48]. The PV is anticipated to play a more prominent role once the grid-connected system is well-established with the legal framework for users selling power to the utility provider is in place. In a complete PV system, the inverter is normally equipped with closed-loop controller. The controller plays a vital role in maintaining the sinusoidal output voltage waveform over all loading conditions. Hence, there is a need to develop a high performance controller for the BHFL inverter. Although many modern control techniques have been proposed in the literature, they are mainly developed for linefrequency inverters [25]-[38]. On the other hand, the published works on highfrequency link inverters only utilising conventional control techniques [7], [8], [13], [14], [16]. As the inverter and closed-loop controller work together as a complete system, it is of preference to apply the modern control techniques into highfrequency link inverters. In this research, the Deadbeat control technique, which has been applied in line-frequency PWM inverters since 1980s [33], is adopted for closed-loop regulation of the BHFL inverter. Besides verifying the feasibility of the control technique on high-frequency link inverter, it also bridges the gap between researches in these two areas. Deadbeat control is selected for closed-loop regulation of the BHFL inverter because it provides excellent dynamic response. The proposed controller consists of inner current loop controller, outer voltage loop controller and feedforward controller. The controller has same structure for the current and voltage loop controllers, which simplifies design and implementation. To improve overall performance of the system, additional decoupling networks are employed. A voltage disturbance decoupling network is added to the voltage loop controller. Similarly, a current disturbance decoupling network is added to the current loop controller. The decoupling networks take into account the model discretisation effect. Therefore, improved system
7 robustness towards load variations is envisaged. In the proposed control technique, there is no observer or estimator applied. This is an advantage because inclusion of observer might introduce estimation errors. The implemented controller possesses fast dynamic response with good steady-state response under all loading conditions. This paves a way to Deadbeat control to be applied in high-frequency link inverters, which hitherto have not been applied. With necessary modifications, the BHFL inverter with Deadbeat controller is suitable for stand-alone and grid-connected residential PV applications.
1.3
Organisation of Thesis This thesis is organised into seven chapters. The content of these chapters are
outlined as follows: •
Chapter 2 provides an overview of various line-frequency and high-frequency link inverter topologies. Closed-loop control techniques for inverters are also presented. The merits and drawbacks of the control techniques are discussed.
•
Chapter 3 describes the BHFL inverter and its operating principle. The analysis and design of the proposed Deadbeat controller are explained in considerable detail. The robustness of the designed controller against parameter mismatches is also investigated.
•
Chapter 4 presents the system modelling of the BHFL inverter with the proposed Deadbeat controller using MATLAB/Simulink simulation package. Descriptions are given on the modelling procedures using blocksets from MATLAB/Simulink libraries.
•
Chapter 5 describes the laboratory experimental set-up. Brief explanation is given on the power circuit and gate drives. Detailed description is provided on the implementation of the proposed controller using DS1104 DSP. This
8 includes the design and realisation of digital filters, and introduction of pulse equalisation technique into the proposed Deadbeat controller. •
Chapter 6 evaluates the performances of the proposed controller. This is performed in comparison with the conventional PI controller and the multirate digital controller. Various types of loads are tested on the system. The simulation and experimental results are provided.
•
Chapter 7 concludes the works undertaken and highlights the contributions of this research. Several suggestions are provided as possible directions for future work.
CHAPTER 2
LITERATURE REVIEW
2.1
Introduction Inverters are power converters that convert dc to ac. In residential solar
energy systems, PV inverters are used to transfer dc power from PV panels to ac loads. There are basically two types of PV inverters, i.e. stand-alone PV inverter and grid-connected PV inverter. To provide galvanic isolation between the dc source and the ac load, isolation transformer is employed, either of line-frequency or highfrequency construction. “All-rounded” PV inverter system has been the trend of late. It is desirable that the PV inverter system is able to operate in the grid-connected mode in normal condition, and the stand-alone mode with UPS features in case of grid failure. Closed-loop controller is the key element that ensures desired sinusoidal output voltage waveform over all loading conditions. This is especially important if the PV inverter is operated in the stand-alone mode. This chapter provides an overview of PV inverter systems and transformer isolated inverters. Various line-frequency and high-frequency link inverter topologies are presented. Closed-loop control techniques to achieve good dynamic response and low harmonic distortion are also reviewed. The advantages and drawbacks of respective control techniques are discussed. In this research, a Deadbeat controller is proposed for closed-loop regulation of the BHFL inverter. The justifications for selection of Deadbeat control technique are also outlined.
10 2.2
Photovoltaic (PV) Inverter Systems PV inverter systems normally consist of PV panels and PV inverter. The PV
panels generate dc power when sunlight falls on them. The dc power generated is subsequently converted into ac power by the PV inverter. Basically, there are two types of PV inverters, namely the stand-alone inverter and the grid-connected inverter. The stand-alone inverter operates independently of the grid, as shown in Figure 2.1(a). Therefore, it provides both active and reactive power to the load. On the other hand, the grid-connected inverter operates in parallel with the grid, as shown in Figure 2.1(b). In this configuration, the grid is used to balance the power flow between the dc source and the ac load. For example, the inverter provides active power to the load, while the reactive power is provided by the grid. As such, the stand-alone inverter must be a four-quadrant inverter, capable to handle bidirectional power flow. In contrast, the grid-connected inverter only needs to support unidirectional power flow from dc source to ac load, thus power switches without anti-parallel diode can be used. This helps in cost reduction of the system.
PV panels
DC link capacitor
PV inverter
Load
(a)
PV panels
DC link capacitor
PV inverter
AC contactors Load Utility/grid
(b) Figure 2.1 : PV inverter systems (a) stand-alone (b) grid-connected
11 The four-quadrant operation [47] of an inverter is shown in Figure 2.2. It is assumed that the inverter supplies an inductive load such as ac motor, where output current io lags output voltage vo, as shown in Figure 2.2(b). The output waveforms of Figure 2.2(b) shows that in mode I, vo and io are both positive, whereas in mode III, vo and io are both negative. Therefore, in mode I and III, the instantaneous power flow, p o = vo io is from dc side to ac side, corresponding to an inverter mode of operation. In mode II and IV, vo and io are of opposite signs, thus po flows from ac side to dc side, corresponding to a rectifier mode of operation. Inverter
idc
+
io
+
Vdc
vo
-
-
(a) vo
io io
II Rectifier t III Inverter
IV
I
II
0
I Inverter vo IV Rectifier
III
(b) Figure 2.2 : Four-quadrant operation of inverter (a) block diagram of inverter (b) output waveforms and corresponding modes of operation
12 2.3
Transformer Isolated Inverters Transformer isolated inverters are normally used in PV inverter systems.
Besides providing galvanic isolation between dc side and ac side for users’ safety, the transformer also steps up the voltage to a level suitable for residential ac loads. Two methods of providing these features are shown in Figure 2.3. In Figure 2.3(a), the basic single-stage inverter is used, and the isolation is obtained through the linefrequency (50Hz) transformer. In Figure 2.3(b), the high-frequency link inverter with two conversion stages is used, where the isolation is obtained through the highfrequency transformer. The following subsections provide more detail descriptions on the line-frequency inverters and high-frequency link inverters. Single-stage converter
Line-frequency transformer
Vdc
Load
(a) Input-stage converter
High-frequency transformer
Output-stage converter
Vdc
Load
(b) Figure 2.3 : Block diagram of transformer isolated inverters (a) line-frequency inverter (b) high-frequency link inverter
13 2.3.1 Line-Frequency Inverters In general, there are three basic configurations of line-frequency inverters – half-bridge inverter, full-bridge inverter and push-pull inverter [47]. These inverters convert the dc source voltage into high-frequency pulses, depending on the switching scheme. They can be operated in a Sinusoidal Pulse Width Modulation (SPWM) or a square-wave mode. Then, the high-order harmonics are filtered by the LC low-pass filter to obtain sinusoidal ac output voltage. The isolation is obtained via linefrequency transformer. A half-bridge inverter is shown in Figure 2.4. Two equal capacitors are connected across the dc source with their junction as the mid-potential point, providing a voltage of
Vdc across each capacitor. This circuit configuration is also 2
known as one-leg inverter, where S1 and S2 are turned on alternately with sufficient blanking time to avoid short circuit across the dc source. Blanking time is the short time interval where both power switches are turned off simultaneously.
idc
Vdc
+ Vdc 2 -
S1
D1
Low-pass filter
Line-frequency transformer
L C
+ Vdc 2 -
io + vo
Load
S2
D2
Figure 2.4 : Half-bridge inverter A full-bridge inverter, also known as two-leg inverter is shown in Figure 2.5. This configuration is the most commonly used inverter, especially in higher power ratings. With the same dc input voltage, the maximum output voltage of full-bridge inverter is twice that of half-bridge inverter. Similar to the half-bridge inverter, S1 and S2 should not be turned on at the same time, nor should S3 and S4. Otherwise, a short circuit across the dc source would occur.
14 Line-frequency transformer
idc S1
D1
S3
D3
Low-pass filter
io
L
Vdc
+ vo
C
Load
S2
D2
S4
D4
Figure 2.5 : Full-bridge inverter The circuit configuration of push-pull inverter is shown in Figure 2.6. This configuration has only two power switches with a common ground. Unlike halfbridge inverter, the mid-potential point between two capacitors, which is normally not available, is eliminated. Push-pull inverter requires a transformer with centretapped primary. The advantage of this configuration is only one power switch conducts at any instant of time, reducing switching loss. However, the power switches used must be of twice the voltage rating for half-bridge inverter or fullbridge inverter.
Line-frequency transformer with centre-tapped primary
Low-pass filter L
idc
C
io + vo
Load
Vdc S1
D1
S2
D2
Figure 2.6 : Push-pull inverter All the above mentioned inverter configurations have bidirectional power flow capability, where the anti-parallel diodes provide a path for current flow in case of reactive load. However, the use of line-frequency transformer increases the size, weight and ultimately cost of the system. This makes the high-frequency link inverters getting more popular as an effective solution to these drawbacks.
15
2.3.2 High-Frequency Link Inverters High-frequency link inverters normally consist of two conversion stages. It is more complex than line-frequency inverters. However, high-frequency link inverters overcome the shortcomings of line-frequency inverters, because the isolation is obtained via high-frequency transformer. Therefore, high-frequency link inverters are preferred for applications that require limited space and weight. Generally, the high-frequency link inverters can be categorised into two main topologies – high-frequency link inverter with cycloconverter output stage, and highfrequency link inverter with rectifier output stage. These topologies will be discussed in the following text.
2.3.2.1 High-Frequency Link Inverter with Cycloconverter Output Stage Cycloconverter is a frequency changer that converts ac power at one frequency to another frequency by ac-ac conversion [49]. Figure 2.7 shows the conventional high-frequency link inverter with cycloconverter output stage. The cycloconverter is essentially a pair of thyristor controlled bridge rectifiers. For one cycle of line-frequency sinusoidal output voltage, the P-converter is operated for the positive half cycle, and N-converter is operated for the negative half cycle. The instantaneous output voltage is determined by the firing angle of the controlled bridge rectifiers. Figure 2.8 shows the typical waveforms of cycloconverter. It is assumed that the input voltage of cycloconverter, vi is high-frequency sinusoidal voltage. This configuration has bidirectional power flow capability, depending on the direction of load current. The cycloconverter output is derived directly from the ac source. However, the maximum output frequency is limited to only about one-third of the source frequency. With the advancements in power devices technology, fast-switching power transistors are taking over thyristors based cycloconverter. Besides, more complex switching schemes can be applied to improve the system efficiency and
16 reduce the harmonic contents of the output voltage. Figure 2.9 shows a highfrequency link inverter with cycloconverter output stage using bipolar transistors and fast recovery diodes. This topology employs natural-commutation phase angle (NCPA) control for the cycloconverter stage [15].
Cycloconverter
idc
High-frequency inverter
High-frequency transformer
P-converter +
+ vi -
Vdc
N-converter
vcl Low-pass filter
io
L
+ vo
C
Load
-
Figure 2.7 : Conventional high-frequency link inverter with cycloconverter output stage vi
t
0
vcl
vo αn t
0 αp
0 0
P-converter
t N-converter
Figure 2.8 : Typical waveforms of cycloconverter
t
17 High-frequency transformer High-frequency square-wave bridge
idc
S1
S3
Vdc
+ vHF S2
Cycloconverter SAU+
SAV-
SAU-
SAV+
+ vi -
S4
Low-pass filter +v - cl
SBU-
SBV+
SBU+
SBV-
io + vo -
L C
Load
Figure 2.9 : High-frequency link inverter with NCPA control cycloconverter In Figure 2.9, the high-frequency square-wave bridge is switched to construct a high-frequency square-wave voltage. At the cycloconverter stage, the sinusoidal output voltage is obtained by “chopping” the high-frequency square-wave voltage, and filtered by low-pass filter. The key waveforms at the principal conversion stages are shown in Figure 2.10. vi
0
t
vcl
vo
0
t
Figure 2.10 : Key waveforms at the principal conversion stages of high-frequency link inverter with NCPA control cycloconverter High-frequency link inverter with cycloconverter output stage converts dc into ac with the cycloconverter operated as frequency changer. However, this configuration has several disadvantages – high switching losses as all the power switches are operated at high frequency, and inherent problem of voltage surge occurrence resulting in additional voltage clamp circuits or complex switching scheme [14], [15].
18
2.3.2.2 High-Frequency Link Inverter with Rectifier Output Stage The conventional high-frequency link inverter with rectifier output stage is shown in Figure 2.11. In this scheme, the dc source voltage is converted into highfrequency ac voltage, vHF by the high-frequency PWM bridge at a fixed duty cycle. On the transformer secondary side, the bridge rectifier is used to rectify vHF into high-frequency dc voltage, vr. Through the dc filter, vr is converted back to a constant dc voltage, Vd. Thus, this topology is also known as “dc-dc converter” type. Then, the line-frequency sinusoidal output voltage, vo is obtained by basic dc-ac conversion, depending on the switching scheme of the high-frequency SPWM bridge. The typical waveforms of “dc-dc converter” are shown in Figure 2.12.
dc
High-frequency ac
idc
Unidirectional power flow dc
High-frequency transformer High-frequency Bridge PWM bridge rectifier
High-frequency SPWM bridge
DC filter +
L
+
N1:N2
Vdc
+ vHF -
vr
C
-
Line-frequency ac
Vd
Low-pass filter + L vpwm C -
io + vo Load -
-
Figure 2.11 : Conventional high-frequency link inverter with rectifier output stage vHF Vdc
t
vr ⎛ N2⎞ Vdc ⎜ ⎟ ⎝ N1 ⎠
Vd ton
t
Tsw 2
Figure 2.12 : Typical waveforms of “dc-dc converter”
19 The conventional “dc-dc converter” type has several disadvantages, such as unidirectional power flow and usage of additional dc filter, which adds to the size of system. In residential PV applications, it is desirable to have a system featuring bidirectional power flow with compact size. A topology with these features has been proposed by Koutroulis et al. [16]. The circuit configuration is shown in Figure 2.13. This topology replaces the diode bridge rectifier with active rectifier, which enables bidirectional power flow. Besides, SPWM switching scheme is adopted for the primary side PWM bridge.
Bidirectional power flow High-frequency dc High-frequency ac
dc
idc
High-frequency transformer High-frequency Active PWM bridge rectifier S1
Sa
S3
Line-frequency ac
Polarity-reversing bridge Sa
+ Sb
Low-pass filter
Sb
N1:N2
Vdc
+ vHF S2
S4
+ vpwm -
vr Sa
Sa
Sb
L
C
io + vo -
Load
Sb
-
Figure 2.13 : High-frequency link inverter with active rectifier output stage In Figure 2.13, the dc source voltage, Vdc is converted into high-frequency ac voltage, vHF by the high-frequency PWM bridge. On the transformer secondary side, the active rectifier is used to rectify vHF into high-frequency dc voltage, vr. Then, the polarity-reversing bridge is used to unfold vr at the second half cycle of linefrequency ac. Through the LC low-pass filter, high-order harmonics are filtered, obtaining the sinusoidal output voltage, vo. The key waveforms at the principal conversion stages are shown in Figure 2.14. The high-frequency link inverter with active rectifier output stage has bidirectional power flow capability. It eliminates the large dc filter used in the conventional topology. Besides, the switching scheme is direct and simple, with the polarity-reversing bridge operated at line-frequency. Therefore, the switching losses are relatively low as compared to the cycloconverter type.
20 vHF Vdc
t vr
⎛ N2⎞ Vdc ⎜ ⎟ ⎝ N1 ⎠ vpwm
t
t vo t
Figure 2.14 : Key waveforms at the principal conversion stages of high-frequency link inverter with active rectifier output stage
2.4
Closed-Loop Control Techniques of Inverters Closed-loop controller of an inverter serves two main purposes. Firstly, to
synthesise a sinusoidal steady-state output voltage waveform under all loading conditions. Secondly, to ensure high disturbance rejection capability, where the inverter will return to the desired operating state in shortest time after a disturbance, such as sudden load change during start-up and lost of load. Traditionally, analogue-based controller is used. It can achieve good dynamic response and low harmonic distortion. However, as it is a hardwired solution, modification or upgrade in the design is difficult. Besides, analogue controller is also limited to simpler control algorithms from classical control theory. With the inherent robustness and flexibility in system modification, digital controller is gradually replacing the analogue controller in power converter applications. It enables modern control techniques to be implemented using microprocessors or DSPs.
21
2.4.1 Proportional-Integral-Derivative (PID) Control Proportional-Integral-Derivative (PID) control is the most commonly used controller in many industrial closed-loop systems [43]. This is due to its simple structure that can be easily understood and practically implemented, both in analogue and digital. Figure 2.15 shows a block diagram of the typical PID control system. The equation of the controller in continuous-time domain is:
u PID (t ) = K P e(t ) + K I ∫ e(t )dt + K D
de(t ) dt
(2.1)
where uPID(t) is the control signal, e(t) is the error; KP, KI and KD are the controller gains.
PID controller KP
e(t )
r (t ) +
KI s
-
+ +
u PID (t )
Plant
y (t )
+
K Ds
Figure 2.15 : A typical PID control system The Laplace transform of equation (2.1) yields:
K ⎛ ⎞ U PID ( s ) = ⎜ K P + I + K D s ⎟ E ( s ) s ⎝ ⎠
(2.2)
Thus, the transfer function of PID controller can be written as:
G PID ( s ) =
U PID ( s ) K = KP + I + KDs E (s) s
(2.3)
22 A block diagram representation of equation (2.3) is shown in Figure 2.16.
KP
E (s)
KI s
+ U PID (s ) +
+
K Ds
Figure 2.16 : Continuous-time PID controller By using bilinear transformation method, the transfer function of equation (2.3) is transformed into discrete-time domain:
G PID ( z ) =
K T z K ( z − 1) U PID ( z ) = KP + I s + D E( z) z −1 Ts z
(2.4)
where Ts is the sampling period of the digital controller. Note that there are many algorithms exist for digital realisation of an analogue controller, thus equation (2.4) is not unique for a digital PID controller. However, it is the simplest and exact approximation of its analogue counterpart. In addition, it is the transfer function used for many commercial PID controllers. The block diagram representation of this digital PID controller is shown in Figure 2.17.
KP E (z )
K ITs z z −1
+ +
U PID (z )
+
K D ( z − 1) Ts z
Figure 2.17 : Discrete-time PID controller
23 It is often that not all three terms in equation (2.1) are implemented. The P controller is obtained if only the first term is implemented, by setting KI and KD to zero. Similarly, the PI controller is obtained by setting KD = 0; and the PD controller is obtained by setting KI = 0. The P controller is used in situations in which satisfactory dynamic and steady-state responses can be obtained by simply setting a pure gain in the system. The PI controller is used to improve the system steady-state response, whereas the PD controller is used to improve the system dynamic response. However, PD controller has an inherent problem of high-frequency noise amplification [43]. Thus, extra care should be given during the design process to limit the high-frequency gain. The multiloop PI controller has been applied to Voltage Source Inverters (VSIs), implemented both in analogue [18], [19] and digital [20]. A method to decouple the output voltage, analogous to the “back-Electromotive Force (EMF)” decoupling in dc motor drive, is also found in [18]. In [18] and [19], the filter capacitor current feedback is used for the inner current loop, thus proper signal filtering is needed. This is due to the fact that tremendous amount of switching noise present in the filter capacitor current. Besides, the system takes about a quarter cycle of the fundamental period to reach steady-state at start-up [19]. The conventional PID controller requires much effort in the tuning of controller gains before a dynamically acceptable response is obtained. Besides, it is usually implemented using operational amplifier circuits, which has the tendency to drift with age and temperature. Therefore, the digital PID controller is adopted. Although the controller gains might still be tuned based on empirical method, the software tuning provides more flexibility in the design process.
24
2.4.2 Hysteresis Control Hysteresis control is a simple PWM control method that determines an inverter output voltage instantaneously. It is essentially an analogue control technique. In a two-loop control system (current loop and voltage loop), the basic idea of hysteresis control is controlling the load current in order to regulate the output voltage. The error between the reference signal and the load current is locked within a fixed hysteresis band. If the error exceeds the upper hysteresis band, the inverter output voltage is switched low; if the error falls below the lower hysteresis band, the inverter output voltage is switched high. This process is illustrated in Figure 2.18.
Upper band
Reference signal
Actual current Lower band vpwm
t
Figure 2.18 : Typical waveforms of hysteresis control The control principle of hysteresis control is simple, and provides fast dynamic response. However, hysteresis control with fixed hysteresis band has several disadvantages, such as variable switching frequency and large current ripple. The varying switching frequency results in an undefined frequency spectrum of the inverter output voltage. This poses difficulty in designing the low-pass filter and causes excessive stress on the power switches. In order to maintain a constant switching frequency, Kawamura and Hoft [21] proposed an adaptive hysteresis control technique, where the hysteresis band is changed as a function of the reference signal. However, this technique is complex and requires extensive knowledge of the system parameters. Sinusoidal-band
25 hysteresis control technique has been proposed to reduce harmonic content whilst keeping the simplicity of controller implementation [22]. In this method, the hysteresis band varies sinusoidally over a fundamental period, rather than being fixed in the conventional hysteresis control. Figure 2.19 shows the band shapes of the fixed-band and the sinusoidal-band hysteresis control. Sinusoidal-band hysteresis control results in a reduced ripple thus lower harmonic content as compared to fixedband hysteresis control. However, the switching frequency is higher, especially near the zero crossing of the reference signal. To limit the maximum switching frequency, lockout circuit is usually incorporated [22].
i
Upper band Reference signal Lower band t
(a) i
Upper band Reference signal Lower band
t
(b)
Figure 2.19 : Band shapes of hysteresis controllers (a) fixed-band hysteresis control (b) sinusoidal-band hysteresis control With the availability of high-speed digital processors, hysteresis controller has been implemented in digital [23]. However, implementation of digital-based hysteresis control is complex with reduced accuracy. Therefore, a hybrid system is used for highly demanding applications – the calculation of the hysteresis band is implemented in digital; while the comparison of the error with hysteresis band, which is the essence of hysteresis control, is remained in analogue to ensure accuracy and response speed [24].
26
2.4.3 Sliding Mode Control Sliding Mode Control (SMC) is basically a Variable Structure Control (VSC) [50]. Essentially, the SMC utilises a high speed switching control law to drive the state trajectory of the plant onto a specified surface in the state space (called sliding or switching surface), and to keep the state trajectory on this surface for all subsequent time. When sliding on the sliding surface, the structure of the system is changed discontinuously according to the instantaneous values of the system states evaluated along the trajectory. Due to the discontinuous change of the system structure, the SMC system is insensitive to parameter variations of the plant and external disturbances [26]. The trajectory of SMC consists of two parts, representing two modes of the system, i.e. the reaching mode and the sliding mode. Figure 2.20 shows a twodimensional (2-D) phase plane of these modes, with the sliding surface viewed as a straight line, written as:
δ = e& + λe
(2.5)
where e = x − x d ; x is the state variable and xd is the desired state; λ is a constant.
e&
Sliding mode
Reaching mode e Reaching mode
δ Figure 2.20 : A 2-D phase plane of typical SMC
27 Owing to the inherent robustness and switching characteristics of SMC, it is suitable for closed-loop regulation of power converters. Jezernik and Zadravec [25] have applied the SMC to UPS inverter by analogue realisation. To achieve maximum flexibility and simplify the controller implementation, digital-based software realisation is preferred. However, the analogue SMC cannot be directly extended to discrete-time. The sampling action in digital-based controller may induce chattering phenomenon or instability to the analogously designed digital-based SMC. In the inverter applications, chattering will cause serious voltage harmonics, which is undesirable. Therefore, a pure Discrete-time Sliding Mode Control (DSMC) algorithm is used for digital implementation. Jung and Tzou [26] have applied the DSMC to PWM inverter with DSP implementation, but the steady-state response is rather poor. This can be attributed to the large step size used to discretise the reference sinusoidal signal. Tai and Chen [27] further applied the DSMC with certain alleviation on the chattering phenomenon. SMC has been used in closed-loop regulation of PWM inverters. It has the advantage of robustness towards parameter variations and load disturbances. However, the drawbacks include the difficulties in locating a suitable sliding surface, and the chattering phenomenon. In practice, the chattering phenomenon may be caused by the parasitic dynamics of sensors or other feedback components, which are often neglected in control design; and the time delays in code execution of softwarebased SMC. These problems are unavoidable, but to compensate for the time delays, pure discrete-time control design approach is used rather than the analogously derived digital-based SMC. In addition, observer or predictor can be used to estimate the desired states. For instance, the inductor current predictor is used in [27].
28
2.4.4 Repetitive Control Repetitive control theory originates from the Internal Model Principle [51]. This principle states that the controlled output tracks a set of reference inputs without steady-state error if the model that generates these references is included in the stable closed-loop system. For example, if a closed-loop control system is required to have a zero steady-state error to a sinusoidal input, then the model of the sinusoidal function, i.e.
ωo , where ω o is the oscillating frequency, should be included in s 2 + ωo 2
its stable closed-loop transfer function. In practice, periodic input or disturbance consist of many high-order harmonics, thus complete elimination of these periodic errors is impossible. This constraint becomes a significant consideration factor in designing the Repetitive controller to minimise low-order harmonic distortion. In a Repetitive control system, the Repetitive controller is inserted in the control loop in addition to the tracking controller. There are various configurations for the Repetitive control systems. Figure 2.21 shows two basic structures of the Repetitive control system [29], where a cascaded type Repetitive controller is shown in Figure 2.21(a) and a feedforward type Repetitive controller is shown in Figure 2.21(b). With these configurations, the system dynamic response is improved by the tracking controller, while the steady-state response is improved by the Repetitive controller. Haneyoshi et al. [28] have applied the Repetitive control for closed-loop regulation of a PWM inverter. To compensate for model uncertainties, adaptive Repetitive control [29] has been applied, where the parameters are tuned by an adaptive parameter tuner that recursively online identify the plant dynamics. While Repetitive control provides an approach to minimise periodic errors and improve the steady-state response of the system, it is very difficult to obtain fast dynamic response. This is due to the compromise that has to be made between the relative stability and the convergence rate of the periodic errors elimination [29]. In addition, Repetitive controller usually requires additional compensation network to assure stability of the system.
29
R +
Repetitive controller
Tracking controller
C2
C1
+
-
Plant
Y
-
(a) Repetitive controller C2
R
+ +
+
Tracking controller C1
Plant
Y
-
(b)
Figure 2.21 : Basic configurations of Repetitive control system (a) cascaded type (b) feedforward type To implement a Repetitive controller, a periodic actuating signal to minimise the periodic errors caused by periodic input or disturbance must be generated. The signal can be generated either by analogue or digital techniques. However, storing an arbitrary waveform in analogue form is very difficult. In contrast, this can be achieved more easily by software-based digital control technique. Moreover, online parameter tuning can be achieved by adaptive Repetitive control technique. Therefore, the Repetitive controllers for closed-loop regulation of PWM inverters have been implemented digitally using microprocessor [28] and DSP [29].
30
2.4.5 Fuzzy Logic and Neural Network Control Fuzzy logic and neural network are known as intelligent control techniques [52]. These control techniques have grown rapidly in recent years. Extensive research has been carried out for various applications, including control of power converters [30]-[32]. Fuzzy logic and neural network are nonlinear and adaptive in nature, with robust performance under parameter variations and load disturbances. These features made fuzzy logic and neural network suitable for closed-loop control of PWM inverter, where a desirable nonlinear model can be derived. Fuzzy logic control is very much closer to human thinking and natural language [31]. It provides a method of converting linguistic rules based on expert knowledge and experience into automatic control strategy. Figure 2.22 shows a basic configuration of fuzzy logic controller.
Knowledge base R +
Fuzzification -
Rule-based controller
Defuzzification
Plant
Y
Figure 2.22 : Basic configuration of fuzzy logic controller After the selection of fuzzy variables, the design of fuzzy controller can be summarized into three steps: i.
Fuzzification Since the feedback signals are nonfuzzy measurements, they have to be fuzzified. This process depends on a number of membership functions. These membership functions form the boundaries of overlapping fuzzy sets, which are defined by linguistic variables. For instance, a five-term fuzzy set can be defined as “Negative Big (NB)”, “Negative Small (NS)”, “Zero (Z)”,
31 “Positive Small (PS)”, and “Positive Big (PB)”. Figure 2.23 shows a typical triangular shape fuzzy membership functions.
NB
NS
Z
PS
PB
Figure 2.23 : Triangular shape fuzzy membership functions It should be noted that the number of fuzzy sets and the shape of membership functions depend primarily on the designer’s experience and preference. ii.
Fuzzy inference As the fuzzy sets overlap each other along the universe of discourse (horizontal axis of membership functions), the fuzzy control rules are used to infer the change in control signal, ∆U from the specific fuzzy variables. Assume that error, e and change of error, ∆e are used as the fuzzy variables, a typical fuzzy control rule can be written as:
IF e is NB AND ∆e is NB THEN ∆U is NB As such, the developed fuzzy control rules can be summarised in the Fuzzy Rule Table, as shown in Table 2.1. iii.
Defuzzification Since the power converter cannot respond directly to fuzzy sets, the fuzzy sets have to be defuzzified. The control signal can then be derived after defuzzification. There is no single optimal procedure for selecting the defuzzification strategy. The two commonly used methods are Mean of Maximum (MOM) method and Centre of Area (COA) method [52].
32
Table 2.1 : Fuzzy Rule Table e
∆U
∆e
NB
NS
Z
PS
PB
NB
NB
NB
NB
NS
Z
NS
NB
NS
NS
Z
PS
Z
NB
NS
Z
PS
PB
PS
NS
Z
PS
PS
PB
PB
Z
PS
PB
PB
PB
As the detailed dynamics of the plant is not needed in the design process, fuzzy logic control possesses inherent robust property. However, it is lack of a systematic procedure for designing the fuzzy control rules and choosing the membership functions. It depends entirely on practical experiences of the designer. Artificial neural networks are interconnections of neurons that tend to emulate the human brain. The architectures are generally distributed and constructed from many nonlinear computational nodes operating in parallel. There are weighting elements between the nodes that define the strength of connection between nodes, which are adapted during learning by some optimisation procedure to yield the appropriate input-output map. Figure 2.24 illustrates the structure of an artificial neuron.
W1j
x2
W2j
x3
W3j
xn
Wnj
. . .
x1
∑
Rj
fnet
θj
Figure 2.24 : Structure of an artificial neuron
Oj
33 In Figure 2.24, the inputs x1, x2, x3 … xn are multiplied by the weighting elements,
W1j, W2j, W3j … Wnj and the weighted values are fed to the summing node. The bias,
θj is summed with the weighted inputs to form the net input, Rj, which is then used as the argument of the transfer function, fnet. Therefore, the output of the neuron can be written as:
⎞ ⎛ n O j = f net ⎜⎜ ∑ Wij xi + θ j ⎟⎟ ⎠ ⎝ i
(2.6)
There are many neural network architectures that have been proposed. The feedforward neural network is the most commonly used architecture. Figure 2.25 shows a feedforward multilayer neural network that has one hidden layer. The training of neural network usually requires iterative techniques. The backpropagation algorithm is normally used for the training of feedforward neural networks [32].
Input
Hidden layer
Output layer
x1 x2
. . .
. . .
. . . xn
Figure 2.25 : Feedforward multilayer neural network architecture The performance of neural network nonlinearity depends on the total allowed errors. A smaller total allowed error results in better performance. Since neural network has fault tolerance, it provides a robust performance for the system [30]. The disadvantages of neural network control are many training examples have to be obtained, and the training process is usually time-consuming.
34
2.4.6 Deadbeat Control Deadbeat control is one of the most attractive control techniques as it exhibits very fast dynamic response for discrete-time control. In Deadbeat control, any nonzero error vector will be driven to zero in at most n sampling periods if the magnitude of the scalar control u(k) is unbounded [45], where n is the order of the closed-loop system. Deadbeat response is unique to discrete-time control systems. There is no such thing as Deadbeat response in continuous-time control systems. In analogue control system, if the closed-loop poles of the system can be moved further towards the left half of the s-plane, it can achieve faster dynamic response. Ideally, the poles are to be placed at minus infinity ( − ∞ ) [53]. This is not realisable as it is impossible to place all the poles at s = −∞ . However, this can be realised in digital control system. Through the mapping between s-plane and z-plane, as shown in Figure 2.26, the pole at s = −∞ in the s-plane is mapped to z = 0 in the
z-plane. The complex variables s and z are related by:
z = e sT
(2.7)
where T is the sampling period.
Im
Im s-plane
0
Re
-1
j
z-plane
0
1
-j Left half plane
Unit circle
Figure 2.26 : The mapping of s-plane and z-plane
Re
35 Therefore, if all the closed-loop poles of the digital control system can be located at the origin of the z-plane, the fastest dynamic response can be achieved. As such, the discrete-time characteristic equation can be expressed as: zn = 0
(2.8)
where n is the order of the closed-loop system. This is the so-called Deadbeat control, where the state variables of the system can follow the reference variables without error after the intervals of n sampling periods. Consider a discrete-time control system in Figure 2.27, where D(z) is the Deadbeat controller, and G(z) is the transfer function of the plant, which could include a zero-order hold. The closed-loop transfer function is written as: Y ( z) D ( z )G ( z ) = M ( z) = R( z ) 1 + D ( z )G ( z )
(2.9)
Solving for D(z) from equation (2.9) yields:
D( z ) =
1 ⎡ M ( z) ⎤ G ( z ) ⎢⎣1 − M ( z ) ⎥⎦
Deadbeat controller R(z ) +
E (z )
D (z )
(2.10)
Plant U (z )
G (z )
Y (z )
-
Figure 2.27 : A typical Deadbeat control system Note that the transfer function of the controller contains the inverse of the uncompensated system’s open-loop transfer function, G(z). Hence, the design of Deadbeat controller is to cancel out the poles and zeros of the uncompensated system,
36 replacing it with a polynomial based on M(z) so that the desired closed-loop response can be achieved. The general equation of M(z) is given as [44]:
M ( z ) = 1 − (1 − z −1 ) n F ( z )
(2.11)
where F(z) is a polynomial of z −1 . In practice, the ideal Deadbeat response is hard to be realised, as there might be some uncertainties in the system model. Therefore, the interest is to implement the controller as close to Deadbeat response as possible. Deadbeat control has been used in various applications, such as robotics [54], head positioning system in hard disk drive [55], and water level control in hydroelectric power plant [56]. In power electronics applications, Deadbeat control has been widely applied since it was proposed by Gokhale et al. [33] for closed-loop regulation of PWM inverter. Numerous works have been published, including applications in dc-dc converters [57], single-phase and three-phase PWM inverters [33]-[40], motor drives [58] and active filters [59]. In PWM inverter applications, the Deadbeat control algorithm is derived based on the state-space model [47] of the system. Early works [33]-[35] have derived the Deadbeat solutions based on linear load assumption, thus the system performance deteriorates if a nonlinear load is applied, or the load changes. It is also frequently pointed out that Deadbeat control is sensitive to system parameter variations. To improve the system performance and robustness towards load variations, decoupling networks have been employed [36], [37]. On the other hand, the approaches employing single feedback [33], [34] give rise to a slow and oscillatory response, which deteriorates the system performance. Therefore, multiloop Deadbeat control [36], [37] is used to overcome this limitation. In this research, Deadbeat control is selected for closed-loop regulation of the BHFL inverter. This is due to its fast response and precise reference tracking capability. Furthermore, a low harmonic distortion sinusoidal output voltage under various load conditions can be obtained. Another motivation is that although many high-frequency link inverters have been developed [7], [8], [13], [14], [16], current
37 and voltage control using modern control techniques is very limited for highfrequency link inverters. Hence, this research proposes a Deadbeat controller for the BHFL inverter, showing that Deadbeat control technique is applicable to highfrequency link inverters in general.
2.5
Summary In this chapter, the PV inverter systems have been described. The major types
of PV inverter systems and their configurations are also discussed. The topologies of transformer isolated inverters, and the need for isolation are described. A brief description on the basic operational principle of the inverter topologies has also been given. Closed-loop control, the key element to ensure desired dynamic and steadystate response of the inverter has been discussed. The salient features of digital controllers, which make them more prevalent over their analogue counterpart, have also been highlighted. Various closed-loop control techniques of inverters have been explained. The basic theory, advantages and shortcomings of the respective control techniques are described. Finally, the motivations for selection of Deadbeat control in this research have been outlined.
CHAPTER 3
DEADBEAT CONTROLLER FOR BIDIRECTIONAL HIGH-FREQUENCY LINK (BHFL) INVERTER
3.1
Introduction In many applications, it is desirable that the inverter is compact and light
weight. This has made the high-frequency link inverter with active rectifier output stage gaining much interest. The merits of this topology have been described in Chapter 2. In this research, an alternative topology – Bidirectional High-Frequency Link (BHFL) inverter is utilised. It has reduced power switch counts and increased efficiency. A Deadbeat controller is proposed for closed-loop regulation of the BHFL inverter. The controller consists of current and voltage loop controllers with decoupling networks, and a feedforward controller. This chapter describes the BHFL inverter and its operating principle. The plant modelling of the BHFL inverter is presented. This takes into account the discretisation effect on the dynamic model of BHFL inverter. Next, the analysis and design of the Deadbeat controller is explained in considerable detail. The range of current and voltage loop controller gains to ensure system stability are derived. The controller gains to achieve Deadbeat response are subsequently selected. The robustness of the designed controller is investigated, considering the parameter variations of the system in practical situations.
39 3.2
Description of BHFL Inverter and System Operating Principle The BHFL inverter [17], which is the plant to be controlled, is shown in
Figure 3.1. The main conversion circuits are: high-frequency PWM bridge, active rectifier and polarity-reversing bridge. On the transformer primary side, the dc source voltage, Vdc is converted into a high-frequency PWM voltage, vHF by the high-frequency PWM bridge. Then, this voltage is isolated and stepped-up using the centre-tapped high-frequency transformer. Next, the high-frequency PWM voltage is rectified using the active rectifier. The active rectifier, which consists of power switches and anti-parallel diodes, enables bidirectional power flow. For transfer of power from the source to load, the diodes are utilised; for reverse power flow, the power switches S3 and S3 are turned on. A regenerative snubber circuit is used to suppress any voltage spikes at the transformer secondary caused by the leakage inductance of the transformer. The snubber circuit is not shown in the figure to simplify the diagram. The rectified PWM voltage, vpwm_rect is then low-pass filtered to obtain the rectified fundamental component, vrect. Finally, using the polarity-reversing bridge, the second half of the rectified sinusoidal voltage is unfolded at zero-crossing, and the sinusoidal output voltage, vo is obtained. The timing diagram for the key waveforms of the power stage is shown in Figure 3.2.
Bidirectional power flow High-frequency ac Rectified ac
dc
idc
High-frequency PWM bridge S1
Centre-tapped high-frequency transformer Active rectifier N1:N2
S2
S3
+ vHF
Vdc
S2
+
L
Polarity-reversing bridge + S4
vpwm_rect -
S1
Low-pass filter
Line-frequency ac
C
S5
+ vo -
vrect
S3
-
S4
io
Load
S5
Figure 3.1 : Circuit configuration of the Bidirectional High-Frequency Link inverter
40 vHF Vdc
t
vpwm_rect ⎛ N2⎞ Vdc ⎜ ⎟ ⎝ N1 ⎠
t vrect
vo
t
t
Figure 3.2 : Key waveforms at the principal conversion stages of BHFL inverter
3.3
Modelling of BHFL Inverter To design a closed-loop controller for the BHFL inverter, a dynamic model of
the BHFL inverter is first derived. State-space technique [47] is used to model the inverter. Referring to Figure 3.1, it is assumed that the dc source voltage, Vdc is constant. The inverter switching frequency is considered to be much higher than the 50Hz sinusoidal modulating frequency. The high-frequency transformer is assumed to be operating in the linear area. As such, the high-frequency PWM bridge and the transformer can be modelled as constant gains. The polarity-reversing bridge is only operated at line-frequency (50Hz), thus its dynamics can be ignored. With these assumptions, the dynamics of the system can be simplified to a LC low-pass filter connected to the load. Figure 3.3 depicts the equivalent circuit of the BHFL inverter, where u is the system input (control variable), and Z denotes the output impedance of an unknown load. The Equivalent Series Resistance (ESR) of the filter inductor is denoted as rL, and the ESR of the filter capacitor is denoted as rc.
41 + vL L
iL rL
ior ic
rc u C
+ vrect -
Z
+ Unknown vor load -
Figure 3.3 : Equivalent circuit of the BHFL inverter By ignoring the polarity-reversing bridge, the rectified sinusoidal output voltage, vor is obtained. Choosing the filter inductor current iL and filter capacitor voltage vrect as the state variables, the state-space representation and output equation of the system are derived:
1⎤ ⎡ di L ⎤ ⎡ 1 ⎡ rc ⎤ ⎢ dt ⎥ ⎢− L (rL + rc ) − L ⎥ ⎡ i L ⎤ ⎡ 1 ⎤ ⎢ ⎥ + ⎢ L ⎥ u + ⎢ L ⎥ ior ⎢ dv ⎥ = ⎢ ⎥ ⎢ ⎥ 1 1 ⎢ rect ⎥ ⎢ ⎢− ⎥ 0 ⎥ ⎣v rect ⎦ ⎢⎣ 0 ⎥⎦ C ⎦ ⎣ C⎦ ⎣ dt ⎦ ⎣
(3.1)
⎡ iL ⎤ vor = [rc 1] ⎢ ⎥ + [− rc ] ior ⎣v rect ⎦
(3.2)
In practice, the values of rL and rc are very small and can be neglected. If the ESRs are neglected, equation (3.1) and (3.2) can be simplified as: ⎡ di L ⎤ ⎡ ⎢ dt ⎥ ⎢ 0 ⎢ dv ⎥ = ⎢ 1 ⎢ rect ⎥ ⎢ ⎣ dt ⎦ ⎣ C
1⎤ − ⎥⎡ i ⎤ ⎡ 1 ⎤ ⎡ 0 ⎤ L L ⎢ ⎥ ⎢ 1 ⎥ ior + + u ⎥⎢ L ⎥ v ⎢ ⎥ ⎢⎣− C ⎥⎦ rect ⎦ ⎣ 0 ⎥ ⎣0⎦ ⎦
⎡ iL ⎤ vor = [0 1] ⎢ ⎥ ⎣v rect ⎦
(3.3)
(3.4)
42 Based on equation (3.3) and (3.4), the dynamic model of the system is represented by the block diagram in Figure 3.4. It can be seen that the load current acts as a disturbance on the output voltage, while the output voltage acts as a disturbance on the inductor current.
ior
u +
1 sL
-
iL +
-
Unknown load 1 Z (s) ic
1 sC
vor
Figure 3.4 : Continuous-time model of the BHFL inverter Since the controller is to be implemented using a digital processor, the continuous-time state-space equations (3.3) and (3.4) are discretised. The derivation of the discrete-time state-space equations is shown in Appendix A. With a sampling period of Ts, the discrete-time state-space equations can be written as: x(k + 1) = Ax(k ) + Bu (k ) + Bd ior (k )
(3.5)
vor (k ) = Cx (k )
(3.6)
where
⎡A A = ⎢ 11 ⎣ A21
1 ⎡ ⎤ − sin(ωTs )⎥ A12 ⎤ ⎢ cos(ωTs ) ωL =⎢ ⎥ ⎥ 1 A22 ⎦ ⎢ sin(ωTs ) cos(ωTs ) ⎥ ⎣ ωC ⎦
⎡ B1 ⎤ ⎡ 1 sin(ωTs )⎤ ⎥ B = ⎢ ⎥ = ⎢ ωL B ⎢ ⎣ 2 ⎦ ⎣1 − cos(ωTs ) ⎥⎦ ⎡ Bd 1 ⎤ ⎡ 1 − cos(ωTs ) ⎤ Bd = ⎢ ⎥ = ⎢− 1 sin(ωT )⎥ B s ⎥ ⎣ d 2 ⎦ ⎢⎣ ωC ⎦ C = [0 1]
⎡ i L (k ) ⎤ x(k ) = ⎢ ⎥ is the state vector, and ω = ⎣v rect (k )⎦ low-pass filter in radian per second.
1 LC
is the cut-off frequency of the
43 From equation (3.5) and (3.6), the discrete-time equations can be rewritten as:
B A A 1 i L (k + 1) − 11 i L (k ) − 12 vor (k ) − d 1 ior (k ) B1 B1 B1 B1
(3.7)
B B A 1 vor (k + 1) − 22 vor (k ) − 2 u (k ) − d 2 ior (k ) A21 A21 A21 A21
(3.8)
u (k ) =
i L (k ) =
From equation (3.7) and (3.8), it can be seen that additional disturbance terms appear because of model discretisation. As compared to the continuous-time model in Figure 3.4, there exist two disturbances instead of one, acting on the inductor current and output voltage. The current and voltage disturbance terms can be written as:
id (k ) = −
B A12 vor (k ) − d 1 ior (k ) B1 B1
(3.9)
B B2 u (k ) − d 2 ior (k ) A21 A21
(3.10)
v d (k ) = −
Based on the discrete-time equations, the digital model of the system can be represented by the block diagram in Figure 3.5, where z −1 denotes a unit delay.
A12 +
u (k )
B1
+ +
+
i L (k + 1)
vor (k ) +
Bd1
z
−1
+ A11
ior (k ) i L (k )
A21
+ +
+
vor ( k + 1)
B2
u (k )
Bd2
ior (k )
z −1
+ A22
Figure 3.5 : Discrete-time model of the BHFL inverter
vor (k )
44
3.4
Design of the Proposed Deadbeat Controller In order to achieve fast dynamic response, Deadbeat control technique is
applied for closed-loop regulation of the BHFL inverter. The Deadbeat controller is designed based on the discrete-time state-space model of the inverter system. This takes into account the effect of model discretisation. Figure 3.6 shows the structure of the proposed controller for BHFL inverter. It consists of inner current loop controller, outer voltage loop controller and feedforward controller. The feedforward controller, which imposes a gain scheduling effect according to the reference signal, is used to compensate steady-state error of the system. From the discrete-time model of the plant in Figure 3.5, it is known that there are disturbance terms acting on the inductor current and output voltage. These disturbances are compensated using additional decoupling networks in equation (3.9) and (3.10). The voltage disturbance decoupling network is added to the voltage loop controller, while the current disturbance decoupling network is added to the current loop controller. With that, the Deadbeat controller has good disturbance rejection capability and improved robustness towards load variations. The design procedures of the controller are described in the following subsections.
Proposed controller Feedforward controller
Kf Voltage loop controller
v ref (k )
+
Kv -
+ +
Current loop controller
+
iref (k )
+
+
Ki -
u (k )
+
+
PWM modulator
vpwm
To gate drives of BHFL inverter (High-frequency PWM bridge)
Current disturbance decoupling network
Voltage disturbance decoupling network v d (k )
id (k )
vor (k )
i L (k ) i L (k )
v or (k )
ior (k )
Figure 3.6 : Proposed Deadbeat controller for the BHFL inverter
45
3.4.1 Current Loop Controller Figure 3.7(a) shows the inner current loop controller. The current disturbance decoupling network is added to compensate the disturbances acting on the inductor current. Cancelling the current disturbance coupling allows a simple gain, Ki to be applied in forming the inner current loop. From Figure 3.7(a), the current loop control law can be derived:
[
]
u (k ) = K i i ref (k ) − i L (k ) + i d (k )
(3.11)
where u (k ) is the control signal applied to the PWM modulator, iref (k ) is the inductor current reference generated by the outer voltage loop, and id (k ) is the current disturbance decoupling network from equation (3.9). Figure 3.7(b) shows the simplified current loop, where the disturbance terms are cancelled. The discrete-time open-loop transfer function can be written as:
Gi ( z ) =
=
B1 z −1 1 − A11 z −1
[
sin(ωTs ) z −1
ωL 1 − cos(ωTs ) z −1
]
(3.12)
The corresponding discrete-time closed-loop transfer function of the current loop is:
Ci ( z ) =
i L (k ) K i Gi ( z ) = iref (k ) 1 + K i Gi ( z ) =
=
K i B1 z −1
[K i B1 − A11 ]z −1 + 1 K i sin(ωTs ) z −1
[K i sin(ωTs ) − ωL cos(ωTs )] z −1 + ωL
(3.13)
46
Current disturbance decoupling network
+
+
−
A12 B1
vor (k )
−
Bd 1 B1
ior (k )
+
+
id (k ) iref (k ) +
+
Ki
+
u (k )
B1
-
+ +
i L (k + 1)
A12
vor (k )
Bd1
ior (k )
z −1
i L (k )
+ A11
Current loop controller
Plant
(a) Gi (z ) iref (k ) +
B1 z −1 1 − A11 z −1
Ki -
iL (k )
(b)
Figure 3.7 : Current controller (a) current loop (b) simplified current loop
From equation (3.13), the characteristic equation of the closed-loop current controller can be written as: z − [ A11 − K i B1 ] = 0
1 ⎡ ⎤ z − ⎢cos(ωTs ) − K i sin(ωTs )⎥ = 0 ωL ⎣ ⎦
(3.14)
47 In discrete-time control systems, the closed-loop poles or the roots of the characteristic equation must lie within the unit circle in z-plane for the system to be stable [45]. Therefore, the range of Ki for the system to be stable is: − 1 < [ A11 − K i B1 ] < 1 A11 − 1 A +1 < K i < 11 B1 B1
ωL[cos(ωTs ) − 1] ωL[cos(ωTs ) + 1] < Ki < sin(ωTs ) sin(ωTs )
(3.15)
To achieve Deadbeat response, the root is to be placed at the origin of the z-plane ( z = 0 ) [53]. Hence, the current loop gain, Ki is designed as:
Ki = =
A11 B1
ωL cos(ωTs ) sin(ωTs )
(3.16)
Substituting equation (3.16) into equation (3.13) yields:
i L (k ) = A11 z −1iref (k ) = cos(ωTs ) z −1iref (k )
(3.17)
When the value of ωTs is sufficiently small, sin(ωTs ) ≈ ωTs and cos(ωTs ) ≈ 1 . Therefore, equation (3.17) can be written as i L (k ) = z −1iref (k ) , which is the Deadbeat response.
48
3.4.2 Voltage Loop Controller Figure 3.8(a) shows the outer voltage loop controller. The voltage disturbance decoupling network is added to compensate the disturbances acting on the output voltage. This will improve the robustness of the system towards load variations, enabling various types of loads to be connected. Besides, it also acts as an additional current loop command to produce the needed load current without waiting for errors in voltage to occur. The design procedure of the voltage loop controller is similar to the current loop controller. The voltage loop gain, Kv is applied to achieve Deadbeat response. Referring to Figure 3.8(a), the voltage loop control law is derived:
[
]
iref (k ) = K v v ref (k ) − vor (k ) + v d (k )
(3.18)
where iref (k ) is the generated current loop command for the inner current loop,
v ref (k ) is the rectified sinusoidal voltage reference, and v d (k ) is the voltage disturbance decoupling network from equation (3.10). Figure 3.8(b) shows the simplified voltage loop, where the disturbance terms are cancelled. It can be noted that the inner current loop is viewed as a constant gain, with the condition of current loop is well designed. The corresponding discrete-time open-loop transfer function is:
Gv ( z ) = =
A21 z −1 1 − A22 z −1
[
sin(ωTs ) z −1
ωC 1 − cos(ωTs ) z −1
]
(3.19)
49 u (k ) −
B2 A21 +
Voltage disturbance decoupling network
+
−
Bd 2 A21
v d (k ) v ref (k ) +
+
Kv
+
ior (k ) +
Inner current loop iref (k )
1
A21
-
+ +
+
vor (k + 1)
B2
u (k )
Bd2
ior (k )
z −1
vor (k )
+ A22
Voltage loop controller
Plant
(a)
Gv (z ) v ref (k ) +
A21 z −1
Kv
v or (k )
1 − A22 z −1
-
(b)
Figure 3.8 : Voltage controller (a) voltage loop (b) simplified voltage loop
The discrete-time closed-loop transfer function of the voltage loop is:
Cv ( z) =
vor (k ) K v Gv ( z ) = v ref (k ) 1 + K v Gv ( z ) =
=
K v A21 z −1
[K v A21 − A22 ]z −1 + 1 K v sin(ωTs ) z −1
[K v sin(ωTs ) − ωC cos(ωTs )] z −1 + ωC
(3.20)
50 From equation (3.20), the characteristic equation of the closed-loop voltage controller can be written as: z − [ A22 − K v A21 ] = 0
1 ⎡ ⎤ z − ⎢cos(ωTs ) − K v sin(ωTs )⎥ = 0 ωC ⎣ ⎦
(3.21)
For the system to be stable, the range of Kv is: − 1 < [A22 − K v A21 ] < 1 A22 − 1 A +1 < K v < 22 A21 A21
ωC [cos(ωTs ) − 1] ωC [cos(ωTs ) + 1] < Kv < sin(ωTs ) sin(ωTs )
(3.22)
Similar to the current loop gain, the voltage loop gain, Kv is designed such that the root of the system can be placed at the origin of z-plane:
Kv = =
A22 A21
ωC cos(ωTs ) sin(ωTs )
(3.23)
Substituting equation (3.23) into equation (3.20) yields: vor (k ) = A22 z −1v ref (k ) = cos(ωTs ) z −1v ref (k )
(3.24)
When the value of ωTs is sufficiently small, sin(ωTs ) ≈ ωTs and cos(ωTs ) ≈ 1 . Therefore, equation (3.24) can be written as vor (k ) = z −1v ref (k ) , which is the Deadbeat response.
51
3.4.3 Feedforward Controller From equation (3.24), it can be seen that there is a steady-state error in the output voltage if ωTs is not sufficiently small. To compensate the steady-state error, a feedforward controller is added to the output of the voltage loop controller. The feedforward controller imposes a gain scheduling effect on the voltage loop controller according to the reference signal. Figure 3.9 shows the voltage loop with inclusion of feedforward controller.
Kf
v ref (k ) +
+
Kv
Gv (z )
+
A21 z −1
vor (k )
1 − A22 z −1
-
Figure 3.9 : Voltage loop with feedforward controller Referring to Figure 3.9, the discrete-time closed-loop transfer function is derived:
[
]
K v + K f A21 z −1 vor (k ) = v ref (k ) [K v A21 − A22 ]z −1 + 1
=
[K
v
]
+ K f sin(ωTs ) z −1
[K v sin(ωTs ) − ωC cos(ωTs )] z −1 + ωC
(3.25)
To ensure Deadbeat response, the feedforward gain, Kf is chosen as:
Kf = =
1 − A22 A21
ωC [1 − cos(ωTs )] sin(ωTs )
(3.26)
Substituting equation (3.23) and (3.26) into equation (3.25), vor (k ) = z −1v ref (k ) is obtained, which ensures the Deadbeat response.
52
3.5
Robustness of the Designed Controller A stability analysis is performed to investigate the robustness of the designed
controller against parameter mismatches. As the controller gains are determined based on the cut-off frequency of the low-pass filter, ω =
1 LC
, parameter
variations of filter inductor and capacitor will degrade the performance of the designed controller. This is due to the shifting of closed-loop poles from the desired value (origin of z-plane), thus Deadbeat response is no longer obtained. Figure 3.10 depicts the trajectories of the closed-loop pole if the inductor value is increased from 0% to 90%, and decreased from 0% to -50%. As the structure of the outer voltage loop is same as the inner current loop, the trajectories with change of capacitor value are quite similar to that with change of inductor value. Referring to Figure 3.10, when the value of L is changed (maintaining the value of C), the pole cancellation is not achieved, thus Deadbeat response is not attained. However, the poles are within the unit circle, so the system is still stable. From Figure 3.10, it is noted that the system is more stable to positive variations, with a reasonably small shifting of pole from the origin of z-plane.
-50%
-40%
-30%
-10%
-20%
10%
90%
0%
Figure 3.10 : Trajectories of the closed-loop pole with L change
53 In general, it is pointed out that Deadbeat controller is sensitive to parameter variations [26], [37]. This is because earlier works derived the Deadbeat solutions based on linear models of the load (nominal resistive load). However, the designed controller with inclusion of decoupling networks improves the robustness of the system. Although the dynamic response of the inverter will be degraded due to large parameter mismatches, the system is still stable within acceptable range.
3.6
Summary In this chapter, the BHFL inverter and its operating principle has been
described. The modelling of BHFL inverter using the state-space averaging technique has been presented. A Deadbeat controller has been proposed for closedloop regulation of the BHFL inverter. Finally, the robustness of the proposed controller is investigated. It is shown that the system is robust towards parameter variations in practical situations.
CHAPTER 4
SYSTEM MODELLING AND SIMULATION
4.1
Introduction In power electronics, computer simulation serves as a tool in gaining insights
on operating principles, dynamic and steady-state behaviour, as well as control performance of an actual system. It is useful in verifying the conceptual designs and streamlining the system implementation process. In this research, the computer simulation package employed is MATLAB/Simulink. It provides a Graphical User Interface (GUI) for constructing block diagram models via drag and drop operations. The extensive block libraries including power electronics components make it ideally suitable for power circuit simulation and controller design tasks. This chapter presents the system modelling of the closed-loop BHFL inverter in MATLAB/Simulink platform. To investigate the performance of the proposed controller, three sets of controllers are constructed and simulated. The controllers evaluated are: the conventional Proportional-Integral (PI) controller, the multirate digital controller, and the proposed Deadbeat controller. Modelling procedures for each component, namely the gate drives, BHFL inverter, signal conditioning, multiloop controllers and test loads, are explained. The simulation settings and practical considerations in system modelling are also discussed. The simulation results will be presented in Chapter 6 for comparison with the experiment results.
55 4.2
System Modelling via MATLAB/Simulink The complete simulation model constructed under MATLAB/Simulink
environment is depicted in Figure 4.1. It consists of gate drives, BHFL inverter, test loads, signal conditioning, and digital controller. Three sets of digital controllers – the conventional PI controller, the multirate digital controller, and the proposed Deadbeat controller have been constructed for comparison. The following subsections provide more descriptions on each of the components.
Figure 4.1 : Complete simulation model of closed-loop BHFL inverter
4.2.1 Gate Drives Gate drive is the gating circuit to switch on/off the power switches, depending on the gate control signals. The power switches of the BHFL inverter are driven by three gate control signals, namely vpwm, vs and vu. These control signals are shown in Figure 4.2. The control signals will then go through a series of logic gates and become the gating signal for each power switch.
56 Modulating signal
Carrier signal
t
vpwm
t
vs
t
vu
t
Figure 4.2 : Gate control signals for the BHFL inverter Figure 4.3 shows the detail of the “Gate drives” block. The control signals are generated by the digital controller. The logic gates are constructed using the Logical Operator from Simulink/Logic and Bit Operations library. The outputs of the logic gates are used to drive the power switches of BHFL inverter.
Figure 4.3 : Detail of “Gate drives” block
57 4.2.2 BHFL Inverter Figure 4.4 shows the detail of the “BHFL inverter” block. It is constructed using the blocksets from SimPower Systems library. The high-frequency PWM bridge and the polarity-reversing bridge are constructed using the Universal Bridge from SimPower Systems/Power Electronics library. The active rectifier is constructed using Diode and Ideal Switch, as shown in Figure 4.5. The centre-tapped high-frequency transformer is constructed using the Linear Transformer from SimPower/Elements library. The output of BHFL inverter is connected to the test loads through the polarity-reversing bridge.
Figure 4.4 : Detail of “BHFL inverter” block
Figure 4.5 : Detail of “Active rectifier” block
58 4.2.3 Feedback Signal Conditioning The feedback signals are sensed and conditioned before being applied to the digital controller. The values of the current and voltage are sensed using the blocksets from SimPower Systems/Measurements library. The output of these blocks provides a Simulink signal that can be used by other Simulink blocks. Figure 4.6 shows the detail of the “Signal conditioning” block, where the feedback signals are sent through low-pass filters for noise filtering. These low-pass filters are inserted to simulate the actual implementation, where signal filters are necessary for good quality signal processing. The low-pass filters are constructed using the Discrete Filter from Simulink/Discrete library. Each of the filters is expressed by its discrete transfer function. This is performed by specifying the coefficients of the numerator and denominator polynomials for the block. The low-pass filters are first designed in analogue [60], and then transformed into the equivalent digital filter using bilinear transformation method [61]. The design procedures for these signal filters will be outlined in Chapter 5 (Section 5.3.2).
Figure 4.6 : Detail of “Signal conditioning” block
59 4.2.4 Multiloop Controller for BHFL Inverter It is common to find voltage loop controller in closed-loop inverters. However, single feedback control is not good enough for ac regulation because of the undamped second-order nature of the LC filter [18]. To improve the performance of inverters under critical load conditions, multiloop controllers are of preference. In this research, three sets of multiloop controllers have been constructed for comparison. The control performance of the multiloop controllers is evaluated under various load conditions.
4.2.4.1 Conventional PI Controller Figure 4.7 shows the conventional PI controller [20], where P controller is employed in the voltage loop, and PI controller is employed in the current loop. The rectified sinusoidal output voltage, vor and filter inductor current, iL are used as the feedback signals for voltage and current loop respectively. As shown in Figure 4.7, vor is compared with the reference signal, vref. The difference between these two voltages is fed to the P controller. The output of P controller is the reference current command for the inner current loop. The current command is compared with iL, and the error signal is fed to the PI controller. The output of PI controller is the control signal, which is sent to the PWM modulator to generate the PWM gate signals. For this system, the transfer function of the current loop PI controller is:
⎛ K ⎞ K Pi ⎜⎜ s + I ⎟⎟ K Pi ⎠ ⎝ G PI ( s ) = s = K Pi +
where the controller zero, ω z =
KI . K Pi
KI s
(4.1)
60
Figure 4.7 : Conventional PI controller For digital implementation, equation (4.1) is transformed into its equivalent digital form:
G PI ( z ) = K Pi +
K I Ti z z −1
(4.2)
where Ti is the sampling period of the current loop controller. The sampling period of the voltage loop is set to twice the current loop controller. In Figure 4.7, the voltage loop P controller is simply constructed using the Gain block from Simulink/Math Operations library. The current loop PI controller is constructed using the Discrete PI Controller from SimPowerSystems/Extra Library/Discrete Control Blocks library. Figure 4.8 shows the detail of the “PI controller” block.
Figure 4.8 : Detail of “PI controller” block
61
4.2.4.2 Multirate Digital Controller Figure 4.9 shows the multirate digital controller with decoupling networks. The inclusion of decoupling networks to inverter controller is first proposed and implemented in analogue by Ryan and Lorenz [18]. The decoupling scheme is then adopted in multirate digital controller by Jung et al. [36]. Employing decoupling networks is a very direct and effective method for disturbance rejection. It improves the system robustness towards different types of loads. In addition, it avoids the use of high controller gain commonly applied to effectively suppress disturbances. This is favourable as high gain control results in limit cycle ringing problem [21].
Figure 4.9 : Multirate digital controller The current and voltage loop controllers of the multirate digital controller are designed separately to achieve Deadbeat response. The sampling frequency of the voltage loop is set to half of the current loop. Figure 4.10(a) shows the inner current loop controller. The output voltage decoupling network is added to compensate the disturbances caused by the output voltage. Note that the continuous-time model of the plant is used in this controller design. The classical design method is applied, where the loop transfer function is discretised using zero-order hold. Figure 4.10(b) shows the simplified current loop, where ZOH represents the zero-order hold. The discrete-time open-loop transfer function can be written as:
Gi ( z ) = Z [G ZOH ( s )G1 ( s )]
=
Ti z −1 L(1 − z −1 )
(4.3)
62
1 − e −Ts is the transfer function of the zero-order hold [44], and Ti where G ZOH ( s ) = s is the sampling period of the current loop. The corresponding discrete-time closed-loop transfer function of the current loop is:
Ci ( z ) =
iL K i Gi ( z ) = iref 1 + K i Gi ( z ) ⎛T ⎞ K i ⎜ i ⎟ z −1 ⎝L⎠ = ⎡ ⎛ Ti ⎞ ⎤ −1 ⎢ K i ⎜ ⎟ − 1⎥ z + 1 ⎣ ⎝L⎠ ⎦
(4.4)
Output voltage decoupling ADC
Plant
ior
iref +
+ +
Ki
-
Ti
u
1 sL
+
-
iL+
-
Unknown load 1 Z (s) ic
1 sC
vor
ADC
(a) Gi(s) iref +
Ki
Ti
GZOH(s) ZOH
-
G1(s) 1 sL
iL
(b)
Figure 4.10 : Inner loop controller (a) current loop (b) simplified current loop
63 From equation (4.4), the characteristic equation of the closed-loop current controller can be written as:
⎡ ⎛ T ⎞⎤ z − ⎢1 − K i ⎜ i ⎟⎥ = 0 ⎝ L ⎠⎦ ⎣
(4.5)
To achieve Deadbeat response, the current loop gain, Ki is designed as:
Ki =
L Ti
(4.6)
Figure 4.11(a) shows the outer voltage loop controller, where the load current decoupling network is added to compensate the disturbances induced by the load current. Figure 4.11(b) shows the simplified voltage loop, with the discrete-time open-loop transfer function written as: Gv ( z ) = Z [G ZOH ( s )G2 ( s )]
=
Tv z −1 C (1 − z −1 )
(4.7)
where Tv is the sampling period of the voltage loop controller. The corresponding discrete-time closed-loop transfer function of the voltage loop is:
Cv ( z ) =
vor K v Gv ( z ) = v ref 1 + K v Gv ( z ) ⎛T ⎞ K v ⎜ v ⎟ z −1 ⎝C⎠ = ⎡ ⎛ Tv ⎞ ⎤ −1 ⎢ K v ⎜ ⎟ − 1⎥ z + 1 ⎣ ⎝C⎠ ⎦
(4.8)
64 From equation (4.8), the characteristic equation of the closed-loop voltage controller can be written as: ⎡ ⎛T z − ⎢1 − K v ⎜ v ⎝C ⎣
⎞⎤ ⎟⎥ = 0 ⎠⎦
(4.9)
Similar to current loop gain, the voltage loop gain Kv is designed to achieve Deadbeat response, thus chosen as:
Kv =
Load current decoupling
vref
Tv +
Kv
+ +
-
iref
C Tv
(4.10)
Unknown load ior 1 Z (s)
ADC Inner current loop
iL +
-
ic
vor
1 sC
ADC
(a) Gv(s) vref +
Kv
Tv
Current loop GZOH(s) 1
-
ZOH
G2(s) 1 sC
vor
(b)
Figure 4.11 : Outer loop controller (a) voltage loop (b) simplified voltage loop The multirate digital controller in Figure 4.9 can be easily constructed using Simulink blocks. For instance, the Gain block from Simulink/Math Operations library is used to construct the current and voltage loop controller gains.
65
4.2.4.3 Proposed Deadbeat Controller In previous discussion, the advantages of decoupling scheme have been highlighted. The multirate digital controller with decoupling networks has been constructed and simulated. However, it is noted that the design does not take into account the effect of discretisation. As a result, the disturbances in the current and voltage loops cannot be totally eliminated. In this research, the decoupling scheme is applied in the proposed Deadbeat controller for BHFL inverter. As described in Chapter 3, the decoupling networks are added by taking into account the effect of discretisation. Therefore, a better disturbance rejection can be achieved. Figure 4.12 depicts the proposed Deadbeat controller in MATLAB/Simulink platform. The voltage disturbance decoupling network is added to the voltage loop controller to compensate the disturbances acting on output voltage. The current disturbance decoupling network is added to the current loop controller to compensate the disturbances on inductor current. The detail of these decoupling network blocks are shown in Figure 4.13.
Figure 4.12 : Proposed Deadbeat controller
66
(a)
(b)
Figure 4.13 : Detail of (a) “Voltage disturbance decoupling network” block (b) “Current disturbance decoupling network” block The proposed Deadbeat controller is constructed using Simulink blocks. The current loop controller gain Ki, voltage loop controller gain Kv, and feedforward controller gain Kf, are constructed using the Gain block from Simulink/Math Operations library. The coefficients of the decoupling networks are also constructed using the Gain block.
4.2.5 Test Loads To evaluate the performance of the closed-loop BHFL inverter, various types of loads in practical applications are tested on the system. A resistive load is connected to the system as linear load; RL load is used as inductive load to illustrate the bidirectional power flow capability of the BHFL inverter. The system is also tested under worst loading conditions, such as triac load and nonlinear rectifier load. Figure 4.14 shows the model of loads in the “Test loads” block. Referring to Figure 4.14(c), the triac is constructed using the Ideal Switch from SimPower Systems/Power Electronics library. The firing angle of the triac is controlled by a gate signal, constructed using the Pulse Generator from Simulink/Sources library. Thus, a cyclic step load change can be synthesised by setting the parameters of the Pulse Generator. For instance, to generate a load change at firing angle of 90° (over 50Hz operating frequency), the pulse width is set to 50%, and the phase delay is set to 5ms, with the period set to 10ms. Referring to Figure 4.14(d), the full-bridge rectifier load is constructed using the Universal Bridge.
67
(a)
(b)
(c)
(d)
Figure 4.14 : Test loads (a) resistive load (b) inductive load (c) triac load (d) rectifier load
4.3
Summary In this chapter, a complete system of the closed-loop BHFL inverter has been
modelled under MATLAB/Simulink platform. Three sets of multiloop digital controllers have been constructed and simulated. The performances of the controllers are compared to verify the effectiveness of the proposed control technique. The system has been tested under various load conditions, among the critical loads are the triac load and rectifier load. The simulation results will be presented in Chapter 6 for comparison with the experimental results.
CHAPTER 5
HARDWARE IMPLEMENTATION
5.1
Introduction To verify the performance of Deadbeat control technique in closed-loop
regulation of the BHFL inverter, a laboratory prototype has been constructed. It consists of the BHFL inverter (which is the plant to be controlled), feedback circuit, DS1104 Digital Signal Processor (DSP) board and the critical load test-rigs. The DS1104 DSP is used to generate control signals and implement the multiloop controllers for the BHFL inverter. Two sets of controllers have been implemented, namely the multirate digital controller, and the proposed Deadbeat controller. Their performances will be compared and evaluated. The conventional PI controller is not implemented because the simulation results indicate that its performance is relatively poor, especially under critical load conditions. This chapter provides description on hardware implementation, with brief explanation on the power circuit and gate drive circuits. The focus will be on the controller implementation using DS1104 DSP board, emphasising on the proposed Deadbeat controller. The gate control signals generation and signal conditioning for the feedback path, including the implementation of digital filter using DSP are presented. The construction of critical load test rigs – triac load and full-bridge rectifier load is also outlined. The experimental results will be presented in Chapter 6 for comparison with the simulation results.
69 Figure 5.1 shows the photograph of the laboratory experimental set-up. The block diagram of the overall system configuration is illustrated in Figure 5.2. Detail description on each of the hardware components is provided in the following sections.
i. High power dc supply ii. DC supply
vi i
iii. BHFL inverter
ii iii
viii
iv. Sub-D connectors of DS1104 DSP
vii
iv v
ix
v. Interface panel to I/O pins of DS1104 vi. PC where DS1104 is installed (via PCI)
x
vii. Oscilloscope xi
viii. Rectifier (load) ix. Triac (load) x. Resistive load bank xi. Inductive load bank
Figure 5.1 : Photograph of laboratory experimental set-up
Loads Power circuit R load
idc + L S2
S1
S3
+ vHF
Vdc
S4
vpwm_rect -
S1
+
C
io vrect
S3
S2
S5
-
S4
+ vo -
RL load
Triac load
S5
Rectifier load Feedback signals Gate drive circuit
DS1104 DSP
Feedback circuit (Current and voltage sensors)
Gate control signals
PWM modulator
Digital controller
ADCs
PCI bus
Signal conditioning
Figure 5.2 : Block diagram of overall system configuration
PC
70 5.2
BHFL Inverter A 1kVA prototype inverter has been constructed. It comprises the gate drive
module and the power circuit module. The feedback circuit, which consists of Halleffect current and voltage sensors, is also mounted on the power circuit module. Figure 5.3 shows the photograph of the prototype inverter.
i. Power switches and gate drivers
i
ii. Gate drive power supplies
ii iii
iii. Dead-time generators and logic gates
(a)
iv. DC link capacitors
iv
iv
v. High-frequency transformer
vi v
vii
vi. Low-pass filter vii. Feedback circuit
(b) Figure 5.3 : Photograph of BHFL inverter (a) top view – gate drive module (b) bottom view – power circuit module
71 5.2.1 Gate Drive Circuit The gate drive circuit acts as interface between the gate control signals and the power switches. It steps up the Transistor-Transistor Logic (TTL) voltage from the DS1104 DSP to a sufficient level, in order to completely turn on/off the power switches. Besides, it also provides electrical isolation between the electronic circuit and the power circuit. Figure 5.4 depicts the block diagram of the gate drive circuit. The detail schematic diagram of the gate drive circuit is shown in Appendix B.
TTL input
Dead-time generator
Gate drive optocoupler
To power switches
dc-dc converter Vdc
dc-ac converter
Rectifier and regulator
Miniature high-frequency transformer
Figure 5.4 : Block diagram of gate drive circuit In Figure 5.4, the dc-dc converter is used to produce a stable voltage supply for the gate driver. The isolated dc-dc converter is driven by the SG3526 pulse generator. The miniature high-frequency transformer is designed such that there are two secondary centre-tapped windings. This ensures two units of gate drive power supply to be constructed with minimum components. The transformer is wound around the EFD12 core (3C90). The output from the transformer is set at ± 15V using LM78L15ACZ (+15V) and LM79L15ACZ (-15V) voltage regulators. Dead-time is necessary to provide sufficient time for the power switches to completely turn off before the complimentary switch on the same leg of inverter bridge turns on. This prevents short circuit of power switches. Dead-time generator delays the pulse width with an amount of td before the control signals are sent to the
72 gate driver. Figure 5.5 shows the dead-time generator and its corresponding timing diagram. The value of td can be varied using the variable resistor R1. 74ACT14
1N4148
vi +
R1 vi
R2 C
vo
t
vo
-
t td
Figure 5.5 : Dead-time generator and its corresponding timing diagram Each power switch of the BHFL inverter is driven by a Hewlett-Packard gate driver chip, HCPL3120. This chip has a built-in optocoupler with power output stage, which is suited for directly driving Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). This “all-in-onechip” solution has simplified the interfacing process.
5.2.2 Power Circuit The power circuit is the key hardware component where energy conversion takes place. The high-frequency PWM bridge is constructed using the APT15GP60BDF1 power IGBT. It is a low conduction loss device with good switching capability. The transformer is wound on the ETD59 ferrite core. Ferrite core is chosen as it has low core loss at high operating frequency. The active rectifier’s switches are built using the IRG4PH40K IGBT and STTA1212D ultrafast high voltage diode. These power switches can withstand 1200V, thus suitable to be used at the centre-tapped active rectifier. The polarity-reversing bridge is constructed using the IRG4PC40FD IGBT. Since the surge voltages on the transformer secondary have been dampened by the regenerative snubber before entering the polarity-reversing bridge, the chosen power switches are only rated at 600V. Using low voltage IGBT, the forward conduction losses can be minimised.
73 5.2.3 Feedback Circuit The feedback circuit is used to measure the required parameters (current and voltage) from the power circuit, and feedback to the DSP for further processing. Hall-effect sensors, i.e. the HY10-P current sensors, and LV25-P voltage sensor, are selected for feedback signals measurement. The Hall-effect sensors provide galvanic isolation between the primary circuit (high power) and the secondary circuit (electronic circuit). Furthermore, they are highly immune to external interference. These features have simplified the design process of the feedback circuit. The block diagram in Figure 5.6 depicts the connection between the sensors and the power circuit. A ± 15V voltage supply is used to power the sensors. For the current sensor, the measured current is converted to a corresponding voltage, vmi. The relationship between the actual current and the measured output is given by: v mi = K si i
(5.1)
where Ksi is the current sensor gain. If HY10-P is used for measurements at nominal primary current, K si = 0.4 .
Current sensor HY10-P +
+15V
-
-15V
M 0V
Power circuit
+
+HT
-
i
vmi
+ R1
PI
v
PO
Voltage sensor LV25-P +HT
Load -HT
-HT
-
-15V
+
+15V
M
iS +
RM
vmv 0V
Figure 5.6 : Connection between sensors and power circuit
74 For the voltage sensor, the primary resistor R1 is selected such that the optimum accuracy can be obtained at the nominal primary current. With a supply voltage of ± 15V and measuring at the nominal primary current, the relationship between the actual voltage and the measured voltage can be written as:
v mv = K sv v
where K sv =
(5.2)
i SN RM is the voltage sensor gain; iSN is the nominal secondary current, v PN
RM is the measuring resistor, and vPN is the nominal primary voltage.
5.3
DS1104 Digital Signal Processor (DSP) Board The DS1104 is a real-time digital signal processor board based on PowerPC
technology (MPC8240 64-bit floating-point processor with PPC603e core running at 250MHz clock) [62]. The DS1104 serves as a platform for rapid control prototyping. It is interfaced to the computer via PCI slot. Figure 5.7 shows the photograph of DS1104 DSP board.
Figure 5.7 : DS1104 DSP board
75 Figure 5.8 shows the block diagram of DS1104 architecture. The built-in Analogue-to-Digital Converter (ADC), digital I/O and slave DSP subsystem (Texas Instruments’ TMS320F240) make the DS1104 an ideal single board solution to implement the digital controller for BHFL inverter. The hardware I/O pins of the DS1104 DSP can be accessed through the Sub-D connectors (labelled as P1A and P1B). For ease of connection between the DS1104 and the BHFL inverter, an interface panel has been constructed. The interface panel provides flexibility in system development and testing, where connections of an individual I/O pin can be easily modified. Figure 5.9 depicts the connections between the Sub-D connectors and the interface panel.
Figure 5.8 : Architecture of DS1104 DSP board
76
To DS1104
Sub-D connectors
PC where DS1104 is installed
To BHFL inverter Interface panel
Figure 5.9 : Interface panel between DS1104 and BHFL inverter Basically, there are two ways of creating real-time applications for the DS1104 DSP. First is using the Real-Time Interface (RTI)
4
[64] in
MATLAB/Simulink environment. The other method is direct handcode in C programming. RTI is the interface between Simulink and dSPACE platform. With RTI, Simulink’s large block library is enhanced by a specific dSPACE block library for the I/O hardware support. With these blocks, the real-time experiment set-up including the I/O initialisation can be built, without writing a single line of C code. This is because the C code is automatically generated by the Real-Time Workshop (embedded in MATLAB), in conjunction with dSPACE’s RTI. On the other hand, if the algorithm is written using C code, the C functions needed to access the hardware I/O can be found from the Real-Time Library (RTLib) 5 [65]. After the control algorithm is successfully compiled, built and downloaded to DS1104 DSP board, experiments can be carried out on the hardware. At this stage, the ControlDesk6 [66] can be used to control and monitor the experiment. Through the ControlDesk, virtual instrument panels are available to display waveforms, and online changing of parameters can be performed. These features provide flexibility to optimise the control designs and full control over experiments. The development steps of implementing a real-time application using the DS1104 DSP can be summarised in the flowchart of Figure5.10. 4
Real-Time Interface (RTI) is licensed software provided by dSPACE GmbH [63]. Real-Time Library (RTLib) is base software provided by dSPACE GmbH [63]. 6 ControlDesk is licensed experiment software provided by dSPACE GmbH [63]. 5
77 Implementation of real-time application
Real-Time Interface (RTI)
Handcode
Construct model in Simulink Set Configuration Parameters: - System target file: rti1104.tlc - Template makefile: rti1104.tmf - Make command: make_rti
Write C code using RTLib’s commands and functions
Download real-time application to DS1104 Experiments using ControlDesk - Start/stop real-time application - Managing and Instrumenting
Figure 5.10 : Flowchart of implementing real-time applications using DS1104 DSP
In essence, the control design for RTI method is model based. Therefore, the development time can be reduced. However, handcoding method provides full access and control over the programming execution order. Furthermore, code optimisation can be performed if required. With these considerations, the control algorithm in this research is written using C code. However, the corresponding RTI model is also developed for ease of explanation. This is because the block diagram model can be better visualised and understood. The C code for the proposed Deadbeat controller is listed in Appendix C.1. The corresponding RTI model is shown in Figure 5.11.
78
Figure 5.11 : Complete RTI model of the proposed Deadbeat controller
5.3.1 Gate Control Signals Generation There are three gate control signals applied to the BHFL inverter at the highfrequency PWM bridge (vpwm), active rectifier (vs) and polarity-reversing bridge (vu). These control signals are shown in Figure 5.12. The PWM signal vpwm and the unfolding signal vu are generated using the DS1104 DSP. This is performed by the PWM modulator in the slave DSP subsystem. As the active rectifier’s control signal vs is half the frequency of vpwm, it is generated using external frequency divider
circuit. This is to ensure exact synchronisation of the two signals.
79 vpwm t
vs
t
vu
t
Figure 5.12 : Gate control signals for the BHFL inverter
The frequency divider circuit is constructed using 74HCT112N JK flip-flop. Figure 5.13(a) shows the circuit configuration of the JK flip-flop operating as frequency divider. The associated timing diagram is shown in Figure 5.13(b). Referring to Figure 5.13, the flip-flop is loaded with the Set (S) and Reset (R) signals, and the inputs (J and K) are connected to logic ‘1’. As such, the flip-flop is triggered on the falling edge of the toggle input (T), producing an output pulse (Q) with frequency half that of toggle input (T). Table 5.1 summarised the states of the inputs and outputs of the JK flip-flop operating as frequency divider.
S ‘1’ J T
Q
T
Clk Q
K
t
Q
R
(a)
t
(b)
Figure 5.13 : JK flip-flop operating as frequency divider (a) circuit configuration (b) timing diagram
80
Table 5.1 : Function table of JK flip-flop operating as frequency divider Operating mode Toggle (freq. divider)
Inputs S
R
H
H
T
Outputs J
K
Q
Q
H
H
q
q
Legend: H
–
High voltage level
q
–
Lower case letters indicate the previous state prior to the High-to-Low T transition
–
High-to-Low T transition
5.3.2 Feedback Signal Conditioning The feedback signals are sent into the DS1104 DSP for processing through the ADCs. There are two types of ADCs provided by DS1104, namely the 16-bit multiplexed ADCs (4 channels), and the 12-bit parallel ADCs (4 ADCs). This means five ADCs can be utilised simultaneously (1 x 16-bit + 4 x 12-bit). In this research, there are three feedback signals required, thus only the 12-bit parallel ADCs are used. In C code, to read the value at one ADC channel, the ds1104_adc_read_ch function is used. Before using the read function, the ADC must be started by means of ds1104_adc_start function. Both of these functions are placed in the timer’s interrupt
service routine. In RTI model, to use one of the four parallel ADCs, the DS1104ADC_Cx block (x denotes the number of channel) is dragged and dropped
into the model, as shown in Figure5.11. Note that the return value of the ADC is scaled as shown in Table 5.2. Therefore, feedback gain for current loop is set at
K fi =
10 , where Ksi is the current sensor gain. The feedback gain for voltage loop K si
is set at K fv =
10 , where Ksv is the voltage sensor gain. K sv
81
Table 5.2 : Scaling between analogue input voltage and return value of ADCs Input voltage range
Return value range
-10V … +10V
-1.0 … +1.0
The feedback signals read by ADCs are sent through Infinite Impulse Response (IIR) digital filters [61] for noise filtering. The IIR digital filters are designed using the bilinear transformation method. The method maps the digital filter into an equivalent analogue filter. The latter can be designed by the welldeveloped analogue design methods. Then, the designed analogue filter is mapped back into the desired digital filter. Figure 5.14 shows the digital filter design procedure using bilinear transformation method. The detail design procedure for a first-order low-pass filter will be described in the following paragraph. A design example of the filter employed in this research will then be presented.
Digital filter specifications Bilinear transformation Ω = g (ω ) Analogue filter specifications Analogue filter design method Analogue filter F(s) Bilinear transformation s = h(z ) Digital filter F(z)
Figure 5.14 : Digital filter design procedure using bilinear transformation method For a first-order digital filter with cut-off frequency fc and operating at sampling frequency fs, the transfer function can be written as:
F1 ( z ) =
b0 + b1 z −1 1 + a1 z −1
(5.3)
82 The magnitude response of the digital filter is illustrated in Figure 5.15. The cut-off frequency, fc defines the range of frequencies that are passed through, that is 0 ≤ f ≤ f c , and the range of frequencies that are filtered out, that is f c ≤ f ≤
fs . 2
The digital cut-off frequency ωc in radian per sample is defined as:
ωc =
2πf c fs
(5.4)
2
More generally, ωc can be defined as the frequency at which F1 (ω ) drops by a 2
factor of Gc < 1 , or a drop in dB:
2
Ac = −10 log10 (Gc ) = −20 log10 Gc
(5.5)
which can be inverted to give:
⎛ A ⎞ Gc = antilog⎜ − c ⎟ ⎝ 20 ⎠
F1 ( f )
(5.6)
2
1
Ac dB
Gc 2
f
0
fc
fs 2
Figure 5.15 : Magnitude response of first-order digital filter
83 Using the bilinear transformation method, the digital cut-off frequency is prewarped to obtain the cut-off frequency of the equivalent analogue filter:
⎛ω ⎞ Ω c = tan ⎜ c ⎟ ⎝ 2 ⎠
(5.7)
Then, the first-order analogue filter is designed by adjusting its parameters to obtain the desired cut-off frequency, Ωc. Figure 5.16 depicts the transformation of the specifications. The transfer function of the analogue filter is:
F1 ( s ) =
α
(5.8)
s +α
The magnitude responses of the analogue filter is obtained by setting s = jΩ :
2
F1 (Ω) =
F1 (ω )
Desired digital low-pass filter
2
1 Gc
0
F1 (Ω)
ωc
(5.9)
2
Equivalent analogue low-pass filter
1
Ac dB
2
α2 Ω2 + α 2
Ac dB
Gc 2
π
ω
0
Ωc
Ω
Figure 5.16 : Equivalent cut-off specifications of low-pass digital and analogue filter
84 Referring to Figure 5.16, the filter parameter α can be determined by requiring the cut-off condition:
2
α2
2
F1 (ω c ) = F1 (Ω c ) =
2
Ωc + α
2
= Gc
2
(5.10)
which can be solved for α :
Gc
α=
1 − Gc
2
Ωc
(5.11)
Once the parameter α of the analogue filter is fixed, the filter can be transformed to the z-domain using bilinear transformation:
F1 ( z ) = F1 ( s ) s=
=
1− z −1 1+ z −1
α ⎛ 1 − z −1 ⎞ ⎜ ⎟ ⎜ 1 + z −1 ⎟ + α ⎝ ⎠
(5.12)
With further manipulations, the transfer function of the digital filter is obtained:
F1 ( z ) =
b(1 + z −1 ) 1 − az −1
(5.13)
where the filter coefficients are written in terms of α :
a=
α 1−α ,b = 1+α 1+α
(5.14)
85 A practical design example of the first-order digital low-pass filter applied in this research is as follows: Design specifications: -
Cut-off frequency, f c = 5kHz
-
Sampling frequency, f s = 25kHz
Design steps: i.
Determine digital cut-off frequency, ωc using equation (5.4).
ωc =
ii.
2πf c 2π (5kHz) = = 0.4π rad/sample fs 25kHz
Determine its prewarped analogue cut-of frequency, Ωc using equation (5.7).
⎛ω ⎞ Ω c = tan ⎜ c ⎟ = tan(0.4π ) = 0.7265 ⎝ 2 ⎠ iii.
Determine Gc using equation (5.6).
⎛ A ⎞ ⎛ 3 ⎞ Let Ac = 3dB , Gc = antilog⎜ − c ⎟ = antilog⎜ − ⎟ = 0.7071 ⎝ 20 ⎠ ⎝ 20 ⎠
iv.
Determine the analogue filter’s parameter, α using equation (5.11). As Gc = 0.7071 , equation (5.11) is simplified to α ≈ Ω c = 0.7265
v.
vi.
Determine digital filter coefficients using equation (5.14).
a=
1 − α 1 − 0.7265 = = 0.1584 1 + α 1 + 0.7265
b=
0.7265 α = = 0.4208 1 + α 1 + 0.7265
Finally, the digital filter is expressed by its transfer function. F1 ( z ) = 0.4208
1 + z −1 1 − 0.1584 z −1
86 The normalised magnitude response of the designed filter is plotted using MATLAB/Simulink, as shown in Figure 5.17. It can be seen that the filter’s characteristic is identical to the desired specifications in theoretical calculation.
Ac = 3dB, fc = 5kHz
fs = 12.5kHz 2
Figure 5.17 : Magnitude response of the designed filter In C code, the designed digital filter is realised in canonical form [61], as shown in Figure 5.18. Referring to equation (5.3), the sample processing algorithm can be written as: w0 (n) = x(n) − a1 w1 (n) y (n) = b0 w0 (n) + b1 w1 (n)
(5.15)
w1 (n + 1) = w0 (n)
where n is the number of sample (repeating integer); w0 and w1 are the internal states of the filter. The internal state vector w is realised by means of array [67], and must be allocated in the main program using the following command: w = (Float64 *) calloc(2, sizeof(Float64));
/* w = [w0, w1] */
87 IIR filter w0 (n)
Input x(n) +
b0
+
Output +
+
y (n)
z −1 w1 (n) − a1
b1
Figure 5.18 : Canonical realisation form of first-order IIR filter In RTI model, the digital filter can be realised using the Discrete Filter block from Simulink library. The desirable filter characteristic can be obtained by simply specifying the filter coefficients in the block. Note that this block is also employed in the simulation model. Therefore, the signal conditioning blocks constructed in simulation model can be directly downloaded into DS1104 DSP for real-time applications.
5.3.3 Multiloop Controller for BHFL Inverter Two sets of multiloop controller, i.e. the multirate digital controller, and the proposed Deadbeat controller have been implemented using the DS1104 DSP. The control performance of the controllers are evaluated and compared under various load conditions. The results and analyses will be presented in Chapter 6. The PWM modulator in the slave DSP subsystem is used to generate the PWM signal for both of the multiloop controllers. This significantly simplifies the generation process of PWM pulses. In C code, this is performed by using the ds1104_slave_dsp_pwm_duty_write function, to set the PWM duty cycle for the related PWM channel. Prior to accessing the slave DSP, the communication between the master PowerPC (main processor) and slave DSP is initialised using the ds1104_slave_dsp_communication_init function. This initialisation function must be performed at the beginning of every application accessing the slave DSP features.
88 For PWM generation, the PWM channels are initialised by means of ds1104_slave_dsp_pwm_init function. After the initialisation, the PWM generation is started by using the ds1104_slave_dsp_pwm_start function. The PWM write function
is
also
registered
in
the
command
table
using
the
ds1104_slave_dsp_pwm_duty_write_register function [65]. In RTI model, the PWM modulator is represented by the DS1104SL_DSP_PWM block, shown in Figure 5.11. The enable signals for the input and output relays, gate drives, and snubber circuit, as well as the control signals for external frequency divider circuit, are generated using the digital I/O unit. In C code, single bits of the digital I/O unit can be set or cleared using the ds1104_bit_io_set and ds1104_bit_io_clear functions, respectively. At the main body of the program, the relevant digital I/O pins are initialised using the ds1104_bit_io_init function. In RTI model, the digital I/O pins can be accessed via the DS1104_BIT_OUT_Cx block (x denotes the number of channel/bit), as shown in Figure 5.11.
5.3.3.1 Multirate Digital Controller The multirate digital controller has been implemented, where the sampling period of the voltage loop, Tv is set to twice the sampling period of current loop, Ti. The C code for the multirate digital controller is listed in Appendix C.2. The corresponding RTI model is shown in Figure 5.19. The detail of the “Multirate digital controller” block is depicted in Figure 5.20. Note that the RTI model of the controller is identical to the simulation model (Figure 4.9), except the control signal is sent to the DS1104SL_DSP_PWM block for real-time pulse generation.
89
Figure 5.19 : Complete RTI model of the multirate digital controller
Figure 5.20 : RTI model of the multirate digital controller
90
5.3.3.2 Proposed Deadbeat Controller The proposed Deadbeat controller has been implemented. Figure 5.21 shows the C code programming flowchart of the control algorithm.
Start Initialise hardware and software modules of DS1104
Generation of reference signal, vref Start ADCs and read feedback signals Signal conditioning Calculation of current and voltage disturbance decoupling network values (id , vd) Calculation of iref iref
